EE330 FINAL PROJECTabdelmagieed.weebly.com/.../presentation1.pdf · File Edit V ew Graph AXIS a 00...

EE330 FINAL PROJECT

Digital clock / Alarm

By: Abdelmagieed Ibrahim & Jie-Hue Yan

TA: Robert Buckley

Introduction

• In this project we design a digital clock with output of 4 seven segments. First 2 represent number of seconds , and the other 2 represent number of minutes. Also this project work as timer with Alarm output.

Components

• Ring oscillator

• Clock divider

• Up/Down counters

• BCD

• Decoders

• Outputs / inputs

• Control gates

Ring oscillator

Ring oscillator freq around 2.5Mhz

DFF to lower Frq

Clock divider

Clock divider output

Up counter

Single up counter output

BCD using 4 (4-bits up counter)

BCD using 4 (4-bits up counter)

2 cascade up counter output

4-bits Down-counter

Down counter output (start at 9 instead 15)

BCD using 4 (4-bit down counter)

Decoder ( 4in (bcd) , 7 out (7seg))

UP counter Or down counter

BUZZ output

Layout

DRC & LVS