Xilinx Training Courses

Xilinx Training Course Listing

Effective January 1, 2013

Overview.........................................................................................................................................................1

XilinxTrainingCourseListing.....................................................................................................................2

CoreDesignSkills........................................................................................................................................3

ProductTraining............................................................................................................................................4

SpecialtyDesignSkills.................................................................................................................................6

PointTechnologies.......................................................................................................................................9

Languages....................................................................................................................................................10

XilinxWorldwideTraining..........................................................................................................................11

AdditionalTrainingResources..................................................................................................................11

TABLE OF CONTENTS

1

OVERVIEW

The Design Challenges of Time and Complexity• Systemdesignersarefacedwithtworapidlygrowingchallenges:shrinking time-to-marketproductdevelopmentcycles;andtheincreasingcomplexity ofproductdesign• Today’scompetitiveenvironmentdemandsthetimely,efficientdelivery ofyourmostinnovativesolutions• Tobeatthecompetition,youmustbeonbudget,ontime,everytime

Xilinx Training— Training Solutions that Put You On The Fast Track to SuccessXilinxprovidestargeted,high-qualitytrainingdesignedbyexpertsinprogrammablelogicdesign,anddeliveredbyXilinxqualifiedtrainers.Weofferinstructor-ledclassesandrecordede-learningforself-pacedtraining.Somecoursesarecompletelyfree!Tosignupforaclassortofindoutmoregotowww.xilinx.com/training.

Xilinx Productivity Advantage (XPA)— Everything You Need in a Customizable BundleTheXilinxProductivityAdvantage(XPA)programallowsyoutocreatecustomizedbundlesofsoft-wareandservicestomeetthespecificneedsofyourteam.AnXPAprovidesforallofyourFPGAdesignneedsup-frontthroughaonestopshoppingexperience.Thissolutionbundleincludesaccessto:

• Trainingcreditsthatcanbeappliedtowardsacomprehensiveportfolioofhands-on trainingledbyexpertinstructors.• Allofyouruserlicensesfortheindustry-leadingISE™designtoolsanddevelopment systemoptions.• Pre-verifiedandpre-optimizedIntellectualProperty(IP)coresandreferencedesigns forXilinxFPGAs.• Completesuiteofdevelopmentandevaluationboardscustomizedforyourteam’sneeds.

TofindouthowyoucanbenefitfromanXPAgotowww.xilinx.com/xpa.

2

XILINX TRAINING COURSE LISTING

Xilinxofferspublic,privateandonlinetrainingavailableworldwidesoyoucanbesuretofindatrainingthatbestfitsyourneeds.SeebelowforadetaileddescriptionofallofthecoursesofferedbyXilinx.

CoreDesignSkills

Keyforalldesigners.Focusesontools,architecture,andmethodology.FrombestpracticeFPGAdesigntechniquesthroughadvancedskillsandmethodologytomeetyourdesigngoals.

XilinxRecommendedDesignMethodologyVivadoDesignFlows-Page3ISEDesignFlows-Page3

ProductTraining

Latestproducttraining.Focusedonin-depthtrainingtobecomeproficientusingtheseproductsintheminimumtimepossible.IncludesallnewHWandSWproducts

VivadoToolFlows-Page4ISEToolFlows-Page47-Series-Page46-Series-Page4ZynqAllProgrammableSOC-Page5

SpecialtyDesignSkills

FocusedtrainingaroundspecifictypesofFPGAdesign.DSPforvideoandcommunicationmarkets.Connectivityforhigh-speedinterfacesandEmbeddeddesignforBOMreductionandsystemintegrationineverymarketandapplication.

EmbeddedDesign-Page6DSPDesign-Page7ConnectivityDesign-Pages7-8

PointTechnologies

TrainingrequiredonpointtechnologysolutionsasHigh-LevelSynthesis,AMStechnologyforADC,PartialReconfiguration,Memory,powerOptimization,andOn-ChipDebug.

Low-Power-Page9Debug-Page9AnalogMixedSignal-Page9PartialReconfiguration-Page9

Languages

FocusonlanguageskillsneededtocreatereliableandoptimalhardwareusingXilinxdesigntools.includesHardwareDescriptionLanguages(HDLs),suchasVerilog,SystemVerilog,andVHDL,Tclscriptinglanguage,andClanguage.

C-Page10Tcl-Page10VerilogandSystemVerilog-Page10VHDL-Page10

3

CORE DESIGN SkILLS

Vivado Design Flows

Essentials of FPGA Design Level: 2 Duration: 2 daysBuildaneffectiveFPGAdesignusingsynchronousdesigntechniques,instantiateappropriatedeviceresources,useproperHDLcodingtechniques,makegoodpinassignments,setbasicXDCtimingconstraints,andusetheVivado™DesignSuitetobuild,synthesize,implement,anddownloadadesign.

Vivado Design Suite Static Timing Analysis and Design Constraints

Level: 3 Duration: 2 days

ThiscourseoffersdetailedtrainingontheVivadosoftwaretoolflow,Xilinxdesignconstraints(XDC),andstatictiminganalysis(STA).LearntousegoodFPGAdesignpracticesandallFPGAresourcestoadvantage.Learntofullyandappropriatelyconstrainyourdesignbyusingindustry-standardXDCconstraints.LearnhowthetheVivadoIDEdesigndatabaseisstructuredandlearntotraversethedesign.CreateappropriatetimingreportstoperformfullSTAandhowtoappropriatelysynthesizeyourdesign.

Advanced Tools and Techniques of Vivado Design Suite

Level: 4 Duration: 1 day

ThiscourseoffersdetailedtrainingontheVivadosoftwaretoolflow,Xilinxdesignconstraints(XDC),andstatictiminganalysis(STA).LearntousegoodFPGAdesignpracticesandallFPGAresourcestoadvantage.Learntofullyandappropriatelyconstrainyourdesignbyusingindustry-standardXDCconstraints.LearnhowthetheVivadoIDEdesigndatabaseisstructuredandlearntotraversethedesign.CreateappropriatetimingreportstoperformfullSTAandhowtoappropriatelysynthesizeyourdesign.

ISE Design Flows

FPGA Design Techniques for Lower Cost

Level: 2 Duration: 1 day

Thiscoursewillappealtoengineerswhohaveaninterestindevelopinglow-costproducts,particularlyinhigh-volumemarkets.Thecourseandexercisescoverseveraldifferentdesigntechniques,whichwillbeinterestingandchallengingforanydigitaldesignerregardlessofthefinalapplication.

Essentials of FPGA Design Level: 2 Duration: 1 dayUsetheISE®softwaretoolstoimplementanFPGAdesignandgainafirmunderstandingoftheXilinxFPGAarchitecture.LearnthebestdesignpracticesfromtheprosandunderstandthesubtletiesoftheXilinxdesignflow.ThiscoursecoversISEsoftwarefeaturessuchastheArchitectureWizard,I/OPlanner,andtheConstraintsEditor.OthertopicsincludeFPGAarchitecture,gooddesignpractices,understandingreportcontents,andglobaltimingconstraints.

Designing for Performance Level: 3 Duration: 2 daysAttendingtheDesigningforPerformanceclasswillhelpyoucreatemoreefficientFPGAdesigns.ThiscoursewillenableyoutooptimizeyourdesignforusageinasmallerFPGAoralowerspeedgradeforreducingsystemcosts.Inaddition,bymasteringthetoolsandthedesignmethodologiespresentedinthiscourse,youwillbeabletocreateyourdesignfaster,shortenyourdevelopmenttime,andlowerdevelopmentcosts.

Advanced FPGA Implementation Level: 4 Duration: 2 daysAdvancedFPGAImplementationtacklesthemostsophisticatedaspectsoftheISEdesignsuiteandXilinxhardware.Labsprovidehands-onexperienceinthistwo-daytrainingandcovertheXilinxSynthesisTechnology(XST)tools.ThiscourserequirestheEssentialsofFPGADesignandDesigningforPerformancecoursesasprerequisites.AnintermediateknowledgeofVerilogorVHDLisstronglyrecommendedasisatleastsixmonthsofdesignexperiencewithXilinxtoolsandFPGAs.ThelecturematerialinthiscoursecoverstheISEtoolsand7seriesFPGAs.

4

PRODUCT TRAINING

Vivado Tool Flows

Vivado Design Suite Tool Flow Level: 1 Duration: 1 dayThiscourseprovidestheoverallcontextandframeworkforthedevelopmentcycleofFPGAs.ForthoseuninitiatedtoFPGAdesign,thiscoursewillarmyouwiththeproperplanningtechniques,strategy,andFPGAtoolflowtogetupanddesigninganFPGAdesignnow.TheflowwilltakeyoufrombehavioralspecificationtotuningspecificationsfortheFPGA,synthesis,verification,andontoimplementationanddownload.Throughoutthedesigncycle,thevarioustoolswithintheVivado™DesignSuiteareintroduced.

Vivado Design Suite for ISE Project Navigator Users

Level: 2 Duration: 1 day

ThiscourseoffersintroductorytrainingontheVivadoDesignSuite.ThiscourseisforexperiencedISEsoftwareuserswhowanttotakefulladvantageoftheVivadoDesignSuitefeatureset.LearnabouttheVivadoDesignSuiteprojects,designflow,Xilinxdesignconstraints,andbasictimingreports.

Vivado Design Suite–Advanced XDC and Timing Analysis for ISE Users

Level: 2 Duration: 2 days

ThiscoursewillupdateexperiencedISEsoftwareuserstoutilizetheVivadoDesignSuite.Learntheunderlyingdatabaseandstatictiminganalysis(STA)mechanisms.UtilizeTclfornavigatingthedesign,creatingXilinxdesignconstraints(XDC),andcreatingtimingreports.LearntomakeappropriatetimingconstraintsforSDR,DDR,source-synchronous,andsystem-synchronousinterfacesforyourFPGAdesign.

ISE Tool Flows

ISE Design Tool Flow Level: 1 Duration: 1 dayISEDesignToolFlowprovidestheoverallcontextandframeworkforthedevelopmentcycleofFPGAs.ForthoseuninitiatedtoFPGAdesign,thiscoursewillarmyouwiththeproperplanningtechniques,strategy,andFPGAtoolflowtogetupanddesigninganFPGAdesignnow.TheflowwilltakeyoufrombehavioralspecificationtotuningspecificationsfortheFPGA,synthesis,verification,andontoimplementationanddownload.Throughoutthedesigncycle,thevarioustoolswithintheProjectNavigatortoolareintroduced.

Essential Design with the PlanAhead Analysis and Design Tool

Level: 2 Duration: 1 day

Learntomanagedesignperformance,plananI/Opinlayout,andimplementbyusingthePlanAhead™softwaretool.Topicsinclude:atooloverview,runningaDesignRuleCheck(DRC)andSimultaneousSwitchingNoise(SSN)analysisofpinassignments,designandtiminganalysis,creatingcores,andcompletingsynthesisandimplementationwiththePlanAheadtool.

Advanced Design with the PlanAhead Analysis and Design Tool

Level: 3 Duration: 2 days

LearntoincreasedesignperformanceandachieverepeatableperformancebyusingthePlanAheadsoftwaretool.Topicsinclude:synthesisandprojecttips,designanalysis,creatingafloorplan,improvingperformancewithareaconstraintsandPblocks,designdebuggingwiththeChipScope™Protool,anddesignpreservationwithpartitions.

7-Series

Designing with the 7 Series Families Level: 3 Duration: 2 daysAreyouinterestedinlearninghowtoeffectivelyutilize7seriesarchitecturalresources?ThiscoursesupportsbothexperiencedandlessexperiencedFPGAdesignerswhohavealreadycompletedtheEssentialsofFPGADesigncourse.Thiscoursefocusesonunderstandingaswellashowtoproperlydesignfortheprimaryresourcesfoundinthispopulardevicefamily.Topicscoveredincludedeviceoverviews,CLBconstruction,MMCMandPLLclockingresources,global,regionalandI/Oclockingtechniques,memory,FIFOresources,DSP,andsource-synchronousresources.Memorycontrollersupportandthededicatedhardwareresourcesavailableineachofthefamilies(PCIExpresstechnology,analogtodigitalconvertersandgigabittransceivers)arealsointroduced.ThiscoursealsoincludesadetaileddiscussionaboutproperHDLcodingtechniquesthatenablesdesignerstoavoidcommonmistakesandgetthemostoutoftheirFPGA.Acombinationofmodulesandlabsallowforpracticalhands-onapplicationoftheprinciplestaught.

6-Series

Designing with the Spartan-6 and Virtex-6 Families

Level: 3 Duration: 2 days

AreyouinterestedinlearninghowtoeffectivelyutilizeSpartan®-6orVirtex®-6FPGAarchitecturalresources?ThiscoursesupportsbothexperiencedandlessexperiencedFPGAdesignerswhohavealreadycompletedtheEssentialsofFPGADesigncourse.Thiscoursefocusesonunderstandingaswellashowtoproperlydesignfortheprimaryresourcesfoundinthesepopulardevicefamilies.Topicscoveredincludedeviceoverviews,CLBconstruction,DCMandPLLclockingresources,global,regionalandI/Oclockingtechniques,memory,DSP,andsource-synchronousresources.Memorycontrollersupportandthededicatedhardwareresourcesavailableineachofthesub-families(EMAC,PCIExpress®technology,andGTPtransceivers)arealsointroduced.ThiscoursealsoincludesadetaileddiscussionaboutproperHDLcodingtechniquesthatenablesdesignerstoavoidcommonmistakesandgetthemostoutoftheirFPGA.Acombinationofmodulesandlabsallowforpracticalhands-onapplicationoftheprinciplestaught.Atwo-daySpartan-6familyonlycourseortwo-dayVirtex-6familyonlycourseisalsoavailable.

PRODUCT TRAINING

Zynq All Programmable SOC

Introduction to the Zynq All Programmable SoC Architecture

Level: 3 Duration: 1 day

ThiscourseprovideshardwareandfirmwareengineerswiththeknowledgetoeffectivelyutilizeaZynq™AllProgrammableSystemonaChip(SoC).ItcoversthearchitectureoftheARM®Cortex™-A9processor-basedprocessingsystem(PS)andtheintegrationofprogrammablelogic(PL).ThecoursealsodetailstheindividualcomponentsthatcomprisethePS,I/Operipherals,timers,andcaching,aswellastheDMA,interrupt,andmemorycontrollers.EmphasiswillbeplacedoneffectiveaccessandusageofthePSDDRcontrollerfromPLuserlogic,efficientPL-to-PSinterfacing,anddesigntechniques.

Zynq All Programmable SoC System Architecture

Level: 3 Duration: 2 days

TheXilinxZynqAllProgrammableSystemonaChip(SoC)providesanewlevelofsystemdesigncapabilities.ThiscourseprovidesexperiencedsystemarchitectswiththeknowledgetoeffectivelyarchitectaZynqAllProgrammableSoC.ThiscoursepresentsthefeaturesandbenefitsoftheZynqarchitectureformakingdecisionsonarchitectingaZynqAllProgrammableSoCproject.ItcoversthearchitectureoftheARMCortex-A9processor-basedprocessingsystem(PS)andtheintegrationofprogrammablelogic(PL)atasufficientlydeeplevelthatasystemdesignercansuccessfullyandeffectivelyutilizetheZynqAllProgrammableSoC.ThecoursealsodetailstheindividualcomponentsthatcomprisethePS,I/Operipherals,timers,andcaching,aswellastheDMA,interrupt,andmemorycontrollers.EmphasiswillbeplacedoneffectiveaccessandusageofthePSDDRcontrollerfromPLuserlogic,efficientPL-to-PSinterfacing,anddesigntechniques,tradeoffs,andadvantagesofimplementingfunctionsinthePSorthePL.

5

SPECIALTY DESIGN SkILLS

Embedded Design

Essentials of Microprocessors Level: 1 Duration: 2 daysLearnwhatmakesmicroprocessorstick!Thisclassoffersinsightsintoallmajoraspectsofmicroprocessors,fromregistersthroughcoprocessorsandeverythinginbetween.DifferencesbetweenRISCandCISCarchitecturesareexploredaswellastheconceptofinterrupts.Agenericmicroprocessorisprogrammedandruninsimulationtoreinforcetheprincipleslearnedinthelecturemodules.ThestudentwillleavetheclasswellpreparedfortheXilinxZynqtrainingcurriculum.

How to Design Xilinx Embedded Systems in One Day

Level: 2 Duration: 1 day

TheworkshopintroducesyoutofundamentalembeddeddesignconceptsandtechniquesforimplementationinXilinxFPGAs.ThefocusisonfundamentalaspectsofXilinxembeddedtools,IP,andtheEmbeddedTargetedReferenceDesign(TRD).DesignexamplesandlabsaredrawnfromtheEmbeddedTRD.Onlyessentialtheoryisintroducedinordertolayafoundationforthematerialandtopicscoveredinthisworkshop,whichcomplementsmoredetailedtrainingfoundinsubsequentXilinxcourses.

Embedded Systems Design Level: 3 Duration: 2 daysTheXilinxZynqAllProgrammableSystemonaChip(SoC)providesanewlevelofsystemdesigncapabilities.ThiscoursebringsexperiencedFPGAdesignersuptospeedondevelopingembeddedsystemsusingtheEmbeddedDevelopmentKit(EDK).ThefeaturesandcapabilitiesoftheZynqAllProgrammableSoCaswellasconcepts,tools,andtechniquesareincludedinthelecturesandlabs.Thehands-onlabsprovidestudentswithexperiencedesigning,expanding,andmodifyinganembeddedsystem,includingaddingandsimulatingacustomAXI-basedperipheral.Additionally,thefeaturesandcapabilitiesoftheXilinxMicroBlaze™softprocessorarealsoincludedinthelecturesandlabs.

Embedded Systems Software Design Level: 3 Duration: 2 days

Thistwo-daycourseintroducesyoutosoftwaredesignanddevelopmentfortheXilinxZynqAllProgrammableSystemonaChip(SoC)usingtheXilinxSoftwareDevelopmentKit(SDK).Youwilllearntheconcepts,tools,andtechniquesrequiredforthesoftwarephaseofthedesigncycle.Topicsarecomprehensive,coveringthedesignandimplementationoftheboardsupportpackage(BSP)forresourceaccessandmanagementoftheXilinxStandalonelibrary.Majortopicsincludedevicedriveruseandcustomdevelopmentanduserapplicationdebuggingandintegration.Practicalimplementationtipsandbestpracticesarealsoprovidedthroughouttoenableyoutomakegooddesigndecisionsandkeepyourdesigncyclestoaminimum.YouwillhaveenoughpracticalinformationtostartdevelopingsoftwareapplicationsfortheARMCortex-A9andMicroBlazeprocessors.Additionally,thiscoursecoversdevelopingsoftwareapplicationsforaXilinxembeddedsystembasedonaMicroBlazeprocessor.

Advanced Features and Techniques of Embedded Systems Design

Level: 4 Duration: 2 days

AdvancedFeaturesandTechniquesofEmbeddedSystemsDesignprovidesembeddedsystemsdevelopersthenecessaryskillstodevelopcomplexembeddedsystemsandenablesthemtoimprovetheirdesignsbyusingthetoolsavailableintheEmbeddedDevelopmentKit(EDK).ThiscoursealsohelpsdevelopersunderstandandutilizeadvancedcomponentsofembeddedsystemsdesignforarchitectingacomplexsystemintheZynqAllProgrammableSystemonaChip(SoC)orMicroblazesoftprocessor.ThiscoursebuildsontheskillsgainedintheEmbeddedSystemsDesigncourse.Labsprovidehands-onexperiencewithdeveloping,debugging,andsimulatinganembeddedsystem.Utilizingmemoryresourcesandimplementinghigh-performanceDMAarealsocovered.Labsusedemoboardsinwhichdesignsaredownloadedandverified.

Advanced Features and Techniques of Embedded Systems Software Design

Level: 4 Duration: 1 day

ThiscoursewillhelpsoftwareengineersfullyutilizethecomponentsavailableintheZynqAllProgrammableSystemonaChip(SoC)processingsystem(PS).ThiscoursecoversadvancedZynqAllProgrammableSoCtopicsforthesoftwareengineer,includingadvancedbootmethodology,theNEONco-processor,programmingPSsystem-levelfunctioncontrolregisters,thegeneralinterruptcontroller,theDMA,Ethernet,andUSBcontrollers,andthevariouslow-speedperipheralsincludedintheZynqprocessingsystem.

Embedded Design with PetaLinux SDk Level: 4 Duration: 2 daysThisintermediate-level,two-daycourseprovidesembeddedsystemsdeveloperswithexperienceincreatinganembeddedPetaLinuxSDKoperatingsystemonaXilinxZynqAllProgrammableSystemonaChip(SoC)processordevelopmentboard.Thecourseoffersstudentshands-onexperienceonbuildingtheenvironmentandbootingthesystemusingabasicZynqAllProgrammableSoCdesignwithPetaLinuxSDKontheARMCortex-A9processor.ThiscoursealsointroducesembeddedLinuxcomponents,useofopen-sourcecomponents,environmentconfigurations,networkcomponents,anddebugging/profilingoptionsforembeddedLinuxplatforms.TheprimaryfocusisonembeddedLinuxdevelopmentinconjunctionwiththeXilinxtoolflow.

6

SPECIALTY DESIGN SkILLS

DSP Design

How to Design a Xilinx Digital Signal Processing System in One Day

Level: 3 Duration: 1 day

TheworkshopintroducesyoutofundamentalDSPconcepts,algorithms,andtechniquesforimplementationinXilinxFPGAs.Designexamplesandlabsaredrawnfromseveralcommonapplicationsspaces,includingwirelesscommunications,video,andimaging.Onlyessentialtheoryisintroducedinordertolayafoundationforthematerialandtopicscoveredinthisworkshop,whichcomplementsmoredetailedtrainingfoundinsubsequentXilinxcourses.ThematerialisalsocomplementarytotheAvnetSpeedWayDesignWorkshoponFPGA-BasedSystemDesignwithHigh-SpeedDataConverters.

Essential DSP Implementation Techniques for Xilinx FPGAs

Level: 3 Duration: 2 days

ThiscourseprovidesafoundationforDigitalSignalProcessing(DSP)techniquesforXilinxFPGAs.Thecoursebeginswitharefresherofbasicbinarynumbertheory,mathematics,andtheessentialfeatureswithintheFPGAthatareimportanttosignalprocessing.ThebodyofthecourseexploresavarietyoffiltertechniqueswithemphasisonoptimalimplementationinXilinxdevicesandcontinueswithanexaminationofFFTs,video,andimageprocessing.Throughoutthecourse,XilinxcoresandIPrelevanttosignalprocessingareintroduced.Thecourseiscomplementedbyhands-onexercisestoreinforcetheconceptslearned.

DSP Design Using System Generator Level: 3 Duration: 2 daysThiscourseallowsyoutoexploretheSystemGeneratortoolandtogaintheexpertiseyouneedtodevelopadvanced,low-costDigitalSignalProcessingdesigns.ThisintermediatecourseinimplementingDSPfunctionsfocusesonlearninghowtouseSystemGeneratorforDSP,designimplementationtools,andhardwareco-simulationverification.Throughhands-onexercises,youwillimplementadesignfromalgorithmconcepttohardwareverificationbyusingXilinxFPGAcapabilities.

C-Based Design: High-Level Synthesis with Vivado HLS

Level: 3 Duration: 2 days

ThecourseprovidesathoroughintroductiontoVivadoHLS(high-levelsynthesis).Thiscoursecoverssynthesisstrategies,features,improvingthroughput,area,interfacecreation,latency,testbenchcoding,andcodingtips.UtilizeVivadoHLStooptimizecodeforhigh-speedperformanceinanembeddedenvironmentanddownloadforin-circuitvalidation.

Connectivity Design

How to Design a Xilinx Connectivity System in One Day

Level: 2 Duration: 1 day

ThisworkshopintroducesyoutofundamentalconnectivityconceptsandtechniquesforimplementationinXilinxFPGAs.Thefocusisonfundamentalaspectsoftransceivers,PCIe®technology,memoryinterfaces,andEthernetMACs.Onlyessentialtheoryisintroducedinordertolayafoundationforthematerialandtopicscoveredinthisworkshop,whichcomplementsmoredetailedtrainingfoundinsubsequentXilinxcourses.DesignexamplesandlabsaredrawnfromtheConnectivityTargetedReferenceDesign(TRD).Inaddition,anIBERTlabisavailablethathighlightsuseoftheMGT.

PCIe Protocol Overview Level: 2 Duration: 1 dayThiscoursefocusesonthefundamentalsofthePCIExpressprotocolspecification.ThetypicalPCIearchitecture,includingdataspace,datamovement,andthemostcommonlyusedTransactionLayerPackets(TLPs)arecovered.Interruptsanderrorhandlingarealsodiscussed.

Designing a LogiCORE PCI Express System Level: 3 Duration: 2 daysAttendingtheDesigningaLogiCOREPCIExpressSystemwillprovideyouaworkingknowledgeofhowtoimplementaXilinxPCIExpresscoreinyourapplications.ThiscoursefocusesontheimplementationofaXilinxPCIExpresssystemwithintheConnectivityTargetedReferenceDesign(TRD).Withthisexperience,youcanimproveyourtimetomarketwithyourPCIecoredesign.VariousXilinxPCIExpresscoreproductswillbeenumeratedtoaidyouinselectingthepropersolution.ThiscoursefocusesontheAXIstreaminginterconnect.

Designing with Multi-Gigabit Serial I/O Level: 3 Duration: 3 daysLearnhowtoemployGTPandGTXserialtransceiversinyour7seriesFPGAdesign.Understandandutilizethefeaturesoftheserialtransceiverblocks,suchas8B/10Band64B/66Bencoding,channelbonding,clockcorrection,andcommadetection.AdditionaltopicsincludeuseoftheArchitectureWizard,synthesisandimplementationconsiderations,boarddesignasitrelatestothetransceivers,andtestanddebugging.Thiscoursecombineslectureswithpracticalhands-onlabs.

Designing with Ethernet MAC Controllers Level: 3 Duration: 2 daysBecomeacquaintedwiththevarioussolutionsthatXilinxoffersforEthernetconnectivity.LearnthebasicsoftheEthernetstandard,protocol,andOSImodelwhileapplyingXilinxsolutionsviahands-onlaboratoryexercises.Performsimulationtounderstandfundamentalprinciplesandobtaintheknowledgetoassesshardwaredesignconsiderationsandsoftwaredevelopmentrequirements.

7

8

SPECIALTY DESIGN SkILLS

Connectivity Design

Signal Integrity and Board Design for Xilinx FPGAs

Level: 3 Duration: 3 days

Learnwhenandhowtoapplysignalintegritytechniquestohigh-speedinterfacesbetweenXilinxFPGAsandothercomponents.Thiscomprehensivecoursecombinesdesigntechniquesandmethodologywithrelevantbackgroundconceptsofhigh-speedbusandclockdesign,includingtransmissionlinetermination,loading,andjitter.YouwillworkwithIBISmodelsandcompletesimulationsusingMentorGraphicsHyperLynx.OthertopicsincludemanagingPCBeffectsandon-chiptermination.Thiscoursebalanceslecturemoduleswithinstructordemonstrationsandpracticalhands-onlabs.

How to Design a High-Speed Memory Interface

Level: 3 Duration: 2 days

Thiscourseteacheshardwaredesignerswhoarenewtohigh-speedmemoryI/OtodesignamemoryinterfaceinXilinxFPGAs.Itintroducesdesignerstothebasicconceptsofhigh-speedmemoryI/Odesign,implementation,anddebuggingusing7seriesFPGAs.Additionally,studentswilllearnaboutthetoolsavailableforhigh-speedmemoryinterfacedesign,debug,andimplementationofhigh-speedmemoryinterfaces.ThemajormemorytypescoveredareDDR2andDDR3.Thefollowingmemorytypesarecoveredondemand:RLDRAMII,LPDDR,andQDRII+.LabsareavailableforDDR3ontheKintex™-7FPGAKC705board.

Signal Integrity and Board Design for Xilinx FPGAs

Level: 3 Duration: 3 days

Learnwhenandhowtoapplysignalintegritytechniquestohigh-speedinterfacesbetweenXilinxFPGAsandothercomponents.Thiscomprehensivecoursecombinesdesigntechniquesandmethodologywithrelevantbackgroundconceptsofhigh-speedbusandclockdesign,includingtransmissionlinetermination,loading,andjitter.YouwillworkwithIBISmodelsandcompletesimulationsusingMentorGraphicsHyperLynx.OthertopicsincludemanagingPCBeffectsandon-chiptermination.Thiscoursebalanceslecturemoduleswithinstructordemonstrationsandpracticalhands-onlabs.

How to Design a High-Speed Memory Interface

Level: 3 Duration: 2 days

Thiscourseteacheshardwaredesignerswhoarenewtohigh-speedmemoryI/OtodesignamemoryinterfaceinXilinxFPGAs.Itintroducesdesignerstothebasicconceptsofhigh-speedmemoryI/Odesign,implementation,anddebuggingusing7seriesFPGAs.Additionally,studentswilllearnaboutthetoolsavailableforhigh-speedmemoryinterfacedesign,debug,andimplementationofhigh-speedmemoryinterfaces.ThemajormemorytypescoveredareDDR2andDDR3.Thefollowingmemorytypesarecoveredondemand:RLDRAMII,LPDDR,andQDRII+.LabsareavailableforDDR3ontheKintex-7FPGAKC705board.

9

POINT TECHNOLOGIES

FPGA Power Optimization Level: 2 Duration: 1 dayAttendingtheFPGAPowerOptimizationclasswillhelpyoucreateamorepowerefficientFPGAdesign.ThiscoursecanhelpyoufityourdesignintoasmallerFPGA,reduceyourFPGA’spowerconsumption,orrunyourFPGAatalowertemperature.Inaddition,bymasteringthetoolsanddesignmethodologiespresentedinthiscourse,youwillbeabletocreateyourdesignfaster,shortenyourdevelopmenttime,andlowerdevelopmentcosts.

Debugging Techniques Using the ChipScope Pro Tools

Level: 2 Duration: 2 days

AsFPGAdesignsbecomeincreasinglymorecomplex,designerscontinuelooktoreducedesignanddebugtime.Thepowerful,yeteasy-to-useChipScope™Protoolsolutionhelpsminimizetheamountoftimerequiredforverificationanddebug.Thistwo-daycoursewillnotonlyintroduceyoutothecoresandtoolsandillustratehowtousethetriggerseffectively,butalsoshowyoueffectivewaystodebuglogicandhigh-speeddesigns—therebydecreasingyouroveralldesigndevelopmenttime.Thistrainingwillprovidehands-onlabsthatdemonstratehowtheChipScopeProtoolscanaddressadvancedverificationanddebuggingchallenges.

Designing with the Xilinx Analog Mixed Signal Solution

Level: 3 Duration: 1 day

ThiscourseintroducestheXilinxAnalogMixedSignal(AMS)solutionandtheappropriatetoolsandtechniquesforhardwareengineersandanalogengineerstoutilizethissolution.Thecompletefront-to-backdesignflowiscovered,includingtheevaluationoftheXilinxAnalog-to-DigitalConverter(XADC)blockutilizingtheKC705boardandtheevaluatoradd-oncard,thevariouswaystoincludetheXADCinyourdesign,XADCsimulationofananaloginput,viewingthedigitaloutput,andimplementation.Additionally,labsareprovidedthatsupporteachtopic,includingthecompeteflow.

Xilinx Partial ReconfigurationTools and Techniques

Level: 4 Duration: 2 days

ThiscoursedemonstrateshowtousetheISE,PlanAhead,andEmbeddedDevelopmentKit(EDK)softwaretoolstoconstruct,implement,anddownloadaPartiallyReconfigurable(PR)FPGAdesign.YouwillgainafirmunderstandingofPRtechnologyandlearnhowsuccessfulPRdesignsarecompleted.YouwillalsoidentifybestdesignpracticesandunderstandthesubtletiesofthePRdesignflow.ThiscoursecoversboththetoolflowandmechanicsofsuccessfullycreatingaPRdesign.ItalsodescribesseveraltechniquesfocusingonappropriatecodingstylesforaPRsystemaswellassystem-leveldesignconsiderationsandpracticalapplications.

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LANGUAGES

C

C Language Programming with SDk Level: 1 Duration: 2 daysThiscourseisbrokenintoadayofClanguagereview,includingvariablenaming,usage,andmodifiersaswellasanintroductiontotheSoftwareDevelopmentKit(SDK)environment,anexplanationoftheuseofthepreprocessors,programcontrol,andproperuseoffunctions.TheseconddayconsistsofcommonissuesandtechniquesemployedbyembeddedprogrammersintheXilinxSDKenvironment.Thiscomprehensivecourseequallybalanceslecturemoduleswithpracticalhands-onlabwork.

C-based HLS Coding for Hardware Designers

Level: 3 Duration: 1 day

C-basedcodingisincreasinglyusedforthemodelingandhigh-levelsynthesisofhardwarecomponents.ThiscourseprovideshardwareengineerswithsufficientknowledgeofC-programmingtechniquesforVivadoHLStotakeadvantageofXilinxFPGAs.Learnhigh-levelsynthesisbestpractices,methodology,andsubtletiesofC-basedcodingforhardwaremodeling,synthesis,andverification.

C-Based HLS Coding for Software Designers

Level: 3 Duration: 1 day

C-basedcodingisincreasinglyusedforthemodelingandhigh-levelsynthesisofhardwarecomponents.ThiscourseprovidessoftwareengineerswithsufficientknowledgeofFPGAhardwaretoefficientlycodeforhigh-levelsynthesis.Learnthehigh-levelsynthesisbestpractices,methodology,andsubtletiesofC-basedcodingforhardwaremodeling,synthesis,andverification.

Tcl

Essential TCL Scripting Level: 1 Duration: 1 dayLearnhowtousebasicTclsyntaxandlanguagestructurestobuildscriptssuitableforusewithXilinxFPGAdesigntools.Learnabouttheeffectiveuseofvariables,datatypes,andTclconstructstobuildeffectiveconditionalstatementsandloopcontrols.YouwillalsohavetheopportunitytouseTcllanguageconstructswithseverallabsdesignedtoprovideyouscriptingexperiencewithintheVivadoDesignSuite.

Verilog and System Verilog

Designing with Verilog Level: 1 Duration: 3 daysLearnwhenandhowtoapplysignalintegritytechniquestohigh-speedinterfacesbetweenXilinxFPGAsandothercomponents.Thiscomprehensivecoursecombinesdesigntechniquesandmethodologywithrelevantbackgroundconceptsofhigh-speedbusandclockdesign,includingtransmissionlinetermination,loading,andjitter.YouwillworkwithIBISmodelsandcompletesimulationsusingMentorGraphicsHyperLynx.OthertopicsincludemanagingPCBeffectsandon-chiptermination.Thiscoursebalanceslecturemoduleswithinstructordemonstrationsandpracticalhands-onlabs.

Designing with System Verilog Level: 1 Duration: 2 daysThiscomprehensivecourseisathoroughintroductiontoSystemVerilogconstructsfordesign.ThisclassaddresseswritingRTLcodeusingthenewconstructsavailableinSystemVerilog.Newdatatypes,structs,unions,arrays,proceduralblocks,re-usabletasksandfunctions,andpackages,areallcovered.Theinformationgainedcanbeappliedtoanydigitaldesign.Thiscoursecombinesinsightfullectureswithpracticallabexercisestoreinforcekeyconcepts.

Verification with System Verilog Level: 1 Duration: 2 daysThiscomprehensivecourseisathoroughintroductiontoSystemVerilogconstructsfordesign.ThisclassaddresseswritingRTLcodeusingthenewconstructsavailableinSystemVerilog.Newdatatypes,structs,unions,arrays,proceduralblocks,re-usabletasksandfunctions,andpackages,areallcovered.Theinformationgainedcanbeappliedtoanydigitaldesign.Thiscoursecombinesinsightfullectureswithpracticallabexercisestoreinforcekeyconcepts.

VHDL

Designing with VHDL Level: 1 Duration: 3 daysThiscomprehensivecourseisathoroughintroductiontotheVHDLlanguage.Theemphasisisonwritingsolidsynthesizablecodeandenoughsimulationcodetowriteaviabletestbench.Structural,RegisterTransferLevel(RTL),andbehavioralcodingstylesarecovered.ThisclassaddressestargetingXilinxdevicesspecificallyandFPGAdevicesingeneral.Theinformationgainedcanbeappliedtoanydigitaldesignbyusingatop-downsynthesisdesignapproach.Thiscoursecombinesinsightfullectureswithpracticallabexercisestoreinforcekeyconcepts.YouwillalsolearnbestcodingpracticesthatwillincreaseyouroverallVHDLproficiency.

Advanced VHDL Level: 4 Duration: 2 days

IncreaseyourVHDLproficiencybylearningadvancedtechniquesthatwillhelpyouwritemorerobustandreusablecode.ThiscomprehensivecourseistargetedtowarddesignerswhoalreadyhavesomeexperiencewithVHDL.Thecoursehighlightsmodeling,testbenches,RTL/synthesizabledesign,andtechniquesaimedatcreatingparameterizableandreusabledesigns.Themajorityofclasstimeisspentinchallenginghands-onlabsascomparedtolecturemodules.

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XILINX WORLDWIDE TRAINING

XilinxtrainingcoursesareofferedbyAuthorizedTrainingProviders(ATPs)inmostregionsoftheworld,providingyouexperttrainingopportunities.CustomercoursesofferedbyourATPsusehigh-qualitytrainingmaterialsdevelopedbyXilinx,andleveragethespecializedknowledgeandextensivenetworkofourATPs.Pricingandavailabilityofclassesvariesbyregion.

ADDITIONAL TRAINING RESOURCES

Curriculum Paths—Curriculumpathsillustratetherecommendedcoursesequencetofollowbasedonyourdesignspecialization.BecauseXilinxcoursesbuildoneachother,youmustmeettheprerequisitestogainthefullbenefitofeachcourse.Prerequisitesareoutlinedinthecoursedescriptions.Test Your knowledgeofthematerialcoveredineachcoursebyselectingtheappropriatelinknexttoyourcourseofinterest.www.xilinx.com/training/courses.htmRecorded e-Learning—Recordede-Learningsarecurrentlyavailableatnocharge,overtheInternetanytime,dayornight,worldwidetoallowyoutogetuptospeedquickly.Newtopicseachmonth,suchas:ClockingTechniques,TimingClosure,DDRMemoryInterface,FPGAvs.ASIC,etc.www.xilinx.com/training/free-video-courses.htm

AUTHORIZED TRAINING PARTNER CONTACT COUNTRY/REGION(S) SUPPORTEDXilinx Training Worldwide www.xilinx.com/training Worldwide

AMERICAS registrar@xilinx.com.

Anacom Eletrônica www.anacom.com.br Brazil

Bottom Line Technologies www.bltinc.com Delaware, District of Columbia, Maryland, New Jersey, New York, Eastern Pennsylvania, Virginia

Doulos www.doulos.com/XilinxNC Northern California

Faster Technology www.fastertechnology.com Arkansas, Colorado, Louisiana, Montana, Oklahoma, Southern Idaho, Texas, Utah, Wyoming

Hardent www.hardent.comAlabama, Connecticut, Eastern Canada, Florida, Georgia, Maine, Massachusetts, Mississippi, New Hampshire, North Carolina, Rhode Island, South Carolina, Tennessee, Vermont

North Pole Engineering www.npe-inc.com Illinois, Iowa, Kansas, Minnesota, Missouri, Nebraska, North Dakota, South Dakota, Wisconsin

Technically Speaking www.technically-speaking.com Arizona, British Columbia, Southern California, Northern Idaho, New Mexico, Nevada, Oregon, Washington

VAI Logic www.vaitechnology.com Indiana, Kentucky, Michigan, Ohio, WesternPennsylvania, West Virginia

EUROPE, MIDDLE EAST, & AFRICA (EMEA) eurotraining@xilinx.com

Core|Vision www.core-vision.nl The Netherlands, Belgium, LuxemburgDoulos www.doulos.com/xilinx United Kingdom, IrelandInline Group www.plis.ru Moscow RegionLogtel Computer Communications www.logtel.com Israel, TurkeyMagnetic Digital Systems www.magneticgroup.ru Urals RegionMindway www.mindway-design.com ItalyMulti Video Designs (MVD) www.mvd-fpga.com France, Spain, Portugal, Switzerland

Prevas www.prevas.com/xilinx Sweden, Norway, Denmark, Finland, Lithuania, Latvia, Estonia

Pulsar www.pulsar.co.ua Ukraine

Programmable Logic Competence Center (PLC2) www.plc2.deGermany, Switzerland, Poland, Hungary, Czech Republic, Slovakia, Slovenia, Greece, Cyprus, Turkey, Russia

SO-Logic Consulting www.so-logic.co.at Austria, Brazil, Czech Republic, Hungary, Slovakia, Slovenia

ASIA PACIFIC education_ap@xilinx.com

Activemedia Innovation www.activemedia.com.sg Malaysia, Singapore, ThailandBlack Box Consulting www.blackboxconsulting.com.au Australia, New ZealandE-elements www.e-elements.com China, Hong Kong, TaiwanHKPC www.hkpc.org Hong KongLibertron www.libertron.com KoreaOE-Galaxy www.oegalaxy.com.vn VietnamSandeepani Programmable Solutions www.sandeepani-vlsi.com IndiaSymmid www.symmid.com MalaysiaUltrawise ultrawise.com.cn ChinaWeDu Solution www.wedusolution.com Korea

JAPAN education_kk@xilinx.com

Avnet Japan www.jp.avnet.com TokyoPaltek www.paltek.co.jp YokohamaShinko Shoji xilinx.shinko-sj.co.jp TokyoTokyo Electron Device ppg.teldevice.co.jp Yokohama

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Notes

©2013XilinxInc.Allrightsreserved.TheXilinxnameandlogoareregisteredtrademarks,andTheProgrammableLogicCompanyisaservicemarkofXilinxInc.

PrintedinU.S.A. PN0402900-01

January2013

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