Electrical-Based ESD Characterization of Ultrathin-Body SOI MOSFETs

130 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 10, NO. 1, MARCH 2010

Electrical-Based ESD Characterization ofUltrathin-Body SOI MOSFETs

Alessio Griffoni, Student Member, IEEE, Steven Thijs, Member, IEEE, Christian Russ,David Trémouilles, Member, IEEE, Dimitri Linten, Member, IEEE, Mirko Scholz, Member, IEEE,

Eddy Simoen, Cor Claeys, Fellow, IEEE, Gaudenzio Meneghesso, Senior Member, IEEE, andGuido Groeseneken, Fellow, IEEE

Abstract—The electrostatic-discharge sensitivity of fully de-pleted SOI MOSFETs with ultrathin silicon body and ultrathingate oxide is studied. An original and detailed electrical analysis iscarried out in order to investigate the degradation of the electricaldc parameters and classify the observed failure modes and mech-anisms. The impact of device geometry and strain engineering isalso analyzed.

Index Terms—CMOS, electrostatic discharge (ESD), reliability,silicon-on-insulator (SOI), strain, transmission-line pulse (TLP),ultrathin body (UTB).

I. INTRODUCTION

CMOS TECHNOLOGY is now entering a phase where

simple shrinking is no longer sufficient to guarantee the

performance gains required from each new generation of de-

vices. Alternative materials and structures are required. On the

one hand, silicon-on-insulator (SOI) technology is now becom-

ing mainstream, owing to its superior control of short-channel

effects (SCEs) and promise for scalability [1]. According to the

2008 International Technology Roadmap for Semiconductors

[2], fully depleted (FD) SOI MOSFETs with ultrathin body

(UTB) [3], together with FinFET devices [4], are the main

candidates to continue with CMOS scaling below the 22-nm

technological node. On the other hand, mobility-enhancing

techniques are increasingly used to improve transistor perfor-

mance. Uniaxial and/or biaxial strain in the channel through

Manuscript received August 22, 2009; revised October 8, 2009. First pub-lished November 20, 2009; current version published March 5, 2010.

A. Griffoni is with the Interuniversity Microelectronics Center, 3001 Leuven,Belgium, and also with the Department of Information Engineering, Universityof Padova, 35131 Padova, Italy (e-mail: [email protected]).

S. Thijs, C. Claeys, and G. Groeseneken are with the InteruniversityMicroelectronics Center, 3001 Leuven, Belgium, and also with the Depart-ment of Electrical Engineering, Katholieke Universiteit Leuven, 3001 Leuven,Belgium.

C. Russ is with Infineon Technologies AG, 81721 Munich, Germany.D. Trémouilles is with the Laboratoire d’Analyse et d’Architecture des

Systèmes (LAAS), CNRS, 31077 Toulouse, France, and also with LAAS,UPS–INSA–INP–ISAE, University of Toulouse, 31077 Toulouse, France.

D. Linten and E. Simoen are with the Interuniversity MicroelectronicsCenter, 3001 Leuven, Belgium.

M. Scholz is with the Interuniversity Microelectronics Center, 3001 Leuven,Belgium, and also with the Department of Fundamental Electricity and Instru-mentation, Faculty of Engineering, Vrije Universiteit Brussels, 1050 Brussels,Belgium.

G. Meneghesso is with the Department of Information Engineering, Univer-sity of Padova, 35131 Padova, Italy.

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TDMR.2009.2036156

the use of stressor layers and/or substrate engineering are an

example of how mobility improvement can be obtained [5].

Electrostatic discharge (ESD) is a major concern for SOI,

since, contrary to bulk technologies, self-heating affects the

small active silicon region. Indeed, both the lateral [shallow

trench isolations (STIs)] and vertical [buried oxide (BOX)]

electrical isolations largely prevent the heat dissipation [6],

[7]. The shrinking of the silicon film further reduces the ESD

robustness [8], [9], making the silicon-body thickness one of

the main restrictions for ESD protection structures in advanced

SOI CMOS integrated circuits.

In this paper, we will investigate the ESD sensitivity and

the degradation of the electrical dc characteristics of UTB FD

SOI MOSFETs with ultrathin gate oxide (GOX), with particular

attention to the device geometry and to the impact of strain

engineering. The focus will be on the devices that need to be

protected from ESD, rather than on the protection structures

themselves. This is a crucial information to design effective

protections at later steps.

II. EXPERIMENTS AND DEVICES

We studied n-channel FD SOI MOSFETs manufactured by

IMEC in a 65-nm CMOS process. The devices feature a 1.5-nm

thermal silicon oxynitride (SiON) as gate dielectric, a 15-nm

undoped top silicon layer (tSi), a 150-nm-thick BOX, a 25-nm

Si source/drain (S/D) elevation prior to highly doped drain

formation, and Ni silicidation. The operating voltage (VDD)is 1 V. Devices with 0.25-µm minimal gate width (W ) and

0.15-µm minimal gate length (L) were used. Polysilicon was

used as gate material, inducing a negative front-gate threshold

voltage (VTH,FG) for NMOSFETs. Final devices will feature

metal gates with proper work functions to adjust VTH,FG.

Three variants were processed (Fig. 1):

1) SOI: reference devices processed on SIMOX substrates.

2) strained contact etch stop layer (sCESL) (sCESL + SOI):obtained by depositing (in one step) an additional 100-nm

tensile nitride (intrinsic stress of 800 MPa) that generates

additional uniaxial strain along the channel.

3) strained SOI (sSOI): fabricated using wafer bonding and

a donor wafer with a Si-capped Si0.8Ge0.2 strain relaxed

buffer that generates additional biaxial strain along the

channel.

More technological information can be found in [10].

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GRIFFONI et al.: ELECTRICAL-BASED ESD CHARACTERIZATION OF ULTRATHIN-BODY SOI MOSFETs 131

Fig. 1. Schematic cross section of the devices under study (not to scale).

The devices were stressed in grounded-gate (GG) configu-

ration by means of a solid-state pulser (transmission-line-pulse

(TLP)-like) at wafer level with square pulsewidth of 100 ns and

rise time of 5 ns. To measure the failure voltage (V t2) and

the failure current (It2) [7], we applied a sequence of pulses

to the drain terminal with increasing peak voltage (starting at

VDS = 1 V and increasing by 100 mV every step, while keeping

the front-gate and source terminals grounded). After each pulse

a full set of device dc characteristics was measured:

a) the front-gate current versus the front-gate voltage

(IG–VGS) with VDS = VBS = 0 V;

b) the drain current versus the front-gate voltage (IDS–VGS)

for different back-gate voltages while keeping VDS =25 mV;

c) the drain current versus the drain voltage

(IDS,front-channel–VDS) for different VGS’s while

keeping VBS = 0 V;

d) the drain current versus the drain voltage

(IDS,back-channel–VDS) for different VBS’s while keeping

VGS = 0 V;

e) the drain leakage current (IDS,leakage) at different drain

voltages and VGS = 0 V.

To perform both ESD stresses and four-terminal dc mea-

surements on the device under test, an RF switch was used to

switch the gate terminal between the ground loop and a source

monitor unit of the parameter analyzer (HP4156C). During the

ESD stresses, the gate terminal was shorted to the grounded

source terminal by means of a ground loop similar to the one

usually used in the TLP stress systems for the source, which

ensures very low impedance to the ground. To measure the

device dc characteristics, the gate terminal was connected to

the parameter analyzer.

We tested more than 150 devices for this work.

III. ESD EFFECTS ON SOI MOSFETs

Destructive ESD events at the drain terminal give rise to

either or both of two distinct phenomena: GOX breakdown

and/or creation of an additional conductive path between source

and drain, which is called “filament.” Figs. 2 and 3 show these

two phenomena through electrical failure signatures.

GOX breakdown during ESD can occur either in the central

gate area (over the conducting channel) or in the overlap

Fig. 2. (a) IG–VG (VDS = VBS = 0 V). (b) Front- and (c) back- channelIDS–VDS (VBS = 0 V and VGS = 0 V, respectively) for a conventional FDSOI MOSFET (W/L = 10/0.25 µm). The GOX hard breakdown occurred,resulting in a large IG increase and an IDS increase that depends on both VGS

and VBS.

regions between gate and S/D extensions. In our samples, the

GOX breakdown occurs near the overlap region between the

gate and drain extension (Fig. 4). The GOX breakdown is

a statistical process and is triggered when a critical density

of traps is reached in the GOX [11]. The breakdown current

(at VGS = 1 V) measured in our devices ranges from a few

hundreds of nanoamperes to hundreds of microamperes. The

GOX breakdown can be of different type and magnitude. The

hard breakdown shows a nearly ohmic current–voltage relation





Fig. 3. (a) IG–VG. (b) Front- and (c) back-channel IDS–VDS (at the samebias conditions shown in Fig. 2) for a conventional FD SOI MOSFET (W/L =10/0.16 µm). Both the GOX soft breakdown and filamentation near theGOX/silicon interface occurred, resulting in back-channel IDS–VDS indepen-dence of VBS.

[Fig. 2(a)], while the soft breakdown displays a power-law

characteristic [Fig. 3(a)]. Such different behavior is due to the

different conduction mechanism for hard and soft breakdowns

[12]. This is related to the types of oxide traps, the free energy

levels, and the different number of traps in the percolation path,

or a different location of the trap centroid between anode and

cathode [13].

Fig. 3(b) and (c) shows the S/D filament formation, possibly

due to silicon and/or silicide being melted by Joule heating [7].

The measured filament resistance (Rfilament), extracted from

Fig. 4. Gate, source, and drain currents versus gate voltage (VDS = VBS =0 V) before ESD stress and after failure for a conventional FD SOI MOSFET(W/L = 10/0.25 µm). After failure, a significant increase in the gate anddrain leakage currents (≈ 100 µA) is observed, indicating the occurrenceof GOX breakdown close to the overlap region between the gate and drainextensions.

the IDS,front-channel–VDS and IDS,back-channel–VDS curves, is

given by

Rfilament =

(

∂IDS

∂VDS

∣

∣

∣

∣

VGS,VDS

)−1

. (1)

Rfilament may be as low as a few hundreds of ohms.

With the aim to classify the occurrence of GOX breakdown

or S/D filamentation, we can discriminate between the two

mechanisms, owing to their different electrical signature as a

function of the applied bias. In fact, the following may be

observed.

1) The current due to GOX breakdown depends on the field

across the GOX.

2) The current due to a filament between source and drain

mainly depends on VDS and may be independent of either

or both the VGS and VBS. In particular, if the drain/source

current is independent of both VGS and VBS, the filament

may be located in the whole silicon body, while, if the

drain/source current is independent only of VBS (VGS),the filament may be located near the GOX/silicon (sili-

con/BOX) interface (Fig. 3).

A low-value resistor can be used to model the filament,

whereas a voltage-dependent current source is more appropriate

to account for the GOX breakdown conduction. With this back-

ground, we can now conclude that the ESD events induce either

GOX breakdown (Fig. 2) or a combination of GOX breakdown

and filament formation (Fig. 3).

IV. FAILURE CRITERION

The device failure is usually taken as the amplitude of the

pulse at which a large change occurs (i.e., 10×) in the leakage

current of the terminal subjected to the ESD. A full set of dc

measurements, after each ESD step, permits to detect also any

parameter degradation before the destructive ESD event and

(based on the consideration made in Section III) the failure

mechanism. For these reasons, it is useful to know how the





GOX is damaged, since stress-induced leakage current and

progressive, soft, and hard GOX breakdowns can occur in

ultrathin GOX (< 2.5 nm) under ESD stresses [14]–[16].

To develop a failure criterion independent from the device

size, we consider the following dc parameters:

1) IG,ON: the gate current at VGS = 1 V and VDS = VBS =0 V;

2) IG,OFF: the gate current at VGS = −0.75 V and VDS =VBS = 0 V;

3) I∗DS,OFF(= IDS,OFF/L): drain current normalized to the

gate length at VGS = −0.75 V, VDS = 25 mV, and VBS =0 V. VGS was chosen as −0.75 instead of 0 V because

VTH,FG varies between −0.3 and −0.2 V, depending on

the device geometry and strain level. The drain current is

normalized to the gate length since the filament resistance

is (in first approximation) directly proportional to L and

does not depend on W .

Notice that, contrary to I∗DS,OFF, the choice of the bias

condition for IG,ON and IG,OFF is not related to the fact that

our samples have VTH,FG < 0 V, but only to monitor the gate

current in the inversion (VGS = 1 V) and accumulation (VGS =−0.75 V, similar results are obtained also for VGS = −1 V)

regions.

The information about the GOX degradation and breakdown

is given by the IG,ON variation (∆IG,ON) before and after

stress. After the first ESD pulses, ∆IG,ON is below 300–

400 pA (Figs. 5 and 6); therefore, the first threshold for the

detection of events in ∆IG,ON can be set about ten times

this value (3–4 nA). Concerning more severe GOX events,

the soft breakdown experiences a ∆IG,ON increase between

10 nA and 1 µA, while the hard breakdown exhibits a larger

increase in ∆IG,ON (> 1 µA). Furthermore, when ∆IG,ON >100 nA, there is also an increase in the absolute value of the

IG,OFF variation (|∆IG,OFF|), which causes a large increase in

I∗DS,OFF variation (∆I∗DS,OFF > 10 µA/µm) (Fig. 5). In other

words, when a hard or severe soft GOX breakdown occurs, it is

detected also from ∆I∗DS,OFF, since a nonmarginal amount of

current is injected from the gate to the drain, biasing negatively

the gate electrode. However, some MOSFETs affected by pro-

gressive and/or nonsevere soft breakdown (∆IG,ON < 100 nA)show a large increase in ∆I∗DS,OFF, although ∆IG,OFF is not

so large to induce this strong increase in ∆I∗DS,OFF (Fig. 6).

This “odd” behavior is due to the filament formation between

source and drain, as confirmed by the IDS–VDS analyses at the

front- and back-channel transistors (Fig. 3).

Based on these considerations, the destructive device fail-

ure was taken as the amplitude of the pulse at which either

∆IG,ON > 10 nA or ∆I∗DS,OFF > 10 µA/µm, whichever took

place first. When the ∆I∗DS,OFF condition is met, the other

parameters (∆IG,ON < 1 µA and |∆IG,OFF| < 100 nA) are

checked to detect a possible filament formation. Other failure

criteria can be used, for instance, taking into account also any

change in the VTH,FG shift and in the transconductance (gm)drop, whichever took place first. However, such failure criterion

can be too severe, particularly if only a modest degradation

occurs and does not give any indication about the occurred

failure mechanism.

Fig. 5. ∆IG,ON (VGS = 1 V and VDS = VBS = 0 V), |∆IG,OFF|(VGS = −0.75 V and VDS = VBS = 0 V), and ∆I∗

DS,OFF(VGS =

−0.75 V, VDS = 25 mV, and VBS = 0 V) as a function of the measuredESD voltage for a conventional FD SOI MOSFET (W/L = 10/0.25 µm).The sample experiences a progressive GOX breakdown, followed by the hardrupture.

Fig. 6. ∆IG,ON, |∆IG,OFF|, and ∆I∗DS,OFF

(at the same bias conditions

shown in Fig. 4) as a function of the measured ESD voltage for a conventionalFD SOI MOSFET (W/L = 10/0.16 µm). The sample experiences a smallincrease in the gate current (indicating a soft GOX breakdown) and a largerincrease of I∗

DS,OFF, indicating the filament formation occurrence.

V. GEOMETRY DEPENDENCE

In this section, the impact of gate length and width on the

failure current and voltage of conventional SOI MOSFETs is

investigated.

A. Gate-Length Dependence

Fig. 7 shows the TLP I−V characteristics for SOI

MOSFETs with W = 10 µm and different L’s. Even though the

devices are stressed in GG configuration, they start to conduct

as soon as a positive voltage is applied because of VTH,FG <0 V. Two regions can be separated. In the first one (voltage <2.5/3 V, depending on L), the current increases linearly with

increasing voltage. In the second region (voltage < 2.5/3 V,

depending on L), the current saturates due to velocity saturation

and self-heating. Fig. 6 also shows a qualitative scaling with L:

It2 decreases while V t2 increases with increasing L. However,

this scaling is limited by the sublinear scaling of current with Land the saturation of the current at higher voltages.





Fig. 7. (a) TLP I−V curves and (b) leakage current evolutions for n-channelFD SOI MOSFETs with W/L = 10/0.16 µm, 10/0.2 µm, and 10/0.25 µm,respectively. A sequence of pulses was applied to the drain terminal withincreasing peak voltage, while keeping the front-gate and source terminalsgrounded.

Fig. 8. Failure current (It2) normalized to the gate width (W ) as a functionof the gate length for FD SOI MOSFETs with W = 10 µm stressed in GGconfiguration.

Fig. 8 shows It2 normalized to W (It2/W ) as a function

of L for different strain levels, while Fig. 9 shows V t2 as a

function of L for SOI MOSFETs with different W ’s. When

L is increased, V t2 increases monotonically (regardless of

W ), while It2 normalized to gate width (It2/W ) decreases

monotonically, regardless of the strain level.

Fig. 9. Failure voltage (V t2) as a function of the gate length (L) forconventional FD SOI MOSFETs with different gate widths (W ) stressed inGG configuration.

Even though the devices are stressed in GG configuration,

a MOS conduction exists on the top of the parasitic bipolar

conduction because of VTH,FG < 0 V. This improves the cur-

rent uniformity at high current levels [7], and the increase in Lmainly induces only additional self-heating, reducing It2 and

increasing V t2. A secondary effect, enhanced by VTH,FG <0 V, is that, when a large voltage is applied to the drain, while

keeping the other terminals grounded, a significant amount of

hot carriers flows through the channel generating hot-carrier-

induced degradation. Clearly, devices with short L’s (at con-

stant drain bias) present larger electric fields and, hence, are

more sensitive. Furthermore, during the ESD discharge, the

device region that is more prone to degradation is the one close

to the drain, as extensively investigated in [17] and [18].

B. Gate-Width Dependence

Fig. 9 shows that V t2 decreases with decreasing W for

short L (< 0.25 µm), while V t2 is almost independent on Wfor long L (≥ 0.25 µm), where the channel-hot-carrier (CHC)

effects are negligible. Such trend can be explained by means

of the similarity between drain ESD events and CHC stresses,

which shows an enhanced degradation on narrow width [19].

The reason can be found in a different electric-field distribution

between wide and narrow devices that makes wider transistors

more robust to the CHC effects.

The high-current characteristics of narrow MOSFETs cannot

be measured by the used TLP test setup. This is because

the ESD current, which is on the order of some hundreds

of microamperes in such devices, is not high enough to be

measured by a TLP system. Therefore, we can make only some

conjecture about the It2 dependence on W .

An improvement in It2 due to the MOS conduction (induced

by VTH,FG < 0 V) on the top of the parasitic bipolar conduction

is expected for wider MOSFETs. Such amelioration is usually

observed for low values of gate bias (< 1 V) [20], similarly to

our case. Single-finger devices, as in our case, can be affected

by isothermal current instability which is initiated by impact

ionization under high field conditions [21]. Locally, a high Joule

power level is generated, which results in a filament formation

and, finally, local burnout. This means that, even within a





Fig. 10. TLP I−V curves and (b) leakage-current evolutions for n-channelFD SOI MOSFETs with W/L = 10/0.16 µm and different strain levels. Asequence of pulses was applied to the drain terminal with increasing peakvoltage, while keeping the front-gate and source terminals grounded.

single wide finger, there can exist a degree of nonuniformity.

Therefore, an improvement in It2 will be apparent in wide

devices where the ESD current is strongly nonuniform. On the

other hand, It2 will be degraded with gate bias for narrow

MOSFETs, where ESD current is known to conduct nearly

uniformly [20].

VI. IMPACT OF STRAIN

The TLP I−V curves for UTB FD SOI MOSFETs with

aspect ratio of W/L = 10/0.16 µm and different strain levels

are shown in Fig. 10. Two regions can be observed. In the first

part of the stress, where the drain current increases linearly

with increasing voltage, sSOI devices exhibit the largest amount

of current and the lowest on-resistance (Ron) compared with

the other samples. These are because sSOI transistors have the

highest mobility and lowest VTH,FG. The lowest amount of

current and largest Ron is observed for SOI MOSFETs. This is

due to the lower mobility (but the same VTH,FG) of SOI devices

with respect to sCESL + SOI ones. In the second part of the

stress (where the voltage is larger than 2.5/3 V), the current

shows a different behavior, depending on the strain level. For

SOI MOSFETs, the current saturates with increasing voltage.

On the contrary, for sSOI and sCESL + SOI devices, the cur-

rent saturation does not occur, and the failure happens before

the turn-on of the parasitic BJT, suggested by the increase in the

TABLE IPERCENTAGE OF SAMPLES AFFECTED (a) ONLY BY GOX BREAKDOWN

AND (b) BY BOTH GOX BREAKDOWN AND FILAMENT FOR DIFFERENT

GATE LENGTHS (L), GATE WIDTHS (W ), AND STRAIN LEVELS

slope of the I−V curves. The turn-on voltage of the parasitic

BJT is lower in strained devices because of a larger common-

emitter current gain (β) due to a higher mobility.

It2/W , as a function of L for devices with different strain

levels, is shown in Fig. 8. An increase up to 20% and 44% is

observed for sCESL + SOI and sSOI, respectively, with respect

to SOI. Similar to SOI FinFETs [22], the It2 improvement is

larger for short L’s, where the effectiveness of the strain is

larger. This behavior can be attributed to larger MOS current,

mobility modulation (of both majority and minority carriers),

and thermal conductivity modulation induced by the strain, as

recently shown in [23].

VII. FAILURE MECHANISMS

In order to carefully analyze the failure mechanisms, we have

reported in Table I the percentage of samples affected 1) only by

GOX breakdown and 2) by both (progressive and/or nonsevere

soft) GOX breakdown and filamentation for different L, W , and

strain levels.

The GOX breakdown alone (without filamentation) is the

only failure mechanism for MOSFETs with long L’s, regardless

of W and strain level, while GOX breakdown together with

filamentation can occur for short L’s. This is because the

base voltage of the parasitic n-p-n increases with increasing

L, leading the GOX to be subjected to more severe stress and

lower current levels for long L’s compared to short ones [24].

In addition, for short gate lengths, where the power to failure

(Pf = V t2 · It2) is 3.5× larger than for long L’s (5 versus

1.3 mW/µm), the filament between source and drain junctions

is supposed to form more easily [25], while with increasing

L’s, the volume of the gate increases, which improves the heat

dissipation.

It is interesting to observe that the position (in the silicon

body) of the filamentation depends on W . For wide devices, the

filament is located close to the GOX/silicon interface (Fig. 3).

On the other hand, for narrow MOSFETs, the whole silicon

body is affected by such failure mechanism (Fig. 11), since

the drain/source current is independent of both VGS and VBS.

This W dependence is due to the reduction in heat removal





Fig. 11. (a) IG–VG. (b) Front- and (c) back-channel IDS–VDS VDS (at thesame bias conditions shown in Fig. 2) for a conventional FD SOI MOSFET(W/L = 0.25/0.17 µm). Both the GOX soft breakdown and filamentationin the whole silicon body (resulting in front- and back-channel IDS–VDS

independence on VGS and VBS, respectively) occurred.

attributed to the STIs for narrow transistors [6] and to a re-

duction of the available silicon volume (2.55 · 10−14 cm3 for

W/L = 10/0.17 µm, while only 6.38 · 10−16 cm3 for W/L =0.25/0.17 µm).

The percentage of short-channel samples affected by both

GOX breakdown and filamentation depends on W and strain

levels. When W is decreased, the percentage of sSOI samples

affected also by filamentation increases from 16% to 53%. Such

percentage is almost independent of W for SOI MOSFETs.

The different trends are due to the different amounts of current

density (IDS/W ) flowing in the channel. For sSOI transistors,

TABLE IITHERMAL PARAMETERS OF THE MATERIALS USED FOR THE

MANUFACTURING OF SCESL + SOI AND SOI FD MOSFETs

the drain current density increases up to 20% with decreasing

W (indicating that strain is more efficient for narrow devices),

while it increases up to only 6% in SOI transistors [10].

Finally, regardless of W and L, sCESL + SOI devices

only present hard GOX breakdown and no filamentation (see

Table I). Similarly to the results found by Kubota et al. for an

n-p-n lateral BJT with field oxide [26], the failure of sCESL +SOI samples can be attributed to dislocations at the drain side,

triggered by the interplay between the local thermal ESD stress

and the residual mechanical stress induced by the sCESL.

Moreover, the capping layer induces an additional lateral me-

chanical stress close to the overlap region between the gate

and drain/source extension [27]. Therefore, dislocations can

induce the GOX breakdown before the S/D filament formation.

The thermal properties of the SiN stressor were found not

to improve the cooling of the fins (Table II), similar to SOI

FinFETs [22]. The thermal conductivity of the 100-nm SiN

strain layer is about 4× lower than the one of the 50-nm SiC

layer, which is used instead for the SOI devices between the

active device area and the low- k layer. On the contrary, the

specific heat capacitance is about the same in both cases.

VIII. DEGRADATION OF THE ELECTRICAL

DC PARAMETERS

We continue our analysis taking into account the degradation

of the electrical dc characteristics, namely, the transconduc-

tance (gm) and the front-gate threshold voltage (VTH,FG).For L ≥ 0.5 µm, the devices exhibit only a negligible gm

drop (< 1%) and (VTH,FG) shift (< 2 mV), regardless of Wand strain level (Fig. 12). On the contrary, for L ≤ 0.25 µm,

the devices show a modest degradation of the electrical dc

parameters (Figs. 13, 14, 16, and 17), depending on the strain

level but not on W .

Fig. 13 shows the (VTH,FG) shift and the relative gm drop

as a function of the ESD voltage for a SOI MOSFET with

W/L = 10/0.25 µm. Two phases can be distinguished. For low

ESD stress levels (voltage < 3.2 V and current < 0.5 mA/µm,

see Fig. 7), a negligible degradation of (VTH,FG) and gm is ob-

served. On the other hand, for high ESD stress levels (voltage >3.2 V and current ≈ 0.5 mA/µm, see Fig. 7), the VTH,FG shift

increases up to 12 mV while gm drops by 26% (Figs. 13 and

14). Fig. 13 also shows that the VTH,FG shift and the gm drop

are correlated. Such degradations cannot be attributed to charge

buildup and interface-state generation in the BOX because the

trends cannot be emulated by biasing the back gate at different





Fig. 12. (a) IDS–VGS and (b) gm−VGS (VDS = 25 mV and VBS = 0 V)for a conventional FD SOI MOSFET (W/L = 10/0.5 µm). No degradation ofthe electrical dc parameters is observed at the ESD zap just before failure.

Fig. 13. VTH,FG shift and relative gm drop (VDS = 25 mV and VBS = 0 V)as a function of the TLP pulse voltage for a conventional SOI MOSFET withW/L = 10/0.25 µm.

voltages. Indeed, under such circumstance, both VTH,FG and

gm increase with decreasing VBS (Fig. 15). Therefore, the

degradation of VTH,FG and gm is attributed to the increase in

interface-state density and traps in the GOX located near the

overlap region between the gate and drain extensions. This is

because a significant amount of hot carriers flows through the

channel, generating hot-carrier-induced degradation.

For short-channel sCESL + SOI MOSFETs (Fig. 16), the

VTH,FG shifts only 4 mV, and gm drops down only by 7%. The

Fig. 14. (a) IDS–VGS and (b) gm−VGS (VDS = 25 mV and VBS = 0 V) fora conventional SOI MOSFET (W/L = 10/0.25 µm). The front-gate thresholdvoltage increases while the transconductance decreases with increasing ESDstress level.

Fig. 15. IDS–VGS and gm−VGS (VDS = 25 mV and VBS = −7, 0, and7 V) for a conventional FD SOI MOSFET (W/L = 10/0.17 µm) for differentback-gate biases. Both VTH,FG and gm increase with increasing back-gatevoltage.

lower degradation of sCESL + SOI samples compared with

SOI ones is attributed to the better GOX quality, as shown

by time-dependent dielectric breakdown measurements on the

same devices [28]. As reported for bulk MOSFETs [29], in

spite of the higher drain current for sCESL + SOI devices, the

ISUB/ID current ratio (where ISUB is the substrate current),





Fig. 16. (a) IDS–VGS and (b) gm−VGS (VDS = 25 mV and VBS = 0 V) fora sCESL + SOI MOSFET (W/L = 10/0.25 µm). The front-gate thresholdvoltage increases while the transconductance decreases with increasing ESDstress level.

which is a measure of the efficiency of the CHC generation

process, is the same for the two types of devices.

For short-channel sSOI MOSFETs (Fig. 17), gm drops down

to 19% while VTH,FG shifts up by 6 mV. The lower degradation

of sSOI devices with respect to SOI ones is attributed to the

lower ISUB/ID ratio for sSOI, as reported for bulk MOSFETs

[30]. Indeed, the IDS–VGS and gm−VGS characteristics con-

firm that the interface-state-generation rate is reduced in sSOI

samples compared with SOI ones.

IX. CONCLUSION

An extensive ESD characterization of UTB FD SOI MOS-

FETs with ultrathin GOX and different strain-inducing tech-

nologies (conventional SOI, sCESL + SOI, and sSOI) has been

presented. A detailed electrical investigation has been carried

out in order to carefully classify the observed failure mech-

anisms. A new failure criterion that allows us to univocally

identify the device failure regardless of the occurred failure

mechanisms (soft/hard GOX breakdown and/or S/D filamenta-

tion) has been proposed.

For long-channel MOSFETs, the failure is attributed only to

the GOX breakdown. In contrast, short-channel transistors can

be affected by both filamentation and GOX breakdown. The

Fig. 17. (a) IDS–VGS and (b) gm−VGS (VDS = 25 mV and VBS = 0 V)for an sSOI MOSFET (W/L = 10/0.25 µm). The front-gate threshold volt-age does not significantly change while the transconductance decreases withincreasing ESD stress level.

absence of filamentation is observed for sCESL + SOI devices,

regardless of the device geometry.

Strain improves the ESD robustness up to 20% and 44% for

sCESL + SOI and sSOI, respectively. A modest degradation

of the electrical dc parameters is observed only for short gate

lengths, and it is larger for conventional SOI devices compared

with the other types of transistors.

Final metal-gate devices may present some difference com-

pared with the results presented in this paper. For example,

final MOSFETs stressed in GG configuration are expected to

not have the additional MOS conduction on the top of parasitic

bipolar conduction. This can induce a different amount of fail-

ure current and degradation of the electrical dc parameters. For

a qualitative comparison between the results obtained in this

paper and the TLP characteristics of SOI MOSFETs with metal

gate, we can refer to the results obtained for SOI FinFETs with

a single “fin” of 40 µm, which are, in essence, planar devices,

and with a silicon thickness of 65 nm [31]. For both NMOS

and PMOS devices, no snapback is seen in the TLP I−V curves

since the parasitic bipolars have their bases floating. In addition,

small gate lengths cannot control SCEs for wide-fin samples,

leading to a significant amount of current flow, even before the

snapback. Failure due to thermal runway (i.e., filamentation)

occurs in NMOS devices regardless of gate length and PMOS

transistors with short gate length. On the contrary, the GOX





breakdown is observed for PMOS devices with medium and

long gate lengths, because of a large voltage drop. However, it

should be remarked that, contrary to our samples, such devices

have a high- k dielectric (Hf-based) as GOX. This improves the

GOX breakdown voltage, as recently reported in [32].

Our data suggest that the ESD effects on I/O MOSFETs

must be constantly monitored, particularly when new process

modules, such as the reduction in the silicon-body thickness and

the employment of channel strain techniques, are introduced

into conventional CMOS technology.

Nonstrained UTB FD SOI MOSFETs can achieve up to

1-mA/µm current capability (namely, It2), making them ro-

bust enough when local clamping devices are used. Although

our samples have negative front-gate threshold voltages, final

metal-gate devices could be biased during ESD events to restore

maximum It2.

Nonstrained UTB FD SOI MOSFETs can achieve up to

1-mA/µm current capability (namely, It2 per channel width),

making them robust enough when local clamping devices are

used. Indeed, such value of current capability is comparable

with the ones obtained for partially depleted SOI with larger sil-

icon thickness, whose It2 per transistor width ranges between

3.5 and 1.1 mA/µm [33]. Despite the fact that our samples have

negative front-gate threshold voltages, final metal-gate devices

could be biased during ESD events to restore maximum It2.

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Alessio Griffoni (S’03) received the B.S. degreein information engineering and the M.S. degree(summa cum laude) in electronic engineering fromthe University of Padova, Padova, Italy, in 2004and 2006, respectively, where he has been workingtoward the Ph.D. degree in the Department of Infor-mation Engineering since 2007.

Since 2008, he has been with the InteruniversityMicroelectronics Center, Leuven, Belgium, workingon the ESD design and characterization of multigateFinFET devices, owing to the APROTHIN project

of the European Community. His main research topics concern the ionizingradiation effects and ESD in advanced CMOS devices.

Steven Thijs (M’08) received the M.Sc. and Ph.D.degrees in electrotechnical engineering from theKatholieke Universiteit Leuven, Leuven, Belgium, in2001 and 2009, respectively. Since 2006, he has beenworking toward the Ph.D. degree at the Interuniver-sity Microelectronics Center (IMEC), Leuven, in thefield of electrostatic-discharge (ESD) protection forFinFET devices and RF CMOS circuits.

In 2001, he was with the Silicon Processing andDevice Reliability Group, IMEC, where he was in-volved in ESD protection design, layout, simulation,

and characterization of CMOS and BiCMOS technologies and in RF circuitdesign with ESD protection. In 2005, he joined Sarnoff Europe, continuing hiswork on innovative ESD protection design. He is currently with the Departmentof Electrical Engineering, Katholieke Universiteit Leuven.

Mr. Thijs is a member of the Technical Program Committee of the Elec-trical Overstress/ESD (EOS/ESD) Symposia 2007–2010 and the InternationalReliability Physics Symposium 2009. He is a Peer Reviewer for various IEEEjournals. He was the recipient of the Best Paper and Best Student Paper Awardsfrom the EOS/ESD Symposia in 2004 and 2008, respectively.

Christian Russ received the M.S. and Ph.D. degreesin electrical engineering from the Technical Univer-sity of Munich, Munich, Germany, in 1991 and 1999,respectively.

From 1994 to 1998, he was with the R&D Labo-ratory, Interuniversity Microelectronics Center, Leu-ven, Belgium, on a fellowship from the EuropeanCommunity for research on electrostatic-discharge(ESD) and reliability issues in CMOS technologies.From 1998 to 2003, he was with Sarnoff Corpo-ration, Princeton, NJ, working on the creation of

innovative on-chip ESD protection and where he was responsible for ESDtechnology transfer and licensing programs. Since 2003, he has been withInfineon Technologies AG, Munich, where he is currently a Principal Engineerfor the development of ESD protection concepts in deep submicrometer CMOSand FinFET processes. He has published over 60 (as of 2009 without theElectrical Overstress/ESD (EOS/ESD) Symposium) conference and journalpublications. He is the holder of over 18 patents in his field.

Dr. Russ was the recipient or corecipient of several Best Paper Awards at theEOS/ESD Symposia and at the ESREF Conference.

David Trémouilles (M’08) received the M.S. de-gree in electrical engineering and the Ph.D. degreein microelectronic circuit and microsystem designfrom the Institut National des Sciences Appliquées,Toulouse, France, in 2000 and 2004, respectively.During his Ph.D. degree, his research activity fo-cused on the design optimization, simulation, andmodeling of electrostatic-discharge (ESD) protectionfor BiCMOS technologies. This work was carriedout at the Laboratoire d’Analyse et d’Architecturedes Systèmes, CNRS (LAAS/CNRS), Toulouse, in

collaboration with ON Semiconductor, Toulouse, France.In October 2004, he was with the Reliability Research Group, Interuniversity

Microelectronics Center, Leuven, Belgium, where he was granted a MarieCurie Intra-European fellowship from the European Community. His researchinterests were on the impact of new technology options and device architectureon ESD robustness, and innovative ESD protection for RF circuits. Since April2007, he has been with LAAS/CNRS to study alternative materials and strate-gies to protect integrated circuits and systems against ESD and electromagneticinterference in the framework of a Marie Curie European Reintegration Grant.In 2008, he succeeded in the CNRS Researcher Entrance Competition. He hasbeen a full-time CNRS Researcher since October 2008. He is also with LAAS,UPS–INSA–INP–ISAE, University of Toulouse, Toulouse.

Dr. Trémouilles served as a member of the Technical Program Committeeof the Electrical Overstress/ESD Symposia 2007 and 2008 and as Chairmanof the “ESD Device Testing” and “System-Level ESD” sessions at the 2009symposium.

Dimitri Linten (S’01–M’06) received the M.Sc.and Ph.D. degrees in electrical engineering fromthe Vrije Universiteit Brussel (VUB), Brussels, Bel-gium, in 2001 and 2006, respectively.

In 2001, he was with the Wireless ResearchGroup, Interuniversity Microelectronics Center(IMEC), Leuven, Belgium. In 2006, he was withthe Department of Fundamental Electricity andInstrumentation (ELEC), Faculty of Engineering,VUB, and also with the Electrostatic Discharge(ESD) Reliability Group, IMEC, as a Postdoctoral

Research Fellow, supported by the Institute for the Promotion of Innovationthrough Science and Technology in Flanders (IWT–Vlaanderen). Since 2007,he has been the Scientific Coordinator of the ESD Research Group, IMEC. Hisresearch interests are on-wafer ESD testers, ESD-reliable RF circuit designand ESD reliability for sub-32-nm FinFET and planar devices, high-voltagesilicon technologies, and Python OOP. He authored or coauthored more than100 publications and patents in these fields.

Dr. Linten was the recipient of the Best Paper Award from the ElectricalOverstress/ESD Symposium 2004.

Mirko Scholz (M’01) received the M.Sc. degree(“Diplomingenieur (FH)”) in electrical engineering(with a minor in communication engineering) fromthe University of Applied Sciences, Zwickau, Ger-many, in 2005. Since January 2009, he has beenworking toward the Ph.D. degree at the Vrije Uni-versiteit Brussels, Brussels, Belgium, with the topic“Human Metal Model—System-level ESD stress oncomponent level.”

Since 2005, he has been with the ElectrostaticDischarge (ESD) Reliability Team, Interuniversity

Microelectronics Center, Leuven, Belgium. He authored or coauthored morethan 40 publications and patents in the field of ESD reliability and testing.His current research interests are ESD measurement methodologies, devicecharacterization and analysis, as well as system-level ESD.

Mr. Scholz is an active member of the Device Testing Working Groups of theESD Association Standards Committee in 2007 and a member of the TechnicalProgram Committee of the Electrical Overstress/ESD Symposium in 2009.





Eddy Simoen received the M.S. degree in physicsengineering and the Ph.D. degree in engineeringfrom the University of Gent, Gent, Belgium, in1980 and 1985, respectively. His doctoral thesis wasdevoted to the study of trap levels in high-puritygermanium by deep-level transient spectroscopy.

Since 1986, he has been with the InteruniversityMicroelectronics Center (IMEC), Leuven, Belgium,where he works in the field of low-temperatureelectronics. His current interests cover the field ofdevice physics and defect engineering in general,

with particular emphasis on the study of low-frequency noise, low-temperaturebehavior, and radiation defects in semiconductor components and materials.He is an IMEC Scientist currently involved in the study of defect and strainengineering in high-mobility and epitaxial substrates and defect studies ingermanium. In these fields, he has coauthored over 1000 journal and conferencepapers and, in addition, 11 book chapters and a monograph on Radiation Effects

in Advanced Semiconductor Devices and Materials (Springer, 2002), whereofthe Chinese translation has been published in March 2008. He was also a Coed-itor of the book on Germanium-based Technologies: From Materials to Devices

(Elsevier, 2007). A new book on the Fundamental and Technological Aspects

of Extended Defects in Germanium will be published by Springer in January2009. He acted as Coeditor of four international conference proceedings.

Dr. Simoen was a Lecturer at the International Noise School held at IMECin 1993, at the ENDEASD Workshop in Santorini, Greece (April 1999) andStockholm, Sweden (June 2000), and at the EUROSOI Workshop in Leuven(January 2007).

Cor Claeys (S’94–SM’95–F’09) received theelectrical–mechanical engineering degree and thePh.D. degree from the Katholieke UniversiteitLeuven (KU Leuven), Leuven, Belgium, in 1974and 1979, respectively.

From 1974 to 1984, he was a Research Assistantand a Staff Member with ESAT Laboratory, Elec-trical Engineering Department, KU Leuven, wherehe has been a Professor since 1990. In 1984, hejoined the Interuniversity Microelectronics Center,Leuven, Belgium, as the Head of the Silicon Process-

ing Group. Since 1990, he has been the Head of the Research Group onradiation effects, cryogenic electronics, and noise studies. Recently, he becamethe Director of Advanced Semiconductor Technologies who is responsiblefor strategic relations. His main interests are, in general, silicon technologyfor ULSI; device physics, including low-temperature operation, low-frequencynoise phenomena, and radiation effects; and defect engineering and materialcharacterization. He is an Associated Editor for the Journal of the Electro-

chemical Society. He had short stays as Visiting Professor at the QueensUniversity, Belfast, Ireland, U.K., and the University of Calabria, Calabria,Italy. He coedited a book on Low Temperature Electronics and Germanium-

Based Technologies: From Materials to Devices and wrote monographs onRadiation Effects in Advanced Semiconductor Materials and Devices and Fun-

damental and Technological Aspects of Extended Defects in Germanium. Healso authored and coauthored eight book chapters and more than 800 technicalpapers and conference contributions related to the aforementioned fields.

Prof. Claeys is a fellow of the Electrochemical Society. He is also a memberof the European Expert Group on Nanosciences. He was the Founder of theIEEE Electron Devices Benelux Chapter, the Chair of the IEEE BeneluxSection, an elected AdComMember of the Electron Devices Society (EDS)during 1999–2005, and the EDS Vice President for Chapters and Regionsduring 2000–2006. Since 2000, he has been an EDS Distinguished Lecturer.In 2006, he was elected as EDS President-Elect and became EDS President in2008. He was also the recipient of the IEEE Third Millennium Medal. Withinthe Electrochemical Society, he has been serving in different committees andwas the Chair of the Electronics Division from 2001 to 2003. In 1999, hewas elected as Academician and Professor of the International InformationAcademy. In 2004, he received the Electronics Division Award of the Electro-chemical Society. He has been involved in the organization of a large numberof international conferences and has edited more than 40 proceedings volumes.

Gaudenzio Meneghesso (S’95–M’97–SM’07) wasborn in Padova, Italy, in 1967. He received the Lau-rea degree in electronics engineering, working on thefailure mechanism induced by hot electrons in MES-FETs and HEMTs, and the Ph.D. degree in electricaland telecommunication engineering, working on hot-electron characterization, effects, and reliability ofGaAs- and InP-based HEMTs and pseudomorphicHEMTs, from the University of Padova, Padova, in1992 and 1997, respectively.

In 1995, he was with the University of Twente,Enschede, The Netherland, with a Human Capital and Mobility fellowship(within the SUSTAIN Network), where he worked on the dynamic behavior ofprotection structures against electrostatic discharge (ESD). Since 2002, he hasbeen an Associate Professor with the Department of Information Engineering,University of Padova. Within these activities, he published over 350 technicalpapers (of which more than 35 are invited papers and 5 received best paperawards). He is a Reviewer of several international journals. His research inter-ests are electrical characterization, modeling, and reliability of the following:1) microwave and optoelectronic devices on compound semiconductors; 2)RF-MEMS switches for reconfigurable antenna switches; 3) ESD protectionstructures; and 4) organic semiconductor devices.

Dr. Meneghesso was the recipient of the Italian Telecom Award for histhesis work in 1993. He has been the Technical Program Chair of Workshopon Compound Semiconductors Devices and Integrated Circuits held in Europe(WOCSDICE) 2001, General Chair of Heterostructures Technology Workshop(HETECH) 2001 and 2008, and General Chair of WOCSDICE 2007. He isin the steering committee of several European conferences, namely, Euro-pean Solid State Device Research Conference (ESSDERC), HETECH, andWOCSDICE. Since 2005, he has been serving for the IEEE InternationalReliability Physics Symposium in the TPC, and in 2009, he entered intothe management committee. He also served for several years for the IEEEInternational Electron Device Meeting: He was in the Quantum Electronicsand Compound Semiconductors subcommittee as a member in 2003, as Chairin 2004 and 2005, and as European Arrangements Chair in the ExecutiveCommittee in 2006 and 2007. He has also been involved in the Technical Pro-gram Committee of several international conferences: European Symposiumon Reliability of Electron Devices, Failure Physics and Analysis (ESREF),Electrical Overstress/ESD Symposium, International EOS/ESD Workshop, andInternational Conference on Solid State Devices and Materials. He has beenthe Associate Editor of the IEEE Electron Device Letter for the compoundsemiconductor devices area since 2007.

Guido Groeseneken (F’05) received the M.Sc. de-gree in electrical and mechanical engineering and thePh.D. degree in applied sciences from the KatholiekeUniversiteit Leuven (KUL), Leuven, Belgium, in1980 and 1986, respectively.

In 1987, he joined the R&D Laboratory, Interuni-versity Microelectronics Center (IMEC), Leuven,where he is responsible for research in reliabilityphysics for deep submicrometer CMOS technolo-gies. From October 2005 to March 2007, he wasalso responsible for the IMEC Post-CMOS Nan-

otechnology Program within IMEC’s core partner research program. Since2001, he has been a Professor with KUL, where he is the Program Directorof the Master in Nanoscience and Nanotechnology, and where he is alsocoordinating a European Erasmus Mundus Master program in nanoscienceand nanotechnology. He has made contributions to the fields of nonvolatilesemiconductor memory devices and technology, reliability physics of VLSItechnology, hot carrier effects in MOSFETs, time-dependent dielectric break-down of oxides, electrostatic-discharge (ESD) protection and testing, plasma-processing-induced damage, electrical characterization of semiconductors, andcharacterization and reliability of high-k dielectrics. Recently, he has alsointerest in nanotechnology for post-CMOS applications, such as carbon nan-otubes for interconnect applications, tunnel FETs for alternative nanowiredevices, etc. He has authored or coauthored more than 500 publications ininternational scientific journals and in international conference proceedings, sixbook chapters, and ten patents in his fields of expertise.

Dr. Groeseneken is an IMEC fellow in 2007. He has served as a technicalprogram committee member of several international scientific conferences,among which the IEEE International Electron Device Meeting (IEDM), theEuropean Solid State Device Research Conference (ESSDERC), the Inter-national Reliability Physics Symposium, the IEEE Semiconductor InterfaceSpecialists Conference, and the Electrical Overstress/ESD Symposium. From2000 to 2002, he also acted as European Arrangements Chair of IEDM. In 2005,he was the General Chair of the Insulating Films on Semiconductor (INFOS)conference organized in Leuven.




Documents

Electrical-Based ESD Characterization of Ultrathin-Body SOI MOSFETs