High capacitance density MIS capacitor using Si nanowires by MACE and ALD aluminadielectricI. Leontis, M. A. Botzakaki, S. N. Georga, and A. G. Nassiopoulou Citation: Journal of Applied Physics 119, 244508 (2016); doi: 10.1063/1.4954883 View online: http://dx.doi.org/10.1063/1.4954883 View Table of Contents: http://scitation.aip.org/content/aip/journal/jap/119/24?ver=pdfcov Published by the AIP Publishing Articles you may be interested in Ultra high density three dimensional capacitors based on Si nanowires array grown on a metal layer Appl. Phys. Lett. 101, 083110 (2012); 10.1063/1.4746762 Dispersive capacitance and conductance across the phase transition boundary in metal-vanadium oxide-silicondevices J. Appl. Phys. 106, 034101 (2009); 10.1063/1.3186024 Molecular-beam epitaxial growth of III–V semiconductors on Ge ∕ Si for metal-oxide-semiconductor devicefabrication Appl. Phys. Lett. 92, 203502 (2008); 10.1063/1.2929386 High density and program-erasable metal-insulator-silicon capacitor with a dielectric structure of SiO 2 ∕ HfO 2 –Al 2 O 3 nanolaminate ∕ Al 2 O 3 Appl. Phys. Lett. 88, 042905 (2006); 10.1063/1.2168227 Fabrication of a metal-oxide-semiconductor-type capacitive microtip array using Si O 2 or Hf O 2 gate insulators Appl. Phys. Lett. 85, 5412 (2004); 10.1063/1.1828226

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High capacitance density MIS capacitor using Si nanowiresby MACE and ALD alumina dielectric

I. Leontis,1 M. A. Botzakaki,2 S. N. Georga,2 and A. G. Nassiopoulou1,a)

1INN, NCSR Demokritos, Patriarchou Grigoriou and Neapoleos, Aghia Paraskevi, 153 10 Athens, Greece2Department of Physics, University of Patras, 26 504 Rion, Greece

(Received 13 January 2016; accepted 14 June 2016; published online 30 June 2016)

High capacitance density three-dimensional (3D) metal-insulator-semiconductor (MIS) capacitors

using Si nanowires (SiNWs) by metal-assisted chemical etching and atomic-layer-deposited

alumina dielectric film were fabricated and electrically characterized. A chemical treatment was

used to remove structural defects from the nanowire surface, in order to reduce the density of

interface traps at the Al2O3/SiNW interface. SiNWs with two different lengths, namely, 1.3 lm and

2.4 lm, were studied. A four-fold capacitance density increase compared to a planar reference

capacitor was achieved with the 1.3 lm SiNWs. In the case of the 2.4 lm SiNWs this increase was

�7, reaching a value of 4.1 lF/cm2. Capacitance-voltage (C-V) measurements revealed that, fol-

lowing a two-cycle chemical treatment, frequency dispersion at accumulation regime and flat-band

voltage shift disappeared in the case of the 1.3 lm SiNWs, which is indicative of effective removal

of structural defects at the SiNW surface. In the case of the 2.4 lm SiNWs, frequency dispersion at

accumulation persisted even after the two-step chemical treatment. This is attributed to a porous Si

layer at the SiNW tops, which is not effectively removed by the chemical treatment. The electrical

losses of MIS capacitors in both cases of SiNW lengths were studied and will be discussed.

Published by AIP Publishing. [http://dx.doi.org/10.1063/1.4954883]

I. INTRODUCTION

Si nanowires (SiNWs) are interesting building blocks

for several applications, including electronic devices, solar

cells, sensors, and energy harvesting devices. One of their

important applications is their use in high capacitance den-

sity metal-insulator-semiconductor (MIS) or metal-insulator-

metal (MIM) capacitors, in which the nanowires are used to

increase the capacitance density by the three-dimensional

(3D) increase of the Si surface area. Potential applications of

these capacitors are in autonomous portable microsystems,

or in power management integrated circuits (ICs). One of the

techniques for their massive and low cost production is

metal-assisted chemical etching (MACE), which gives verti-

cal Si nanowires of variable length on a large Si surface.1–6

For the use of SiNWs in any electronic device, it is essential

to minimize surface roughness and structural defects at their

surface, since these defects contribute to the formation of

active electronic states, which compromise electronic device

operation.

Three-dimensional (3-D) structuration is a general strat-

egy towards achieving high capacitance density devices. The

capacitance density (Cd) of a planar capacitor with a nano-

structured surface is given by

Cd ¼ e:S=ðt:AÞ;

where e is the dielectric constant of the insulator used, S is

the electrode surface area, t is the dielectric thickness, and A

is the top view area occupied by the device. Through

nanostructuration, we increase the electrode surface area,

thus increasing the capacitance density.

Several techniques are used for the 3D structuration of

Si for the above application. They include the electrochemi-

cal etching of Si for the formation of vertical cylindrical

pores of diameter in the micrometer range,7–9 the use of deep

reactive ion etching for the formation of high-aspect-ratio

trenches or pores in the Si wafer, randomly distributed or

arranged in a hexagonal arrangement for high packing

density of the 3D structures,10 nanotip array fabrication by

electron cyclotron resonance (ECR) plasma process,11 and

the formation of nanotubes12 or nanowires13,14 by bottom-up

techniques. The corresponding technique for Si nanowire

formation by the bottom-up approach is Chemical Vapor

Deposition (CVD), providing a network of randomly

oriented nanowires. Conformal deposition of dielectric and

metal on their surface has been achieved, and corresponding

metal-insulator-semiconductor (MIS) capacitors with a

capacitance density of 18 lF/cm2 (Ref. 14) were reported;

however this capacitance density was shown for a frequency

of only 1 kHz. In addition, the CVD process for nanowire for-

mation involved high growth temperatures (above �400 �C),

which makes integration with current back-end-of line

(BEOL) Si technology for integrated circuits (ICs) difficult.

On the other hand, MACE1–6 is a simple, low cost, high

throughput, and low temperature technique for producing

high-aspect-ratio nanostructures on Si. 3-D capacitors using

SiNWs by MACE were already demonstrated,6 using the

two-step MACE process for SiNW formation and a thermally

grown silicon oxide as dielectric. A capacitance density of

5.26 lF/cm2 was achieved; however, the capacitor operation

frequency was limited to a maximum of 1 kHz and thea)Email: A.Nassiopoulou@inn.demokritos.gr

0021-8979/2016/119(24)/244508/6/$30.00 Published by AIP Publishing.119, 244508-1

JOURNAL OF APPLIED PHYSICS 119, 244508 (2016)

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leakage current at 2 V was quite high (1.15� 10�5 A/cm2).

This means that the capacitor was not really operational. The

Si substrate used in Ref. 6 was highly doped n-type Si. To

our opinion, this was the reason of the high leakage currents

and the poor performance of the capacitor, since Si NWs by

MACE on highly doped p- or n-type Si are porous,15 and thus

inadequate for the formation of a good quality capacitor on

their surface. Leakage currents and an increased density of

interfacial states at the interface Si nanopillars/SiO2 are

expected.

In this work, we report on the MIS capacitors using

SiNWs produced by a single step MACE process, and a thin

alumina dielectric on their surface, produced by atomic-

layer-deposition (ALD). The SiNWs were formed on p-type

Si with low doping concentration. They are thus crystalline

and compact, without pores, contrary to the case of SiNWs

on pþ- or nþ-type Si. Prior to the deposition of the dielectric

layer, different chemical treatments were used, aiming at

minimizing interface states at the dielectric/SiNW interface,

as well as bulk states due to structural defects. The aim of

this work is to achieve high electronic quality capacitors,

with high capacitance density, as well as to assess the pro-

cess of chemical treatment of the SiNWs, used to reduce sur-

face and bulk parasitic electronic states. This is an essential

step towards using the SiNWs by MACE in any electronic

device, including solar cells. The electrical behavior of the

capacitors for two different lengths of SiNWs was tested and

discussed in detail.

II. EXPERIMENTAL RESULTS AND DISCUSSION

A. Sample fabrication

p-type, (100)-oriented, Czochralski-grown Si wafers,

with resistivity in the range of 1–2 X cm, were used. SiNWs

were fabricated by a single step MACE process, as described

in detail elsewhere.4,15 An aqueous chemical solution, com-

posed of 4.8 M HF (50%) and 0.02 M AgNO3, was used.

The process temperature was 30 �C and the immersion time

was 3 and 6 min, resulting, respectively, in SiNWs of 1.3 lm

and 2.4 lm. Following etching for SiNW formation, the sam-

ples were dipped in 50% HNO3 in order to completely dis-

solve the Ag dendrites and any other Ag residues from the

SiNW surface.

For the formation of the MIS capacitor, the following

process was used: The SiNWs were fabricated on selected

areas of the Si wafer, determining the capacitor area, con-

fined within 500 nm thick SiO2 field oxide.4 Prior to the dep-

osition of the dielectric layer, the SiNWs were subjected to

successive cycles of chemical treatment, in order to smooth

down any roughness coming from structural defects at their

surface. These defects introduce active electronic states,

which affect their electrical behavior. Two different chemi-

cal treatments were used, the first comprising a single cycle

of piranha cleaning in 1:1 v/v H2O2/H2SO4 solution for

30 min, followed by a dip in 2% per volume aqueous HF

solution at room temperature (RT) for 1 min. The second

chemical treatment comprised two successive cycles as

above, instead of one. After the chemical cleaning, a thin

alumina (Al2O3) layer was deposited on top of all the

samples by a Cambridge NanoTech atomic layer deposition

(ALD) system, at 200 �C, using 100 ALD cycles.16 The nom-

inal thickness of the alumina layer was 10 nm. The final step

of the MIS capacitor formation was the deposition and pat-

terning of the gate metal and the formation of a back ohmic

contact. Al deposition was performed by electron gun evapo-

ration, while lithography and Al etching were applied for

patterning the Al gate metal. The thickness of the deposited

Al gate metal layer was 300 nm. For the back ohmic contact,

Al deposition and annealing were also used. Finally, the

samples were subjected to a post-metallization annealing

at 430 �C for 1 h, in order to reduce interface states at the

alumina/Si interface and to improve the back ohmic contact.

A schematic representation of the MIS capacitor struc-

ture with the SiNWs by MACE is depicted in Fig. 1.

B. Structure, morphology, Si NW density,and calculated capacitance density

Scanning Electron Microscopy (SEM) images of the

SiNWs were obtained with a field emission scanning elec-

tron microscope (JEOL JSM-7401 F). Representative cross

sectional SEM images of the as-formed nanowires with a

6 min process time are depicted in Fig. 2(a), while Figs.

2(b)–2(d) depict SEM images of the NWs with both the

ALD alumina dielectric and Al gate metal deposited on

them. Fig. 2(b) depicts the whole length of the NWs, Fig.

2(c) their top part and Fig. 2(d) their bottom part in contact

with Si. It is clear from these last three images that the depo-

sition of both the dielectric and the metal is conformal to the

NW surface, with a slightly higher thickness of the Al layer

at the top half length of the NWs. The thickness of the Al

layer at the bottom of the NWs is of the order of 30–50 nm.

Continuity of the Al film covering the NWs with that of the

electrical Al pad was observed.

The measured maximum SiNW length of the as-formed

SiNWs for the 3 min MACE process was 1.3 lm, while their

diameter ranged from 50 to 150 nm, their inter-distance

being about 100–150 nm. For the 6 min process, the obtained

maximum SiNW length was 2.4 lm, while the other parame-

ters were similar to those of the 1.3 lm length SiNWs. By

considering a mean diameter of 100 nm, a cylindrical shape

and a mean inter-distance of 120 nm, the SiNW density was

calculated at d � 2� 109 SiNWs/cm2. The capacitance

density per cm2 in the two cases of SiNWs with 1.3 lm and

2.4 lm lengths, respectively, was calculated by considering a

simplified cylindrical geometry of the SiNWs and the

FIG. 1. Schematic representation of the MIS capacitor structure with the

SiNWs by MACE and the ALD alumina dielectric (Al/Al2O3/SiNWs

structure).

244508-2 Leontis et al. J. Appl. Phys. 119, 244508 (2016)

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geometrical parameters given above, deduced from the SEM

images. In practice, the SiNWs are not cylindrical and

their diameter is much smaller at their top parts. In order to

take into account this effect, we considered a mean SiNW

length of 1 lm and 2 lm, respectively. With the assumptions

described above, and considering an array of parallel cylin-

drical nanocapacitors, the capacitance of one nanowire was

calculated from the well-known formula

Ccyl ¼ 2pe0erðL=lnðb=aÞÞ; (1)

where e0 is the vacuum permittivity (e0¼ 8.85� 10�14 F/cm),

er is the dielectric constant of the dielectric (alumina), L is the

length of the SiNWs, b is the coaxial diameter of the SiNWs,

covered with the dielectric layer, and a is the bare nanowire

diameter. For the total device capacitance, we multiply the

capacitance of one nanowire by the nanowire density, d, and

we add the capacitance of the bottom surface outside the NWs

and the top NW surface. The values of 4.3 lF/cm2 for the

SiNWs with 1 lm mean length and 8.6 lF/cm2 for the SiNWs

with 2 lm mean length were calculated. These values are com-

pared with the experimental ones below.

C. Electrical characterization of the MIS capacitor

Capacitance-voltage (C-V) and current-voltage (I-V)

measurements were performed by using an IBM probe station,

combined with an HP 4284 precision LCR meter and an HP

4594 system. Measurements were performed in the frequency

range of 1 kHz–1 MHz at RT. The ac conductance-voltage

(G-V) characteristics of the MIS capacitor were also extracted

from measurements.

1. MIS capacitors with 1.3 lm long SiNWs

Fig. 3(a) shows C-V curves in the frequency range of

1 kHz–1 MHz for three different samples: (i) a planar capaci-

tor without NWs, (ii) a capacitor with 1.3 lm SiNWs sub-

jected to a single cycle of piranha/HF chemical cleaning, and

(iii) a capacitor with the same SiNWs as in (ii), but subjected

to two cycles of piranha/HF cleaning. The capacitor area was

50 lm� 50 lm in all cases. Fig. 3(c) depicts the leakage cur-

rent through all the devices, which in all cases lies within the

acceptable limits (value at �2 V< 10�9 A/cm2). At positive

voltages, a slight increase in the leakage current of the SiNW

MIS capacitor was observed, compared to the planar capaci-

tor, remaining however below 10�8 A/cm2.

The comparison of the capacitance at accumulation in all

cases reveals that in samples with SiNWs subjected to a sin-

gle piranha/HF treatment, there is threefold increase in the ca-

pacitance compared to that of the reference capacitor without

SiNWs. This increase is �4 in the case of the double piranha/

HF treated samples. The difference between these two cases

of chemically treated SiNWs can be attributed to parasitic

capacitive effects. In the case of the as-formed SiNWs, a

large number of structural defects exist on the SiNW surface,

which form a parasitic series capacitor, contributing to the

decrease in the total capacitance. By smoothing out these

structural defects, the total capacitance increases. The

obtained experimental value for the double chemical treated

samples is �2.5 lF/cm2, which is not far from the calculated

value of 4.3 lF/cm2 in Sec. II B.

An interesting feature of Fig. 3(a) is that there is almost

no frequency dispersion at accumulation for the devices sub-

jected to the two-cycle chemical treatment. This is attributed

to the effective removal of the structural defects at the SiNW

surface and the effective reduction of leakage current.

Piranha cleaning leads to surface chemical oxidation and the

subsequent HF dip removes the defected oxide, resulting in a

lift-off of the existing SiNW surface nanostructuring, and

thus to surface smoothing. With the single piranha/HF

treatment, part of these defects still remains, and this seems

to be the origin of the observed frequency dispersion. The

observed limited frequency dispersion is an important

advancement compared to the previously published results.15

In other reported 3-D silicon capacitors,5,6,13,14,17 an impor-

tant frequency dispersion at accumulation and a sharp

decrease of Cacc at frequencies above 1 kHz were observed.

FIG. 2. (a) Cross sectional SEM

images of the as-grown SiNWs by

MACE for a 6 min etching time. (b) Si

NWs after ALD Al2O3 layer and Al

metal deposition, (c) and (d): top and

bottom parts of the SiNWs shown in

(b) at higher magnification.

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This frequency dispersion was observed in 3D MIS capaci-

tors not only in the case of high-k deposited dielectrics5 but

also in capacitors with low-k deposited dielectric.6,14,17

From the experimental value of Cacc of the planar capac-

itor and the known thickness of the deposited Al2O3, a

dielectric constant of 7.1 was evaluated for the ALD Al2O3

layer used. This value is in good agreement with previously

published results.18,19

Another interesting feature depicted in the C-V charac-

teristics of Fig. 3(a) is the VFB shift in the case of SiNW

capacitors, compared to the planar ones. This is attributed to

fixed interface charges, Qf , at the Al2O3/Si interface.20 In

general, the fixed charge density of a MIS structure is deter-

mined by the equation,

Qf ¼ ðCox=qAÞðums þ VFBÞ; (2)

where Cox is the measured dielectric capacitance at accumu-

lation, q is the elementary charge, ums is the work function

difference between metal (Al) and silicon, and A is the

capacitor area. For ums¼ 0.87 V,21 the value of Qf for the

planar reference capacitor was calculated and found to be

4.4� 1012/cm2, which is in agreement with previously pub-

lished results for ALD Al2O3 thin films on Si.16 For the sin-

gle- and double-cycle treated Piranha/HF SiNWs capacitors,

Qf was calculated to be 1.5� 1013/cm2 and 7.3� 1012/cm2,

respectively. For the calculation, we considered the top view

capacitor area and not the electrode surface area. This is one

of the reasons why the obtained values are relatively high.

These results demonstrate that the SiNW capacitors exhibit

higher values of fixed oxide charges at the alumina/Si inter-

face, compared to the planar capacitor, due to structural

defects at the large SiNW surface (increased electrode sur-

face area). The double-cycle surface chemical treatment

applied to the SiNWs prior to the alumina deposition is quite

effective in reducing these parasitic charges.

2. MIS capacitors with 2.4 lm long SiNWs

The 2.4 lm SiNWs show a slightly different behavior

than the 1.3 lm SiNWs. The corresponding C-V characteris-

tics are depicted in Fig. 3(b) for single- (i) and two-cycle (ii)

piranha/HF chemically treated samples. The main difference

is that for the 2.4 lm SiNWs the frequency dispersion at

accumulation (more than 20%) persists even after the two-

step chemical treatment. This is attributed to the fact that the

longer SiNWs show some porosity at their tops, which

increases with increasing SiNW length (see Fig. 3(d)). On

the other hand, in Fig. 3(b) we see that in this case there is

no VFB shift between samples with one- and two-cycles of

chemical treatment. This means that in the specific case of

SiNW length, the interface states at the SiNW surface do not

significantly change between the single and double step

chemical treatments. For the single chemical treatment, the

capacitance at accumulation ranges from 2.7 lF/cm2 at 1 kHz

to 2.1 lF/cm2 at 1 MHz. For the double treatment, the corre-

sponding values lie between 4.1 lF/cm2 and 3.3 lF/cm2,

respectively.

The maximum value of 4.1 lF/cm2 with the two-step

treatment is almost twice as high as in the case of the 1.3 lm

long SiNWs, but is still lower than the theoretically calcu-

lated value in Sec. II B (8.6 lF/cm2). On the other hand,

the measured leakage current in both cases of chemical

FIG. 3. (a) CV characteristics at differ-

ent frequencies in the range of 1

kHz–1 MHz of a planar capacitor (i),

and capacitors with 1.3 lm SiNWs (ii),

(iii), subjected to one- (ii) and two-

cycles (iii) of piranha/HF treatment.

(b) C-V curves as in (a) for the case of

2.4 lm SiNWs. (c) Leakage current

density of the different capacitors

described in the inset. The smaller

leakage current in the case of the 2.4

lm SiNWs is attributed to the exis-

tence of a porous Si layer (dielectric)

at the top of the nanowires. (d)

Schematic representation of the 1.3 lm

and the 2.4 lm Si NWs. The porous

layer at the top of SiNWs in the case of

the 2.4 lm NWs persists after the two-

step chemical treatment ((d) (ii)). This

is not the case for the 1.3 lm SiNWs

((d) (i)).

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treatments remains low (about 10�9 A/cm2 at �1.5 V, quite

close to that of the planar capacitor).

Another feature depicted in the characteristics of Fig.

3(b) is that the single-step-treated samples show significant

frequency dispersion at the inversion regime, which is more

pronounced at lower frequencies, but persists even at 1 MHz.

The frequency dispersion at inversion can be attributed to

bulk traps, resulting from the existence of the porous struc-

ture at the tops of the SiNWs. The schematic representation

of Fig. 3(d) shows (i) the SiNWs without the porous layer

and (ii) the SiNWs with the thin porous Si layer on top. One

could also expect that the existence of this porous layer dete-

riorates also the quality of the ALD alumina layer deposited

on that specific part of the SiNW surface area. The presence

of the porous Si layer can explain the frequency dispersion at

inversion, more pronounced at lower frequencies, as

expected. The fact that such frequency dispersion at inver-

sion was not observed in the case of 1.3 lm long SiNWs sug-

gests that the porous structure in that case was thinner and

thus effectively removed by the chemical treatment. In the

case of the 2.4 lm long nanowires, even though frequency

dispersion at inversion disappears after the double step

chemical treatment, it still persists at accumulation. This sug-

gests that the double chemical treatment smoothed out struc-

tural defects at the nanowire surface, but does not fully

remove the porous layer at the SiNW tops.

3. Electrical losses

The electrical losses of the MIS capacitors were studied

by measuring the loss tangent (tan d) versus voltage (V) for

the single- and double-step chemically treated SiNWs of 1.3

and 2.4 lm length. Tan d is expressed by the equation,

Tan d ¼ G=x Cox; (3)

where x is the angular frequency and Cox is the capacitance

at accumulation.

The conductance was extracted from experimental data

within the series resistance model. The corresponding curves

are depicted in Fig. 4 (right vertical axes).

It is obvious that following a single step piranha/HF

chemical treatment in both cases of 1.3 lm and 2.4 lm

SiNWs (Figures 4(a1) and 4(b1)), electrical losses appear in

both weak inversion, where interface traps are dominant,

and/or in deep inversion, where bulk traps are dominant. A

small peak at the transition from accumulation to depletion,

attributed to interface states, is observed in both cases, not

revealed in the main curve of (b1) due to the different scale,

but highlighted in the inset at higher magnification. Bulk

traps are slow, since the corresponding peaks are more pro-

nounced at 1 kHz compared to 1 MHz. They are also

more evident in the case of the 2.4 lm SiNWs compared to

those of 1.3 lm nanowires (the corresponding peaks at the

G/xCox characteristic are almost ��10 higher in intensity

in this second case). Interface traps in weak inversion do not

change significantly with frequency.

After the double step of piranha/HF chemical treatment

and for both cases of 1.3 lm and 2.4 lm SiNWs, bulk traps

at inversion almost disappear; however, fast responding

interface trap states at depletion appear, which are more pro-

nounced in the case of the 2.4 lm SiNWs (see Figs. 4(a2)

and 4(b2)). This behavior could be explained by considering

that the chemical treatment smooths out the surface of

SiNWs, this smoothing being more effective after the second

cycle of treatment. Smoothing reduces the existing bulk

traps; however, it induces fast interface traps with a signature

at depletion and/or weak inversion. Using Hill method22 for

the case of the 1.3 lm SiNWs, the density of interface traps

was calculated from the G/x-V peak in weak inversion and

FIG. 4. Capacitance density (left verti-

cal axis) and G/xCox (right vertical

axis) versus voltage for 1.3 lm SiNWs

(a1), (a2) and 2.4 lm SiNWs (b1), (b2)

for a single piranha/HF treatment cycle

(a1), (b1) and a double piranha/HF

treatment cycle (a2), (b2).

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values of �2–3� 1011 cm�2 eV�1 after 1 cycle of piranha/

HF treatment and 1� 1013 cm�2 eV�1 after the two cycles of

piranha/HF treatment were obtained. This is consistent with

the qualitative behavior deduced from Fig. 4.

III. CONCLUSIONS

MIS capacitors with 3D modulated surface were fabri-

cated on p-type Si using SiNWs by MACE and ALD alu-

mina dielectric. A two-step chemical treatment was used to

remove structural defects from the SiNW surface. This was

fully successful in the case of 1.3 lm SiNWs. However in

the case of 2.4 lm SiNWs, a porous Si layer on top of

SiNWs still remained even after the second chemical clean-

ing cycle. This porous layer was responsible for the remain-

ing frequency dispersion of C-V curves at accumulation.

Frequency dispersion was also observed at inversion after

the first chemical treatment cycle, which disappeared after

the second such cycle. The 2.4 lm SiNWs exhibited a maxi-

mum capacitance density at accumulation of 2.6 lF/cm2,

which was 4.3 times higher than that of the corresponding

planar capacitor.

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