Name: Shyamveer Singh Regno:11205816

Aim: Implement full adder and half adder,full ,full and half subtractor.

Rollno:B-54

Apparatus: Xilinx Ise (.2i.

Half adder Implementation : Truth Table: a b sum carry

0 0 0 0

0 1 1 0

1 0 1 0

1 1 1 1

Full adder truth table:

a b c sum carry

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

Half Separation:

a b Difference Borrow

0 0 0 0

0 1 1 1

1 0 1 0

1 1 0 0

Full separator :

a b c difference Borrow

0 0 0 0 0

0 0 1 1 1

0 1 0 1 1

0 1 1 0 1

1 0 0 1 0

1 0 1 0 0

1 1 0 0 0

1 1 1 1 1

THORY : Full Subtractor : A logic Circuit Which is used for Subtracting Three Single bit Binary numbers is known as Full Subtractor. The half-subtractor is a combinational circuit which is used to perform subtraction of two bits Full adder and half adder used to add three and two bit data respectively. Veri log code:

module halfadd(a,b,sum,carry);

input a,b;

output sum,carry;

assign sum=((~a)&b)|(a&(~b));

assign carry=a&b;

endmodule

RTL Schematic:

Output Waveform:

Full Adder Implementation : Verilog Code: module fulladder(a,b,c,sum,carry);

input a,b,c; output sum,carry; wire w1,w2,w3,w4,w5,w6,w7,w8,w9,w10,w11,w15,w16,w17;

not(w1,a); not(w2,b); not(w3,a); not(w4,c); not(w5,b); not(w6,c); and(w7,w1,w2,c); and(w8,w3,b,w4); and(w9,a,w5,w6); or(sum,w7,w8,w9,w10); not(w11,a);

not(w12,b); not(w13,c); and(w14,w11,b,c); and(w15,a,w12,c); and(w16,a,b,w13); and(w17,a,b,c); or(carry,w14,w15,w16,w17);

endmodule

RTL schematic:

Output Wave form:

Half subtractor Implementation :

Verilog Code: module halfsub(a,b,diff,borrow);

input a,b; output diff,borrow; assign diff=((~a)&b)|((~b)&a);

assign borrow=((~a)&b);

endmodule

Output Waveform:

Full subtraction:

Verilog Code:

mdule fullsub(a,b,c,diff,borrow);

input a,b,c; output diff,borrow; wire w1,w2,w3,w4,w5,w6,w7,w8,w9,w10,w11,w12,w13,w14,w15,w16,w17,w18,w19;

not(w1,a); not(w2,b); not(w3,a); not(w4,c); not(w5,b); not(w6,c); and(w7,w1,w2,c); and(w8,w3,b,w4); and(w9,a,w5,w6); and(w10,a,b,c); or(diff,w7,w8,w9,w10); not(w11,a);

not(w12,b); not(w13,a);

not(w14,c); not(w15,a); and(w16,w11,w12,c); and(w17,w13,b,w14); and(w18,w15,b,c); and(w19,a,b,c); or(borrow,w16,w17,w18,w19);

endmodule RTL schematic : Output Waveform :