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Design Techniques for NBTI-TolerantPower-Gating Architectures

Andrea Calimera, Member, IEEE, Enrico Macii, Fellow, IEEE, and Massimo Poncino, Member, IEEE

AbstractWhile negative bias temperature instability (NBTI)effects on logic gates are of major concern for the reliability of dig-ital circuits, they become even more critical when considering thecomponents for which even minimal parametric variations impactthe lifetime of the overall circuit. pMOS header transistors used inpower-gated architectures are one relevant example of such com-ponents. For these types of devices, an NBTI-induced current ca-pability degradation translates into a larger IR-drop effect on thevirtual-Vdd rail, which unconditionally affects the performanceand, thus, the reliability of all power-gated cells. In this brief,we address the problem of designing NBTI-tolerant power-gatingarchitectures. We propose a set of efficient NBTI-aware circuit

design solutions, including both static and dynamic strategies, thataim at improving the lifetime stability of power-gated circuits bymeans of oversizing, body biasing, and stress-probability reduc-tion while minimizing the design overheads. Experimental resultsprove the effectiveness of such techniques when applied to a suiteof benchmarks mapped onto a 45-nm industrial CMOS technologylibrary. In particular, we prove that it is possible to achieve morethan ten times of lifetime extension with respect to a traditionalpower-gating approach.

Index TermsNegative bias temperature instability (NBTI),power gating, reliability, sleep transistor.

I. INTRODUCTION

S CALING OF MOS device geometries poses hard limita-tions on the development of new generations of integratedcircuits. In particular, reliability has been indicated as one ofthe most serious concerns [1], [2]. Adverse on-chip operatingconditions, characterized by extremely high substrate tem-perature, accelerate the degradation of the electromechanicalproperties of both active (i.e., transistors) and passive (i.e.,interconnects) devices. Electromigration, hot-carrier injection,and time-dependent dielectric breakdown have been indicatedas the main responsible of reliability decrease [3]. If we restrictour attention to the aging sources, negative bias temperatureinstability (NBTI) has emerged as the dominant factor in deter-mining the lifetime of digital devices [4].

In CMOS circuits, NBTI effects occur in p-type transistorswhen a logic 0 is applied to the gate terminal (gate-to-sourcevoltage Vgs = Vdd, i.e., negative bias). Under this condition,called the stress state, the magnitude of the threshold voltage(Vth) increases over time, resulting in a degradation of the drive

Manuscript received July 17, 2010; revised October 10, 2010; acceptedJanuary 29, 2012. Date of publication March 8, 2012; date of current versionApril 11, 2012. This paper was recommended by Associate Editor C.-C. Wang.

The authors are with the Dipartimento di Automatica e Informatica, Politec-nico di Torino, 10129, Torino, Italy.

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TCSII.2012.2188457

current. In contrast, when a logic 1 is applied to the gateterminal (Vgs = 0), NBTI stress is actually removed. The lattercondition, called the recovery state, induces a progressive yetpartial recovery of the Vth.

The impact of NBTI in random logic manifests itself as anincrease of the propagation delay. Increased Vth reduces infact the drive current of individual gates, which thus requiremore time to propagate the input signals, and might then nolonger meet the timing constraints [5]. To overcome this issue,a number of recent works proposed various design techniquesto compensate and/or tolerate such NBTI-induced effects

[6][8]. The basic idea behind these approaches is to iden-tify the gates which are responsible for the overall perfor-mance degradation (i.e., critical cells) and selectively applygate/transistor resizing [6] to guarantee larger design marginand/or circuit transformation [7] (like NBTI-aware synthesisand technology mapping) to maximize the use of the standardcells that show smaller NBTI sensitivity. Different from thesestatic design-time solutions, the authors of [8] propose the useof adaptive techniques to dynamically compensate for NBTIeffects during the lifetime of the circuit.

Such solutions are effective because the total delay degra-dation of a circuit is usually significantly smaller than that ofindividual devices, on the order of a few percent per year ofoperation [6]. This is mainly due to the fact that the propagationdelay of a circuit consists of the sum of rising and fallingtransitions, and NBTI only affects rising transitions. Moreover,the stress time of some cell may be extremely low due to thelogical structure of the circuit, thus masking the aging effect of0 values.

Nevertheless, there exist special devices for which the stresstime is dominant, which thus represent a concentrated sourceof timing failure [9]. For these components, even a minimalvariation on the electrical parameters drastically impacts theperformance of the overall circuit. The sleep transistors usedin power-gated architectures are a significant example of suchdevices: Due to accumulated active periods (i.e., when thecircuit is not idle), NBTI effects induce a progressive increaseof the channel resistance of the sleep transistors, which, inturn, causes a larger IR drop between the real Vdd and thevirtual Vdd (at which the gated cells are connected). As a finalresult, the propagation delay of all the gated cells suffers from asensible increase, no matter if it is a rising or a falling transition,independently of the stress time of the local input signals.

While standard power-gating flows [11][19] ignore thedeleterious effects of NBTI on sleep transistors, in this brief,we present several design techniques for an effective imple-mentation of NBTI-tolerant power-gating architectures. Theproposed solutions, which exploit static and dynamic strategies,aim at compensating the aging effects on the sleep transistors,

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thus guaranteeing maximum lifetime stability of the power-gated circuits. We describe seven design solutions represent-ing different combinations of three main mechanisms used tocompensate Vth increase: 1) sleep-transistor oversizing (OS),2) body biasing (BB), and 3) equivalent stress-time reductionof the sleep-transistor driving signal. Each technique, charac-terized by its own aging-versus-leakage tradeoff, is appliedto several benchmarks, which have been synthesized onto a45-nm industrial CMOS technology using a power-driven de-sign flow.

Experimental results define the basic guidelines to be usedfor the design of sleep transistors that are NBTI tolerant andemphasize the effectiveness of the proposed design methodolo-gies in terms of lifetime extension (more than ten times in thebest case) and leakage overhead.

II. BACKGROUND

A. BTI Effects on PMOS Transistor

BTI has emerged as the most insidious source of perma-nent time-dependent variation of transistor characteristics. Themostly affected parameter is the threshold voltage Vth, whoseabsolute value increases over time, thus causing the shift ofother electrical parameters, such as the drive current Ids and thetransconductance Gm. Even if both n- and p-type MOS transis-tors suffer from BTI-induced degradation, at typical operatingfields of SiO2, BTI is relevant only for pMOS transistors undernegative gate bias NBTI (i.e., Vgs < 0).

We summarize here the basic factors that impact NBTIeffects using, as reference, the reactivationdiffusion model[10]. A simplified version of such a model is described in thefollowing equations:

Stress : Vgs = Vdd Vth kseEakT (t tstr)

1

4 (1)

Recovery : Vgs = 0 Vth kr

t trcv

t(2)

where kv and kr are two parameters whose magnitude dependson a few technological parameters (like channel strain andnitrogen concentration), k is the Boltzmann constant, T is thelocal operating temperature of the device, Ea is a technology-independent parameter that guarantees the convergence of themodel, and tstr and trcv correspond to the times at which thestress and the recovery phases begin, respectively.

The above equations highlight the relevant features of

NBTI.1) During stress phases (t > tstr), the shift in Vth increases

with time as a power law exponent of one-fourth, while itshows an exponential relationship with temperature.

2) As soon as the stress is removed (t > trcv), a significantfraction of broken SiH bonds are annealed, thus induc-ing a partial Vth recovery.

3) The Vth recovery is independent of temperature andtransistor BB.

4) The final Vth is frequency independent; in other terms,it is the total stress time that matters.

From the aforementioned observations, it is possible to de-rive an additional property; since aging is independent of the

frequency of the waveform applied to the gate terminal and itis the total stress time that matters, a generic waveform can be

modeled as a periodic one with the same amount of stress time,thus allowing the use signal probabilities for the evaluation ofthe effective aging. In other words, NBTI can be modeled as afunction of the gate signal stress probability

Vth = K t1

4 (3)

where K is a parameter which lumps all the technologicalconstants and considers the operating conditions of the device.

B. Power-Gating Basics

Power gating is one of the most effective leakage reductiontechniques for deep-submicrometer technologies. It is based onthe principle of adding switches (i.e., sleep transistors) in serieswith the pull-up and/or pull-down network of logic blocks, thuscreating an intermediate virtual rail (i.e., virtual Vdd) or virtualground (i.e., virtual GN D). In the idle mode, the sleep transistoris off, and the pull-up/pull-down path is cut. In this condition,the logic gates are ideally isolated from power supply/ground

rail and sensibly reduce their subthreshold leakage current.Conversely, in the active mode, the sleep transistor is on; thenormal circuit functionality is guaranteed, but due to the on-resistance of the sleep transistor, the logic gates connectedto it are slowed down. Therefore, proper sizing of the sleeptransistor, and thus its on-resistance, is of primary importancewhen designing power-gated architectures.

Although the power-gating version using a footer has beenhistorically very popular in the literature [11], [12], the useof header pMOS switches has also become widespread [13],[14]. The two choices represent different tradeoffs betweensleep-transistor area and leakage. On one hand, nMOS sleeptransistors are more conductive than pMOS ones; thus, from

the area point of view, the use of nMOS sleep transistors ispreferable. On the other hand, pMOS transistors have a betterleakage characteristic than nMOS.

Another important issue in the choice of pMOS or nMOSsleep transistors is technology [15]. Usage of nMOS sleeptransistors requires triple-well CMOS process; conversely, inthe case of a pMOS sleep transistor, the p-substrate easily sep-arates its n-well from other n-wells of pMOS transistors usedin normal cells. For this reason, pMOS header transistors areusually preferred by semiconductor vendors.

III. CHARACTERIZATION OF NBTI EFFECTS ON

POWER-G ATED CIRCUITSThis section describes the customized SPICE-based frame-

work that we have implemented for the assessment of NBTI-induced effects on power-gated circuits. Fig. 1 shows the flowof the proposed two-phase methodology. In the first phase, theaging of the sleep transistor is evaluated in terms of currentcapability degradation. The latter is then used in the secondphase to estimate the delay degradation of the power-gated logiccircuit.

Sleep-Transistor Current Capability Degradation: Thisanalysis consists of a two-step simulation: the prestress sim-ulation phase, in which we estimate the aging effects on thepMOS sleep transistor, and the poststress simulation phase, in

which the stress information is integrated into the pMOS deviceparameters.

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Fig. 1. NBTI-characterization flow for pMOS sleep transistor.

According to the properties of the sleep signal (defined by itszero static probability and voltage level), and the user-definedenvironmental setup (Vdd voltage, virtual-Vdd voltage, tem-perature, BB Vbs, and temperature), the prestress simulationcomputes the aging of the pMOS sleep transistor after a user-defined usage time.

The amount of aging, calculated on the base of the built-in aging models integrated into Synopsys HSPICE and thetechnology parameters provided by the silicon vendor, is thentranslated and annotated into device parameter degradation,i.e., threshold voltage degradation (i.e., Vth). As shown inFig. 1, during poststress simulation, the NBTI-induced Vthdegradation is modeled using a voltage source on the gate

terminal of the sleep transistor. At the end of the pre- andpoststress simulations, we have a complete characterization ofthe current drive profile before and after NBTI stress. In otherwords, we are able to estimate the degradation over time ofthe maximum current drained by the pMOS sleep transistor(Ids = Ids Ids), for a given value of usage time and forany operating condition.

Circuit Delay Degradation: The knowledge of the degradedvalue of the maximum drain current Ids allows estimating theactual delay degradation of the power-gated logic block, asfollows. Since the sleep transistor operates in the triode region,it behaves as a resistor. The value of such a resistance afteraging is given by

Rsleep = (Vdd VVdd)/I

ds. (4)

Given the active current Ion drained by the power-gated circuitfrom the virtual rail,1 we can now estimate the new voltage dropacross the sleep transistor as

VVdd = R

sleep Ion. (5)

The IR-drop voltage between the real Vdd and the virtual Vddis finally used to estimate the actual delay degradation of thegated logic block.2

1We consider as Ion the worst case active current drained by the circuit at

time zero.2Technology-dependent derating factors are used to estimate the delayvariation due to VVdd variation.

IV. NBTI-AWARE SLEEP-T RANSISTOR DESIGN

Since NBTI effects on sleep transistors induce performanceslowdown throughout the lifetime of the circuit, it is importantto identify a set of effective low-cost NBTI-tolerant implemen-tations of power gating. In the sequel, we present some possiblesolutions, in which aging is controlled by means of three basic

strategies, i.e., transistor OS, BB, and control of equivalentstress probability. Each technique results into some area andleakage overheads; thus, it is possible to combine them intohybrid solutions, which can achieve better tradeoffs betweenleakage and aging. We will first outline the basic featuresof the three strategies and eventually describe their possiblevariants.

Sleep-Transistor OS: The pMOS sleep transistor can be upsized in order to compensate for NBTI-induced current capa-bility degradation over time. The size of the transistor does nothave a direct impact on the amount of Vth shift, i.e., it is not anexplicit parameter in the equation describing the drift in thresh-old voltage. Rather, using a larger sleep transistor implies larger

currents, thus compensating the current degradation induced byNBTI. In other words, up sizing provides a larger guard bandand, thus, more functionality margin. Conceptually, if the sizeof the sleep transistor that guarantees the functionality of thecircuit at time zero is Wsleep and the drain current degradationafter the required lifetime is , then the resulting oversizedsleep-transistor width is simply given by Wsleep = Wsleep(1 +

). Needless to say, increasing the size of the sleep transistorresults in larger area, larger dynamic power, and increasedleakage current. All the three overheads increase linearlywith .

BB: In a standard CMOS configuration, the bulk terminalof each pMOS transistor is connected to the power supply

(i.e., Vb = Vdd). However, by varying the bulk voltage Vb, itis possible to control the body effect and thus modulate thethreshold voltage Vth and the current drive of the transis-tors: Vth decreases for Vb < Vdd [forward body bias (FBB)]and increases for Vb > Vdd [reverse body bias (RBB)]. Thetwo methods have been widely used for controlling processvariability (specifically, FBB, to speed up devices showingdegraded performance after fabrication), and for low-powerdesign (RBB, to reduce the subthreshold leakage by selectivelyraising Vth).

BB represents an attractive solution for NBTI-aware design.At first glance, one may imagine that FBB can be used, alone, tocompletely recover any degradation in the sleep transistor Vthand bring the drain current to exactly meet the target specifica-tion. The amount of FBB, however, is severely constrained byseveral issues. First, Vb must be larger enough to guarantee thecorrect functionality of the transistor, namely, source-to-bulkvoltage larger than the built-in potential of the p-n junctions.Second, but not for importance, the reduction in Vth causedby FBB translates into an exponential increase of subthresholdleakage (in fact, Isub e

Vth/kbT).Therefore, in order to alleviate such leakage overhead, it is

preferable to apply FBB in conjunction with RBB, followingan adaptive BB (ABB) style: During the active mode, when thesleep transistor is turned on (i.e., under NBTI stress), applyingFBB guarantees more current margin, extending the lifetime of

the entire circuit; during idle periods, using RBB reduces thestatic power consumption.

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It is important to notice that, although NBTI recovery isnot directly affected by bulk polarization, the substrate underRBB is subject to substrate hot-carrier injection [2]. Under thiscondition, the carriers in the substrate, which are driven by thesubstrate field toward the SiSiO2 interface, may gain enoughkinetic energy to overcome the surface energy barrier and getinjected into the gate oxide, where some of them are trapped,inducing Vth instability.

Stress-Probability Control (p0): As described in Section II,NBTI aging effects occur only during stress; therefore, thelarger the zero probability of the sleep signal, the larger theaging of the sleep-transistor characteristics. However, thestatic zero probability of the sleep signal is not a free designvariable by itself; it depends on the actual workload and theresulting idle periods of the circuit. Nevertheless, it is possibleto distribute the NBTI-induced stress over multiple sleeptransistors. This idea of multiple parallel sleep transistors hasbeen also used to dynamically compensate for performancevariations of different nature (temperature, variability, and

NBTI aging) [17], [18].For example, suppose that we duplicate the sleep transistor(i.e., two sleep transistors ST1 and ST2), so that the stressperiod Tstress (i.e., the time in which the sleep signal is at zero)can be time multiplexed over the two transistors. This impliesthat, for the first half period of duration Tstress/2, ST1 is onand ST2 is off while, for the other half period, ST1 is off andST2 is on. Then, both ST1 and ST2 are stressed for half time.

This scheme can be generalized by assuming that the originalsleep transistor consists of n equally sized parallel subsleeptransistors (as it is usually done) and adding m redundantsubsleep transistors. Since, at each period, only n over n + mtransistors must be activated, in order to guarantee the proper

current capability, the new zero probability P

(Vg=0) becomesP(Vg=0) = P(Vg=0) [1m/(n + m)] . (6)

From an overhead viewpoint, this approach is equivalent tooversizing the sleep transistor by a factor = 1 + m/n. Fur-thermore, we should consider the area and power overheadsrequired to implement the selection of m signals out of n + mones (e.g., a shift register ofn + m bits plus the proper wiring).

Hybrid Approaches: The OS and p0 strategies can extendthe lifetime of the power-gated circuit at the cost of bothincreased area and leakage. Integrating such techniques withRBB might offer a solution to achieve the best tradeoff be-tween reliability and power efficiency. While, in the standard

approaches, the bulk voltage Vb of a pMOS is set, statically, toits nominal value Vdd, here, we consider a dynamic approach inwhich, for both OS and p0, the sleep transistor can be reversebiased.

V. EXPERIMENTAL RESULTS

For the validation of the proposed power-gating strategies,we used as benchmarks the circuits in the ISCAS85 suite [20].Each circuit is assumed to be fully power gated (i.e., all cells areconnected to the same virtual-Vdd rail) and was mapped onto a45-nm CMOS library by STMicroelectronics using SynopsysDesign Compiler for synthesis and Synopsys ICCompiler for

the placement of the cells. The methodology presented in [16]was adopted to determine the maximum active current Ion of

Fig. 2. Normalized lifetime of the ISCAS85 benchmarks.

each benchmark. The resulting current values were then usedas upper bounds to the sizing of the sleep transistors.

The nominal width of the sleep transistor Wsleep is chosen sothat the maximum virtual-Vdd voltage drop across it equals 10%of Vdd (110 mV) when Ion is flowing. Although this voltagedrop may appear as a relatively large value, it corresponds toa minimum leakage choice, which is the main target of ouroptimization flow. The sleep transistor is customly designed asa standard cell that can be seamlessly used by the synthesisengine [19]; as such, since the height of a standard cell isconstrained, the desired width is obtained by putting multipletransistors in parallel.

The analysis framework described in Section III has beenimplemented using HSPICE built-in reliability analysis modelas a basis. This allowed us to explore NBTI-aware designtechniques in a practical fully automated analysis environment.

Ad hoc TCL scripts have been written to synchronize pre-and poststress simulations, as well as the estimation of delaydegradation Dp of the power-gated logic block, which is basedon technology-dependent propagation delay derating factors(Dp/Vdd).

Fig. 2 shows the lifetime results for the ISCAS85 bench-marks. The plot shows the normalized results with respect tothe case of a standard power-gating approach (2.1 years). Wedefine lifetime as the time required by the circuit to degrade itsperformance by 15% with respect to its time-zero performance.

Each group of bars denotes the lifetime for a benchmarkusing the various strategies. The group marked with avg repre-sents the average over all benchmarks. Results refer to a givenprobability (namely, 40%) of the sleep signal, i.e., percent oftime spent in the idle state; the latter is a parameter of thecharacterization step, and any value can be used. Aging willclearly be proportional to the time spent in the idle state.

Before discussing the results, we first detail the specificparameters that identify the various schemes.

1) OS: a sleep transistor with size 20% larger than thenominal case ( = 0.2).

2) FBB: Vb = 0.75 Vdd.3) RBB: Vb = 2.5 Vdd.4) p0: Equivalent stress probability of the sleep signal is

lowered to 50% using m = n.5) ABB: Vb = 0.75 Vdd during active periods, and Vb =

2.5 Vdd during idle periods.

OS+RBB and p0+RBB are the combinations of the basicsolutions.

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TABLE ILEAKAGE OVERHEAD PER YEAR OF LIFETIME EXTENSION

As the bar chart shows, all the proposed techniques but RBByield significant improvements of the lifetime. RBB is howeverreported for the sake of comparison as a purely leakage-orientedsolution. As a matter of fact, even the combination of RBB

with other schemes negatively impacts the effectiveness of thebaseline scheme.In general, OS yields the best results, extending lifetime by

more than eight times with respect to the baseline. Combinationwith RBB (i.e, OSRBB) does not significantly affect the effec-tiveness ofOS. FBB and ABB have comparable results (about5 lifetime improvement), while p0 is not very effective.

Lifetime results must be weighted against their overheads,area, and particularly leakage. Concerning area, the variousmethods have comparable overheads, ranging from 6% (FBBand RBB) to 8.2% (p0). These figures refer to the overallarea overhead, i.e., with respect to the original power-gatedcircuit.

The variance of leakage overhead is much larger, as shownin Table I. The table reports the percentage of leakage powerpenalty paid for each year of lifetime extension, i.e., leak-age/lifetime ratio (LLR). A smaller LLR clearly identifies abetter solution, i.e., less leakage to obtain the same lifetime.

We can observe that OS remains very competitive evenfrom the leakage standpoint (LLR = 2.38%), whereas FBBalone expectedly has the highest LLR (32.76% on average),ending up being the worst scheme. ABB, even if it reducesthe leakage cost, owing to the application of reverse bias, stillhas a significant overhead (16.2% on average). p0, in spite ofits modest lifetime extension, appears to also be quite costlyLLR = 28.8% on average, due to large area overhead.

The two hybrid solutions justify the introduction of RBB asa strategy: OS+RBB and p0+RBB, although characterized bya reduced lifetime extension due to the use of RBB, can offerthe best tradeoff and can be safely applied to extend the life-time while maintaining under control the standby consumption.OS+RBB in particular has negligible overhead.

As a last observation, the RBB entry is not considered heresince it actually reduces lifetime, so its LLR would not bemeaningful.

VI. CONCLUSION

NBTI negatively affects the reliability of sub-100-nm cir-cuits. The pMOS sleep transistors used to implement power

gating are a clear example where this situation occurs withdramatic effects. For these devices, even a small change in

the threshold voltage results in a significant degradation of thevirtual-Vdd line, with direct consequences on the performanceof the power-gated circuit.

We have addressed this critical issue by presenting sev-eral design solutions for the implementation of NBTI-tolerantpower-gating architectures. The analysis of the aging-versus-leakage tradeoff, obtained through a SPICE-based explorationframework, shows that, while oversizing the sleep transistorgives the best results in terms of absolute lifetime extension(8.2 on average), a hybrid solution that combines OS withreverse BB yields the best balance between aging and leakage,namely, a 7.7 lifetime extension with negligible leakageoverhead.

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