07_dft_2pp

1 K.T. Tim Cheng 07_dft, v1.0 1

K.T. Tim Cheng 07_dft, v1.0 2

Testability Is concept that deals with costs associated with

testing. Increase testability of a circuit

Some test cost is being reduced Test application time Test generation time Fault simulation time Fault location time Test equipment cost


Goal: keep test cost within a reasonable bound and ensure product quality exceeds desired level

Definition - Design for Testability (DFT) refers to those design techniques that make test generation and testing cost-effective and ensure high-quality testing

Some DFT methods:1. Ad-hoc methods, design reviews, etc.2. Scan, full and partial3. Built-in self-test (BIST)4. Boundary scan

Design for Testability


Controllability: Measure the ease of controlling a line. Observability: Measure the ease of observing a line at

a PO

In general, DFT deals with ways for improving controllability and observability

Important Factors of Testability


Pins

Area/Yield

Performance

Design time

Theres no free lunch!!

Costs Associated with DFT


Ad Hoc Design For Testability

Design guidelines Avoid asynchronous logic Avoid clock gating

Insert test points

Disadvantages High fault coverage not guaranteed Design iterations required


Test Point Insertion Employ test points to enhance

Controllability Observability

CP: Control Points Primary inputs used to enhance controllability

OP: Observation Points Primary outputs used to enhance observability


Example

G6

G4

G5

G1

OP

G2

G3

W

XY

Z

CP


Modifications

X

X

X

X X

X

X

X X

X

0

0

0

1

1

1

Control Points

X

Observe X


Problems Large number of I/O pins

Add MUXs to reduce number of I/O pins

Serially shifts control point values

Long testing time


General Architecture Using Test Points Tied to Scan Registers

R1

X Z

R2

Control Observe

S

X' Z'


Partitioning Using Transparent Registers

B

E CA

D

B

E CA

D

R

R

RSout

R

Sin


Scan Design Objective: To provide controllability and observability

of internal state variables for testing

Method: Add test mode control signal(s) to circuit Connect flip-flops to form shift register(s) in test

mode Make inputs/outputs of the test shift registers

controllable/observable


The Scan Concept

CombinationalLogic

PrimaryInputs

PrimaryOutputs

FF

FF

ModeSwithch

Scan in

FFScan out


Tests for Full-Scan Circuits Test generation for combinational logic only Denote the test vectors and response data based

on PI, PO and state variablesti = tiI, tiF i = 1, 2, , nri = riO, riF

Test application1. Scan-in tiF by setting the circuit in test mode2. Apply tiI3. Observe riO4. Set the circuit in functional mode and capture the

response riF into scan register5. Scan-out riF while scanning -in ti+1F by setting the circuit

in test mode6. i i+1. Goto 2


Scan Flip-Flop (SFF)D

TC

SD

CK

Q

QMUX

D flip-flop

Master latch Slave latch

CK

TC Normal mode, D selected Scan mode, SD selected

Master open Slave opent

t

Logicoverhead


Level-Sensitive Scan-Design Flip-Flop (LSSD-SFF)

D

SD

MCK

Q

Q

D flip-flop

Master latch Slave latch

t

SCK

TCK

SCK

MCK

TCK Nor

mal

mod

e

MCK

TCK Sca

nm

ode

Logicoverhead


Scan Design Rules Use only clocked D-type of flip-flops for all state

variables. All flip-flop clocks must be controlled from primary

inputs Clocks must not feed data inputs of flip-flops All asynchronous preset or clear of flip-flops must

be disabled during scan The circuit cannot have bus contention during scan

shifting Memory arrays must support write-lock during scan

shifting.

10


Scan Rule Violation Example

DFlipFlop

Clock

D1 Q1 Q2D2D

FlipFlop

Rule Violation

DFlipFlop

Clock

D1 Q1Q2

D2

DFlipFlop

A Workaround


Bus Contention: Normal Mode

In normal system operation, it is assumed that there will not be bus contention.

This assumption cannot be justified in the scan-shift cycle for scan design and/or in the test sequence generated by ATPG.

Therefore add disabling logic unless ... RECOMMEND Fully

Decoded Enables!

d q

qnclkdff

d q

qnclkdff

data_1

data_2

11

K.T. Tim Cheng 07_dft, v1.0

Add Logic to Prevent Bus Contention in Scan Mode

d q

qnclkcsdff

scan_in

sclk

d q

qnclkcsdff

scan_in

sclk

scan_enable

data_1

data_2

Inactive

Active

Automatically add real disabling logic


Some Problems with Full Scan

Area overhead

Possible performance degradation

Long test application time

Not applicable to all designs (e.g. asynchronous designs, designs violating scan design rules)

High power dissipation during testing

12


Standard-Cell Design Layout

PolycellRows RoutingChannels


Layout of Scan Circuit

Scan-OutMODSW

ScanFlip-Flops

Scan-in

13


Area Overhead

Due to larger flip-flops Due to extra routing

Performance OverheadIncrease in delay of normal data paths includes Extra gate delay due to the multiplexer Extra capacitive loading delay due to scan wiring

at the flip-flop output


Issues for Multiple-Clock Design Clock skew might occur between different domains To minimize skew during scan shift, scan chains

should be ordered s.t. all FFs in same clock domain are grouped together minimizing locations where clock skew can occur

To completely avoid skew where the scan/clock domains cross, a lockup latch can be inserted.

A

SOSFF3

Q

QSET

CLR

DSFF2

Q

QSET

CLR

D

SFF1Q

QSET

CLR

D

Y

SI

SECLK1

B

CLK2

Q

QSET

CLR

D

L

LL1

Lockup latch

14


Issues for MC Design Contd To avoid clock skew during capture, pulse only one clock per pattern

Resulting in high pattern count (long test time)

Optimization: Perform clock domain analysis to identify independent clock domains and/or clocks that can be safely pulsed simultaneously

Scan Enable

TClk1

TClk3

Start load_unload

shift shift capture shift

TClk2

TClk4

shift capture

Pattern 1 Pattern 2

Start load_unload

Scan Enable

TClk1

TClk3

Start load_unload

shift shift capture shift

TClk2

TClk4

shift capture

Pattern 1 Pattern 2

Start load_unload

TClk1

TClk3

Start load_unload

Start load_unload shift

TClk2

TClk4

shift capture

TClk1

TClk3

shift capture

TClk2

TClk4

Pattern 1 Pattern 2shift


General Issues of Scan Design Scan chain ordering

To prevent skew during shift To minimize routing overhead Use placement info to determine a good ordering

Balancing scan chains To minimize total test time Total scan cycles = (Scan patterns +1)*(Length of longest

scan chains) # of scan chains is normally limited by the package (pins

available to borrow or dedicate for scan) as well as the tester (channels available with memory depth that can handle scan vectors).

15


Partial Scan Basic idea

Select a subset of flip-flops for scan lower overhead (area and speed) Relaxed design rules

Cycle-breaking technique Cheng & Agrawal, IEEE Trans. on Computers, 1990 Select scan flip-flops to simplify sequential ATPG

Timing-driven partial scan Jou & Cheng, ICCAD, Nov. 1991 Allow optimization of area, timing and testability

simultaneously


What Makes ATPG Difficult?

Poor controllability and observability of memory elements

Structure-dependenceC i r c u i t N o . o f

g a t e sN o . o f

f l i p - f l o p sS e q u e n t i a

l d e p t hT e s t g e n .C P U s e c .

F a u l tc o v e r a g e

T L C 3 3 5 2 1 1 4 1 2 4 7 8 9 . 0 1 %

C h i p - A 1 1 1 2 3 9 1 4 2 6 9 9 8 . 8 0 %

Gate count, memory element count, and sequential depth do not explain the results

Cycles in the circuit are mainly responsible for the test generation complexity

16


Directed Graph A Synchronous Sequential Circuit

2 3 4 5 6

1

A circuit with eight flip-flops

D3

1 2

4 5 6

L=2L=1

Graph of the ciruit

7 8

7 8

3 L=1L=1

2L=3


Test Length In A Sequential Ckt

D: Sequential depth (the distance along the longest path in its graph)

L: Maximum length of any cycle Test generation complexity of a cycle-free circuit

(pipeline structure) is similar to that of a comb. ckt In a circuit with depth D, any single-SA fault can

be tested by at most D+1 vectors The length of a test sequence ~ Dx2L

17


Partial Scan For Cycle-free Structure

Select minimal set of flip-flops to eliminate some or all cycles

Self-loops (cycles of unit length ) are not broken to the scan overhead low

The number of self-loops in real design can be quite large

Limit the length of consecutive self-loop paths

Long consecutive self-loop paths in large circuits may pose problems to sequential ATPG


Example: Directed Graph Of A Synchronous Sequential Ckt

2 3 4 5 6

1

A circuit with eight flip-flops

D3

1 2

4 5 6

L=2L=1

Graph of the ciruit

7 8

7 8

3 L=1L=1

2L=3

18


A Cycle-Breaking Algorithm Lee - Reddy algorithm (ICCAD90)Begin

graph reductionwhile (graph is not completely reduction)do begin

heuristic node selectiongraph reduction

endend


Graph Reduction 5 basic operations(a) Source operation

Ve1

e2

e3

Remove V, e1, e2 & e3

(b) Sink operation

Ve1e2e3

Remove V, e1, e2 & e3

19


(c) Self-loop operation

Ve1

e2

e3e4

Select V & remove V, e1, e2, e3 & e4

(d) Unit - in operation

VV

e1

e2

e5

e4

e3

Merge V into V Ve1

e2

e4

e3

e5


(e) Unit - out operation

VV

e1

e2e4

e3

Merge V into V Ve1

e2

e4

e3

Heuristic Node Selection Selects node with maximum ( in_degree *

out_degree) and removes it and its incident edges

20


}

}

scanpathsysclk

CombinationalLogic

CombinationalLogic

PrimaryInputs

PrimaryOutputs

Clocking Schemes for Partial Scan Circuits

Scheme 1: Use a separate scan clock (dff+csff)

scanclk


Clocking Schemes for Partial Scan Circuits

Scheme 2: Gate the system clock (dff+mdff)

non-scan cells

scanenable sysclk

gatedclock

scan path

CombinationalLogic

CombinationalLogic

}

}

Primaryoutputs

Primaryinputs

21


Partial Scan With a Separate Scan Clock or Gated Clock Purpose: Freeze the values in non-scan FFs during scan mode Disadvantage: Require multiple clock trees and cause extra clock-

signal routing efforts Advantage: ATPG is easier: scan FFs are fully controllable &

observable; can be treated as PI/PO for ATPG Test generation procedure: Scan FFs are removed and their input and output signals are

added to the PO/PI lists A sequential ATPG is used for test generation The vector sequences are then converted into scan sequences:

Each vector is preceded by a scan-in sequence to set the required values in scan FFs A scan-out sequence is added at the end of each vector sequence

to observe the values captured in scan FFs


Test Gen. Model - A Separate Scan Clock or Gated Clock

ScanIn

systemclock

II

I 12

n

PPI

PPI

1

m

PSPS

PS

1

2

k

systemclock

systemclock

OO1

2

nO

PPOmNSNS

NS

1

2

k

PPO1

Timeframe

1

Timeframe

2

Timeframe

N

22


Experimental Results - TLC (A Toy Ckt w/ 355 Gates, 21 FFs)

No. of Scan flip-flops

Max. cycle length

Depth Test Gen.

CPU sec.

Fault sim.

CPU sec.

Fault Coverage

No. of tests

Total vectors

0 4 14 1247 61 89.01% 805 805

4 2 10 157 11 95.90% 247 988

9 1 5 32 4 99.20% 136 1224

10 1 3 13 4 100.00% 112 1120

21 0 0 2 2 100.00% 52 1092


Test Length Statistics For TLC

Without Scan

200150100

500

0 50 100 150 200 250

No. ofFault

Test lenght

9 scan flip-flops

200150100

500

0 5 10 15 20

No. ofFault

Test lenght200150100

500

0 5 10 15 20

No. ofFault

Test lenght

10 scan flip-flops

23


Clocking Schemes for Partial Scan CktsScheme 3: Use the system clock as a scan clock but

without gating the clock*

non-scan cells

scanenablesysclk scan path

CombinationalLogic

CombinationalLogic

}

}

Primaryoutputs

Primaryinputs

Ref: Cheng, Single-Clock Partial Scan, IEEE Design and Test of Computers, June 1995.


Using System Clock for Scan Operation

The contents of the non-scan FFs may change during the scan operations

ATPG needs to deal with it - test generation process is more complicated

The fault coverage may be slightly lower than that of two-clock partial scan designs

The total test length (including scan sequences) is usually shorter than that of two-clock PS designs

24


Test Generation Model - Clocking Scheme 3

ScanIn

systemclock

II

I 12

n

PPI

PPI

1

m

PSPS

PS

1

2

k

systemclock

systemclock

OO1

2

nO

PPOmNSNS

NS

1

2

k

PPO1

Timeframe

1

Timeframe

2

Timeframe

N

Test Mode Functionalmode

Scan Shifting


Test Generation Model - Clocking Scheme 3

ScanIn

systemclock

II

I 12

n

SI

SI

1

m

PSPS

PS

1

2

k

systemclock

systemclock

OO1

2

nO

SOmNSNS

NS

1

2

k

SO1

Timeframe

1

Timeframe

2

Timeframe

N

Functional Mode

Functional Justification

25


Area Growth vs.ATPG Effort

full scannon-scan only selfloops remain

feedbackfree circuit

5%

10%

15%

20%

Real-estategrowth

CPU Time

ATPG complexity

real-estate growth

TestGenerationEffort


Timing-Driven Partial Scan

Aim at reducing both area overhead and performance degradation caused by test logic Timing analysis data can be used to guide scan flip-

flop selection Avoid selecting flip-flops on critical paths

Can be incorporated in existing logic synthesis system to satisfy or trade-off design constraints in terms of area, performance and testability

Testability

Area Performance

26


Summary-Seq. ATPG & Partial Scan

The combination of sequential ATPG and partial scan offers a cost-effective solution Cycle breaking is an effective heuristic for scan flip-

flop selection to simplify sequential ATPG Timing analysis data can be incorporated in the FF

selection process to minimize performance degradation There are choices in clocking schemes Commercial tools are available to support this

methodology


Primary Reasons For Using IEEE 1149.1 JTAG Boundary Scan

(1) To allow efficient testing of board interconnect(2) To facilitate isolation and testing of chips via the

test bus(3) To reuse the chip level tests at the board level

27


IEEE 1149.1 JTAG Boundary Scan All primary inputs/outputs latched and connected in a

shift register in test mode A test access port added with following signals:

TMS Test mode signal TCK Test clock TDI Test data input TDO Test data output

Test instructions & test data are sent to a chip over TDI

Test results & status information are sent from a chip over TDO

TAP controller is an FSM that decodes the state of the bus.


Boundary Scan Architecture

Iden

tity

Bypa

ss

Inst

ruct

ion

Con

trol

MUX

Scannable Register

To otherscannableregisters

SystemLogic

Boundary - Scan Path

TDITMSTCKTDO

Test

Acc

ess

Port

(TA

P)

28


Boundary Scan Cell

MUXS

QBQA

MUX0

1

SoutIN

SINShiftDR

ClockDR

UpdateDR

Modecontrol

Out

1. Normal mode: Mode-control = 02. Scan mode: Shift DR = 1

First scan FF is driven by TDI Last scan FF drives TDO

3. Capture mode: Shift DR = 04. Update mode: Mode-control = 1

0

1


Board & Chip Test Modes(1) External test mode

Chip 1 Chip 2

1 2

updateoperation

captureoperation

(2) Sample Test Mode: The I/O data associated with a chip can be sampled during normal system operation. The sampled data can be scanned out while the board remains in normal operation.

(3) Internal Test Mode Scan BIST

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