1 ERD 2009 ITRS Winter Conference – Hsinchu, Taiwan – 16 December, 2009 ITRS Public Conference Emerging Research Devices Jim Hutchby – SRC December 16,

1 ERD 2009 ITRS Winter Conference – Hsinchu, Taiwan – 16 December, 2009

ITRS Public ConferenceEmerging Research Devices

Jim Hutchby – SRCDecember 16, 2009

2009 ERD Chapter Emerging Memory Devices Emerging Logic Devices Emerging Architectures

2 ERD 2009 ITRS Winter Conference – Hsinchu, Taiwan – 16 December 2009

Hiroyugi Akinaga AIST Tetsuya Asai Hokkaido U. Yuji Awano Keio U. George Bourianoff Intel Michel Brillouet CEA/LETI Joe Brewer U. Florida John Carruthers PSU Ralph Cavin SRC An Chen GLFOUNDRIES U-In Chung Samsung Byung Jin Cho KAIST Sung Woong Chung Hynix Luigi Colombo TI Shamik Das Mitre Erik DeBenedictis SNL Simon Deleonibus LETI Kristin De Meyer IMEC Bob Fontana IBMPaul Franzon NCSU Akira Fujiwara NTT Christian Gamrat CEA Mike Garner Intel Dan Hammerstrom PSU Wilfried Haensch IBM Tsuyoshi Hasegawa NIMS Shigenori Hayashi Matsushita Dan Herr SRC Toshiro Hiramoto U. Tokyo Matsuo Hidaka ISTEK Jim Hutchby SRC Adrian Ionescu ETH Kohei Itoh Keio U. Kiyoshi Kawabata Renesas Tech Seiichiro Kawamura Selete Rick Kiehl U. C. Davis Suhwan Kim Seoul Nation U Hyoungjoon Kim Samsung Tsu-Jae King Liu U.C. Berkeley

Atsuhiro Kinoshita Toshiba Dae-Hong Ko Yonsei U. Hiroshi Kotaki Sharp Franz Kreupl Qimonda Nety Krishna AMAT Mark Kryder INSIC Zoran Krivokapic GLOBALFOUNDRIES Phil Kuekes HP Kee-Won Kwon Seong Kyun Kwan U. Jong-Ho Lee Kyungpook Nation U. Jong-Ho Lee Hanyang U. Lou Lome IDA Hiroshi Mizuta U. Southampton Kwok Ng SRC Fumiyuki Nihei NEC Ferdinand Peper NICT Yaw Obeng NIST Dave Roberts Nantero Barry Schechtman INSIC Kaushal Singh AMAT Sadas Shankar Intel Atsushi Shiota JSR Micro Satoshi Sugahara Tokyo Tech Shin-ichi Takagi U. Tokyo Ken Uchida Toshiba Yasuo Wada Toyo U. Rainer Waser RWTH A Franz Widdershoven NXP Jeff Welser NRI/IBM Philip Wong Stanford U. Kojiro Yagami Sony David Yeh SRC/TI In-Seok Yeo Samsung Hiroaki Yoda Toshiba In-K Yoo SAIT Yuegang Zhang LLLab Victor Zhirnov SRC

Emerging Research Devices Working Group


year

Beyond CMOS

Elements

Existing technologies

New technologies

Evolution of Extended CMOS

More Than Moore

ERD-WG in Japan


2009 ERD Chapter Emerging Memory Devices

Emerging Logic Devices

Emerging Architectures


Resistive Memories

Memory Technology Entries

Nanothermal–Thermochemical FUSE/Anti-FUSE− Nanowire PCM Nanoionic Memory (Electrochemical)− Cation migration− Anion migration

Electronic Effects Memory− Charge trapping− Mott Transition− FE barrier effects

Nanoelectromechanical Spin Transfer Torque MRAMMacromolecular (Polymer)Molecular Memory


Resistive Memories

Memory Technology Entries

Nanothermal–Thermochemical FUSE/Anti-FUSE− Nanowire PCM Nanoionic Memory (Electrochemical)− Cation migration− Anion migration

Electronic Effects Memory− Charge trapping− Metal-Insulator Transition− FE barrier effects

Nanoelectromechanical Spin Transfer Torque MRAMMacromolecular (Polymer)Molecular Memory

FeFET Memory

Capacitive Memory


One Diode – One Resistor (1D1R) Memory Cell

H-S. P. Wong – Stanford U.


Resistive Change Memory Cells

Electrochemical metallization or Atomic Switch

Phase Change Memory Cell Nanoionic Memory Cell

9 ERD 2009 ITRS Winter Conference – Hsinchu, Taiwan – 16 December 2009 9

Content changes for Emerging Research Memory Section

Recommend transfer of Engineered Tunnel Barrier Memory to PIDS and FEP

Add Nano Wire Phase-Change Memory

Add Spin Transfer Torque Magnetic RAM






New Logic Technology Tables

Table 1 – MOSFETsExtending the Channel

of MOSFETs to theEnd of the roadmap _____________

CNT FETsGraphene nanoribbons

III-V Channel MOSFETsGe Channel MOSFETs

Nanowire FETsNon conventional geometry devices

Table 2- UnconventionalFETS, Charge-based

Extended CMOS Devices

_______________

Tunnel FET I-MOS

Spin FET SET

NEMS switchNegative Cg MOSFET

Table 3 - Non-FET, Non Charge-based ‘Beyond

CMOS’ devices

_______________

Collective Magnetic DevicesMoving domain wall devices

Atomic SwitchMolecular Switch

Pseudo-spintronic DevicesNanomagnetic (M:QCA)

2009 Logic Transition tableTechnology Status Reason Comment

RTD out No viable logic functionality

Has been tracked for multiple revisions

Bi-layer tunneling devices

In Significant theoretical work in NRI

Band to band tunneling devices

In

NEMS In

RSFQ Possible future device


Carbon-based Nanoelectronics

Fullerenes (C60) Carbon Nanotubes

GraphiteGraphene

0D 1D 2D 3D

Atomic orbital sp2

P. Kim – Columbia U.


Graphene Electronics: Conventional & Non-conventional

Conventional Devices

Cheianov et al. Science (07)

Graphene Veselago lense

FETBand gap engineered Graphene nanoribbons

Nonconventional Devices

Trauzettel et al. Nature Phys. (07)

Graphene pseudospintronics

Son et al. Nature (07)

Graphene Spintronics

Graphene quantum dot

(Manchester group)

P. Kim – Columbia U.






Emerging Architectures Benchmarking Devices

Memory

Architecture for Inference (e.g. Morphic )


Four Architectural Projections

1) Hdwre Accelerators execute selected functions faster than software performing it on the CPU.

2) Alternative switches often exhibit emergent, idiosyncratic behavior. We should exploit them.

3) CMOS is not going away anytime soon.

4) New switches may improve high utilitization accelerators


Matching Logic Functions & New Switch Behaviors

Single Spin

Spin Domain

Tunnel-FETs

NEMS

MQCA

Molecular

Bio-inspired

CMOL

Excitonics

?

Popular Accelerators New Switch Ideas

Encrypt / Decrypt

Compr / Decompr

Reg. Expression Scan

Discrete COS Trnsfrm

Bit Serial Operations

H.264 Std Filtering

DSP, A/D, D/A

Viterbi Algorithms

Image, Graphics

Example: Cryptography Hardware AccelerationOperations required: Rotate, Byte Alignment, EXORs, Multiply, Table LookupCircuits used in Accel: Transmission Gates (“T-Gates”)New Switch Opportunity: A number of new switches (i.e. T-FETs) don’t have

thermionic barriers: won’t suffer from CMOS Pass-gate VT drop, Body Effect, or Source-Follower delay.

Potential Opportunity: Replace 4 T-Gate MOSFETs with 1 low power switch.


Emerging Architectures Benchmarking

Memory

Architecture for Inference (e.g. Morphic )


Improving Memory Power Efficiency

Critical Needs --

◦ Reduced power SRAM replacements 45 nm L1 Cache: 3.6 pJ/bit Note: re-architecting in 3D potentially can save ~50% What is the potential for an ERD to reduce to 0.3 pJ/bit?

◦ Reduced power switched interconnect Esp. packet routed interconnect (NOC) What is the potential for a memory-style ERD to be used for

fast switchable interconnect?


For both General Purpose and Application Specific Computing, the bottleneck is not in logic operations but in memory, communications, and reliability

3DIC creates new opportunity for algorithms and architectures that benefit from locality

ERD could benefit from a 1R1D cell– 1 Resistor 1 Diode (1R1D) potentially as useful as 1

Resistor 1 Transistor (1R1T)– Gives better scaling

Memory Architecture Preliminary Observations


Emerging Architectures Benchmarking

Memory

Architecture for Inference (e.g. Morphic)


04/10/2323

Architecture by InferenceIntelligent Computing

Large class of problems that computers still do not solve well

Lack of general solutions to these problems constitutes a significant barrier to computer usage and huge potential markets

Traditional Rule Based Knowledge systems are now evolving into probabilistic structures where inference becomes the key computation, generally based on Bayes’ rule

Maseeh College of Engineering and Computer ScienceHammerstrom04/10/23 24

Bayesian Networks

We now have Bayesian networks Bayesian nets express the structured, graphical

representations of probabilistic relationships between several random variables

And the fundamental computation has become probabilistic inference

A

C

B

D

P(a)

P(b|a)

P(c|a)P(d|b,c)

P(d|b,c) d1 d2

b1, c1 0.5 0.5

b2, c1 0.3 0.7

b1, c2 0.9 0.1

b2, c2 0.8 0.2


Process for Technology Transfer to PIDS/FEP made explicit Logic Devices

New Logic Table structure defined to identify three device categories(1 – Extend CMOS; 2 – Charge-based Non-CMOS; 3 – Non-charge-based Beyond-CMOS)

New potential solution table for “Carbon-based Nanoelectronics” Memory Devices

Transfer Engineered Tunnel Barrier Memory to PIDS/FEP A new taxonomy for categorizing resistive memories introduced. STT RAM and Nano-wire PCM scaled beyond 15nm STT RAM included in ERD to complement entry in PIDS/FEP An assessment of new memory devices is underway.

Architecture New Architectural work for benchmarking “Beyond CMOS” devices New Architecture section includes 1) memory architecture, 2) a new

inference compute proposal, and 3) a conceptual thermodynamic method for evaluating architecture.

ERD – Key Messages

Documents

1 ERD 2009 ITRS Winter Conference – Hsinchu, Taiwan – 16 December, 2009 ITRS Public Conference Emerging Research Devices Jim Hutchby – SRC December 16,