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Strip-by-strip Test Setup• Sensor in Light-tight Box
• Vacuum support jig is carrying the sensor– Mounted on freely movable table in
X, Y and Z
• Needles to contact sensor bias line – fixed relative to sensor
• Needles to contact:– DC pad (p+ implant)
– AC pad (Metal layer)
– Can contact ever single strip while table with sensor is moving
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Strip-by-Strip CharacterizationWhat do we test?• Global parameters:
– IV-Curve: Dark current, Breakthrough
– CV-Curve: Depletion voltage, Total Capacitance
• Strip Parameters e.g.– strip leakage current Istrip
– poly-silicon resistor Rpoly
– coupling capacitance Cac
– dielectric current Idiel
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Test structures Measurement Setup
• Instruments– Source Measurement Unit (SMU)
– Voltage Source
– LCR-Meter (Capacitance)
• Heart of the system: Crosspoint switching box, used to switch instruments to different needles
• Labview and GPIB used to control instruments and switching system
• Cold chuck will be provided by Karlsruhe
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CMS Test Structures
• TS-CAP:– Coupling capacitance CAC to
determine oxide thickness– IV-Curve: breakthrough voltage of
oxide
• Sheet:– Aluminium resistivity– p+-impant resistivity– Polysilicon resistivity
• GCD: – Gate Controlled Diode– IV-Curve to determine surface
current Isurface
– Characterize Si-SiO2 interface
• CAP-TS-AC: – Inter-strip capacitance Cint
• Baby-Sensor: – IV-Curve for dark current– Breakthrough
• CAP-TS-DC: – Inter-strip Resistance Rint
• Diode:– CV-Curve to determine depletion
voltage Vdepletion – Calculate resistivity of silicon bulk
• MOS: – CV-Curve to extract flatband voltage
Vflatband to characterize fixed oxide charges
– For thick interstrip oxide (MOS1)– For thin readout oxide (MOS2)
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Example of identified problems
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• Limit: Rint > 1GΩ to have a good separation of neighbouring strips
• Each dot in the left plot shows one measurement
• Value started to getting below limit
• We reported this to the company• Due to the long production
pipeline, a significant amount of ~1000 sensors were affected
Inter strip resistance issue during CMS sensor production
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Other Facilities
• Longterm Setup – Dark current characterization for
hours/days/weeks
• Wire bonding Machines– Semi-automatic Kulicke & Soffa (old)– Fully automatic Delvotec 6400
• 3D coordinate measurement machine– Mitutoyo Euro-C apex 776
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Sensor Design
• Electronic Design Automation Tool
• Mentor Graphics– ICstudio– ICstation– Physical design not drawn
but “programmed” using simple language called AMPLE
• Status: We can draw simple strip sensors
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Vienna Plans for SLHC
Main topic:
• Sensor Design
• Connectivity: – Sensor design for dual metal layer– test structures for dual metal layer readout– Have 1st test structures with dual metal layers
processed with fab (ITE Warsaw, ON Semi)
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Connectivity
• Occupancy reduction by segmentation of strips => Strixels
• Conventional pitch adapter and wire bonding not applicable anymore
• Readout chip has to be bump-bonded directly onto sensor– Cooling?
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Connectivity
• TODO:– Reliable design for
routing lines: short distances, low crosstalk
– calculation of additional capacitance caused by routing lines (causing noise in the readout)
– simulation of overhangs– Test structures with dual
metal layers to verify optimal geometry experimentally
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Bump-/Stud- bonding
• Readout chip must be connected upside down onto sensor (flip-chip bonding)
• Two methods:– Indium Bump-bonding needs
treatment of both chip and sensor with indium
• Advantage: fine pitch
– Stud-bonding doesn’t need special treatment
• 1st step: Design to enable both, wire or flip-chip bonding with same chips and sensors
• Open point: Cooling
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Summary– We cannot competitive with RD50, which works since years on new
rad-hard materials. We should concentrate on other issues.
– Intermediate Tracker will need strixels– Routing lines should be integrated into sensor– Flipchip-bonding of readout chip necessary, cheap stud-bonding preferred.– Effect on noise caused by increased strip length has to be investigated
• Capacitance of strip together with routing line unknown and complicated to calculate (Simulation?)
– Correlation of this project with Tracker-Trigger ambitions unclear (to me)
– We will not afford many wafer processing runs within this consortium (no external funding)
• Many things have to be tested cost-effective, e.g. test structures with dual metal layers by ITE Warsaw
• Extensive simulations before starting processing