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Preliminary design of the SSLB (“S” for SLHC). sLHC upgrade meeting. SLB – Functional Description. Overall synchronization of the ECAL and HCAL trigger primitives. Transmission of the Trigger Primitives to the Calorimeter Regional Trigger. SLB – Functional Description. - PowerPoint PPT Presentation
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José C. Da SilvaCMS Upgrade Workshop, FNAL, October 28, 2009
Preliminary design of the SSLB(“S” for SLHC)
sLHC upgrade meeting
José C. Da SilvaCMS Upgrade Workshop, FNAL, October 28, 2009
SLB – Functional Description
• Overall synchronization of the ECAL and HCAL trigger primitives.
• Transmission of the Trigger Primitives to the Calorimeter Regional Trigger.
José C. Da SilvaCMS Upgrade Workshop, FNAL, October 28, 2009
SLB – Functional Description
• Receives 9 bit data @ 40 MHz / TT
• Each SLB houses 8 TT
• Align Trigger Data using the LHC Orbit bunch structure to determine the BX position using internal histograms
• FIFO stage to compensate fiber length differences, deserialisers lock delays and to guarantee the alignment of data sent to the RT from both ECAL and HCAL.
• 2 TT data merging + Hamming code prior to send it over the high speed link
• 4 High speed links (1.2Gb/s each)
José C. Da SilvaCMS Upgrade Workshop, FNAL, October 28, 2009
SSLB details
• Maintain same connectivity and form factor
• Replace cables by optical links
• Latency budget increases in most cases when using FPGAs
• High speed link, 850/1310 nm, commercial package
• PCB for both ECAL/HCAL and RCT (duplex)
• FPGA Transceivers, deeper FIFO and Full Orbit histogram per
channel
• Stratix II or IV (GX) or Virtex 4 or 5 (6 arriving)
• SSLB (TX and RX)
José C. Da SilvaCMS Upgrade Workshop, FNAL, October 28, 2009
SSLB TPG side
90% JTAG Coverage
4 x 9 BITS BUS40.08 MHz
4 x 9 BITS BUS40.08 MHz
VITESSEctrl interface
TTC_rx CLK
Main Board Interface
HIGH SPEED
MERGER
PMC connectors
SYNC-S
SYNC
4 x 8 Bit BUS120.24 MHz Clock
RX_BCO
120.24 MHz Clock, 15 ps jitter
RX_CLK
PMC connectors
SYNC
mux
SYNC
SYNC
SLB-SController(Embedded )
EDC
EDC
SYNC-S
SYNC
SYNC
mux
SYNC
SYNC
mux
EDC
EDC
CLOCK Multiplier
mux
TTC BUS
Local_BUS
JTAG
4.8GB/sOptical Transceiver
José C. Da SilvaCMS Upgrade Workshop, FNAL, October 28, 2009
SSLB RCT side
90% JTAG Coverage
ctrl interface
ALIGN DATA
BLOCK
PMC connectors
PMC connectors
DE MUX
Controller(Embedded )
CLOCK Multiplier
4.8GB/sOptical Transceiver
RCT interface
José C. Da SilvaCMS Upgrade Workshop, FNAL, October 28, 2009
SSLB PCB Preview
José C. Da SilvaCMS Upgrade Workshop, FNAL, October 28, 2009
SSLB borders
RCTReceiver
Card
EE-TCC: EB-TCC:
EE EB borders
SLBAB
SLBCD
Hydra Cable2x(2x1.2Gb)
RCTReceiver
Card
EE-TCC: EB-TCC:
EE EB
SLBABCD
SLBABCD
Normal Cable4x1.2Gb
RCTReceiver
Card
José C. Da SilvaCMS Upgrade Workshop, FNAL, October 28, 2009
SSLB PCB Preview
José C. Da SilvaCMS Upgrade Workshop, FNAL, October 28, 2009
RCT
Calorimeter Trigger Evolution
RCT
GCT:Sources
GCT:Main GT/GMT
GCT/uTCA
ETCC:TPGs
HTR:TPGs
Cu
FO
RCT
GCT:Sources
GT/GMT
GCT/uTCA
uTCA-HTR:TPGs
SSLBRCT/
uTCA
GCT/uTCA
GT/GMT
ETCC:TPGs
uTCA-HTR:TPGs
SSLB
Step 1 (2009) Step 2(2010-2011)
RCT/uTCA
ETCC:TPGs
uTCA-HTR:TPGs
SSLB
Step 3 (>2011) Step 4 (>2012)
SSLBSSLB
GCT:Sources
GT/GMT
GCT/uTCA
SLBSLBSLB
SLB SLB
ETCC:TPGs
SLB
Matrix& AuxCards
José C. Da SilvaCMS Upgrade Workshop, FNAL, October 28, 2009
RCT
Calorimeter Trigger Evolution II
RCT
GCT:Sources
GCT:Main GT/GMT
GCT/uTCA
ETCC:TPGs
HTR:TPGs
Cu
FO
RCT
GCT:Sources
GT/GMT
GCT/uTCA
uTCA-HTR:TPGs
SSLBRCT/
uTCA
GCT/uTCA
GT/GMT
ETCC:TPGs
uTCA-HTR:TPGs
SSLB
Step 1 (2009) Step 2(2010-2011)
RCT/uTCA
ETCC:TPGs
SSLB
Step 3 (>2011) Step 4 (>2012)
SSLBSSLB
GCT:Sources
GT/GMT
GCT/uTCA
SLBSLBSLB
SLB SLB
ETCC:TPGs
SLB
Matrix& AuxCards
uTCA-HTR:TPGs
José C. Da SilvaCMS Upgrade Workshop, FNAL, October 28, 2009
Conclusions
• Use a single design for the new SLB , with Optical Transceivers
• Both connectors footprints
• Maintain modularity for compatibility with existing design
• LIP will take the responsibility of this design