1

Processor: Datapath and Control

Chapter 5

2

Components of a Computer

Processor

Control

Datapath

Memory

Devices

Input

Output

3

Code Stored in Memory

Processor

Control

Datapath

MemoryDevices

Input

Output

000000 00000 00101 0001000010000000000000 00100 00010 0001000000100000100011 00010 01111 0000000000000000100011 00010 10000 0000000000000100101011 00010 10000 0000000000000000101011 00010 01111 0000000000000100000000 11111 00000 0000000000001000

4

Processor Fetches an Instruction

Processor

Control

Datapath

MemoryDevices

Input

Output

000000 00000 00101 0001000010000000000000 00100 00010 0001000000100000100011 00010 01111 0000000000000000100011 00010 10000 0000000000000100101011 00010 10000 0000000000000000101011 00010 01111 0000000000000100000000 11111 00000 0000000000001000

Processor fetches an instruction from memory

5

Control Decodes the Instruction

Processor

Control

Datapath

Memory

Devices

Input

Output

000000 00100 00010 0001000000100000

Control decodes the instruction to determine what to execute

6

Datapath Executes the Instruction

Processor

Control

Datapath

Memory

Devices

Input

Outputcontents Reg #4 ADD contents Reg #2results put in Reg #2

Datapath executes the instruction as directed by control

000000 00100 00010 0001000000100000

7

What Happens Next?

Processor

Control

Datapath

MemoryDevices

Input

Output

000000 00000 00101 0001000010000000000000 00100 00010 0001000000100000100011 00010 01111 0000000000000000100011 00010 10000 0000000000000100101011 00010 10000 0000000000000000101011 00010 01111 0000000000000100000000 11111 00000 0000000000001000

Fetch

DecodeExec

8

Output Data Stored in Memory

Processor

Control

Datapath

MemoryDevices

Input

Output000001000101000000000000000000000000000001001111000000000000010000000011111000000000000000001000

At program completion the data to be output resides in memory

9

Processor

• Two main components– Datapath– Control

10

Design of Processor

1. Analyze the instruction set architecture

2. Select the datapath elements each instruction needs

3. Assemble the datapath

4. determine the controls required

5. Assemble the control logic

11

A Basic MIPS Implementation

• will implement the following subset of MIPS core instructions– lw, sw– add, sub, and, or, slt– beq, j

12

Steps in executing add instruction

add $t0, $t1, $t2

• Send PC to memory that contains the code and fetch instruction

• PC = PC+4• Read $t1 and $t2 from register file• Perform $t1 + $t2• Store result in $t0

13

Steps in executing lw instruction

lw $t0, offset($t1)

• Send PC to memory that contains the code and fetch instruction

• PC = PC+4• Read $t1 from register file• Perform $t1 + sign-extend(offset)• Read value at Mem[$t1 + sign-extend(offset)]• Store result in $t0

14

Steps in executing beq instruction

beq $t0, $t1, Label

• Send PC to memory that contains the code and fetch instruction

• PC = PC+4• Read $t0 and $t1 from register file• Perform $t0 - $t1 • If result = 0, set PC=Label

15

Steps in implementing these instructions

• Common steps– Send PC to memory that contains the code and fetch the

instruction– Set PC = PC+4– Read one or two registers

• Steps dependent on instruction class– Use ALU

• Arithmetic/logical instr for operation execution • lw/sw for address calculation• beq for comparison

– Update memory or registers• lw/sw read or write to memory• Arithmetic/logical instr write to register• beq updates PC

16

Components needed for Fetching and Incrementing PC

PC

Instructionaddress

Instruction

Instructionmemory

Add Sum

a. Instruction memory b. Program counter c. Adder

17

Datapath for Fetching and Incrementing PC

18

Components needed for R-format Instructions

Readregister 1

Readregister 2

Writeregister

WriteData

Registers ALUData

Data

Zero

ALUresult

RegWrite

a. Registers b. ALU

5

5

5

Registernumbers

Readdata 1

Readdata 2

ALU operation4

add $t0, $t1, $t2: $t0= $t1 + $t2

and $t0, $t1, $t2: $t0= $t1 AND $t2

19

Register File

• Consists of a set of 32 registers that can be read and written– Registers built from D flip-flops

• has two read ports and one write port

• Register number are 5 bit long• To write, you need three

inputs:– a register number, the data to

write, and a clock (not shown explicitly) that controls the writing into the register

– The register content will change on rising clock edge

5

5

5

20

Portion of datapath for R-format instruction

4

31-26 25-21 20-16 15-11 10-6 5-0

opcode rs rt rd shamt funct

R-format

rs

rt

rd

21

Components needed for load and store instructions

lw $t0, offset($t1): $t0=Mem[$t1 + se(offset)]

sw $t0, offset($t1): Mem[$t1 + se(offset)]=$t0

22

Memory Unit

• MemRead to be asserted to read

• MemWrite to be asserted to write

• Both MemRead and MemWrite not to be asserted in same clock cycle

• Memory is edge triggered for writes

MemRead

MemWrite

Address

Write Data

ReadData

23

Load/Store instruction datapath

4

lw $t0, offset($t1): $t0=Mem[$t1 + se(offset)]

sw $t0, offset($t1): Mem[$t1 + se(offset)]=$t0

31-26 25-21 20-16 15-0

opcode rs rt offset I-format

24

Load instruction datapath

4

lw $t0, offset($t1): $t0=Mem[$t1 + se(offset)]

31-26 25-21 20-16 15-0

opcode rs rt offset I-format

rs

rt

offset

25

Store instruction datapath

4

sw $t0, offset($t1): Mem[$t1 + se(offset)]=$t0

31-26 25-21 20-16 15-0

opcode rs rt offset I-format

rs

rt

offset

26

Branch Instruction Datapath

31-26 25-21 20-16 15-0

opcode rs rt C

If ($rs-$rt)=0, PC=PC+4+(C.4)

rs

rt

C

27

Creating a single Datapath

Simplest Design: Single Cycle Implementation

• Any instruction takes one clock cycle to execute– This means no datapath elements can be used more

than once per instruction

– But datapath elements can be shared by different instruction flows

28

4

4

29

Composite Datapath for R-format and load/store instructions

30

Composite Datapath for R-format and load/store instructions

P

C

Instruction Memory

4+

31

Composite datapath for R-format, load/store, and branch instructions

32

Datapath for for R-format, load/store, and branch instructions

4

ALU Operation

33

Instruction RegDst RegWrite ALUSrc MemRead MemWrite MemToReg PCSrc ALU operation

R-format 1 1 0 0 0 0 0 0000(and)

0001(or)

0010(add)

0110(sub)

lw 0 1 1 1 0 1 0 0010 (add)

sw X 0 1 0 1 X 0 0010 (add)

beq x 0 0 0 0 X 1 or 0 0110 (sub)

34

Control

• We next add the control unit that generates – write signal for each state element– control signals for each multiplexer– ALU control signal

• Input to control unit: instruction opcode and function code

35

Control Unit

• Divided into two parts– Main Control Unit

• Input: 6-bit opcode• Output: all control signals for Muxes, RegWrite,

MemRead, MemWrite and a 2-bit ALUOp signal

– ALU Control Unit• Input: 2-bit ALUOp signal generated from Main

Control Unit and 6-bit instruction function code• Output: 4-bit ALU control signal

36

37

Truth Table for Main Control Unit

38

Main Control Unit

39

ALU Control Unit• Must describe hardware to compute 4-bit ALU control

input given– 2-bit ALUOp signal from Main Control Unit – function code for arithmetic

• Describe it using a truth table (can turn into gates):

40

ALU Control bits

0010

0010

0110

0010

0110

0000

0001

0111

41

ALU Control Unit