Su L17 Processor Datapath

8/8/2019 Su L17 Processor Datapath

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CDA 3101 Summer 2007

Introduction to Computer Organization

Processor Organization

Datapath Design

21 June 2007


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Review

Construction of the ALU Building blocks (digital design gates)

Modular design

Multiplexor chooses operation

All operations are performed in parallel Carry lookahead adder

Computer arithmetic

Finite precision

Laws of algebra do not always hold

Integers: twos complement representation

Floating point: IEEE 754 standard


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Overview

Computer organization (microarchitecture)

Processor organization

Datapath

Control

Register file

Processor implementation overview

Clocking methodologies

Sequential circuits Latches

Registers


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Processor Performance

Program

Compiler

ISA

Microarchitecture

Hardware

CPU time = IC* CPI * Cycle time


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Computer Organization

I/O

device

I/O

device

I/O Subsystem

ProcessorMemory

Subsystem

. . .

Address Bus

Data Bus

Control Bus


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The Processor

Processor(CPU) Active part of the computer

Does all the work Data manipulation

Decision-making

Datapath Hardware that perform all required operations

ALU + registers + internal buses

The brawn

Control Hardware which tells the datapath what needs to be done

The brain


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Processor Organization

ALU

Control

Unit

Registers

Control signals

Data values

Control signals

Control bus signals

Data values (results)

Data values (operands)

Address bus Data bus


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Implementation of MIPS

ISA determines many aspects of implementation

Implementation strategies affect clock rate and CPI

MIPS subset to illustrate implementation

Memory-reference instructions

Load word (lw) Save word (sw)

Integer arithmetic and logical instructions

add, sub, and, or, and slt

Branch instructions

Branch if equal (beq)

Jump (j)


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Implementation Overview

PC

Instructionmemory

+4

rt

rs

rd

Registers ALUData

memory

imm

Data

Data

Address

Controller

Opcode, funct

Address

Instruction

Datapath is based on register transfers required to execute instructions

Control causes the right transfers to happen


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Logic and Clocking

Combinational elementsOutputs depend only on current inputs

Example: ALU (adders, multiplexers, shifters)

Sequential elementsContain state

Output depend on input and state

Inputs: data values and clock

Memory, registers

Asserted signal: logically high


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Clocking Methodology

Determines the order of (gate) eventsDefines when signals can be read/written

Clock: circuit that emits a series of pulses

clock

Timing diagrams

C Asymmetric clock

clock cycle

time

(C1 AND C2)

Rising edge Falling edge


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Edge-Triggered Clocking

State

element

1

State

element

2

Combinational

logic

State

element

Combinational

logic

Either the rising edge or the falling edge is active State changes only on the active clock edge

clock


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NOR SR Latch

State 0 State 1

InputsS - set

R - resetOutputs: Q and Q


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Clocked SR Latch


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Clocked D Latch

DC

Q

Output is initially deasserted


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D flip-flop

D

C

Q

C

D QD

latchC

D QD

latch

C

D Q

QQ

Setup time

hold time

Falling-edge trigger, output is initially deasserted


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Register File

Read ports

Write port


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Register File Read Ports


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Register File Write Ports


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Conclusions

Datapath performs work of computation

Building blocks for datapath

ALU: Performs work of computation

Register File: Data I/O from registers

Register file implemented with D flipflops,

multiplexers, and decoder

Clocked (synchronous) logic circuits

Write-enabled data transferinto registers

No need to protect data transfer from registers


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Anticipate the Mid-SemesterBreak!!


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New Topic Datapath Design

Datapath implements fetch-decode-execute

Design Methodology

Determine instruction classes and formats

Build datapath sections for each instr.fmt.

Compose sections to yield MIPS datapath

Challenge #1: What are instruction classes? Challenge #2: What components are useful?


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Simple Datapath Components

Memory stores the instruction PC address of current instruction ALU executes current instruction

PC Read Addr

Instruction

InstructionMemory

4

+

fetch

Increment program counter


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R-format Datapath

Format: opcode r1, r2, r3

Result

Zero

ALU

Read

Data 1

Read

Data 2

Read Reg 1

Read Reg 2

Write

Register

Write Data

Register

Write

ALU op

RegisterFile

3

Instruction


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Load/Store Datapath Issues

lw $t1, offset($t2)

Memory at base $t2 with offset

lw: Read memory, write into register $t1

sw: Read from register $t, write to memory

Address computation ISA says:

Sign-extend 16-bit offset to 32-bit signed value

Hardware: Data memory for read/write


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Load/Store Datapath Components

Address

Read data

Write data

MemWrite

MemRead

DataMemor

y

SignExtend

16 32

1101 0011 1111 1111 1111 1111

1101 0011


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Load/Store Datapath Actions

1. Register Access Register File

--Instruction/Data/Address Fetch

1. Memory Address Calculation ALU-- Address Decode

1. Read/Write from Memory DataMemory

2. Write into Register File Register File

-- Load/Store InstructionExecute


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Load/Store Datapath

Fetch Decode Execute


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Branch Datapath Issues

beq $t1, $t2, offset

Two registers ($t1, $t2) compared for equality

16-bit offset to compute branch target address

Branch target address ISA says:Add sign-extended offset to PCBase address is instruction after branch (PC+4)

Shift offset left 2 bits => word offset

Jump to targetReplace lower 26 bits of PC with lower 26 bits

of instruction shifted left 2 bits


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Branch Datapath Actions

1. Register Access Register File

--Instruction/Data Fetch

1. Evaluate Branch Condition ALU #12. Calculate Branch Target ALU #2

--Branch Computation similar to

Decode

1. Jump to Branch Target Control Logic

-- Branch Instruction Execute


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Delayed Branch (MIPS)

MIPS ISA: Branches always delayed

- Instr.Ib

following branch is always executed

- condition = false => Normal branch

- condition = true =>Ib executed

Why bother?

1. Improves efficiency ofpipelining

2. Branch not taken (false condition) can be

common case


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Conclusions

MIPS ISA: Three instruction formats (R,I,J)

Datapath designed for each instruction format

Datapath Components:

--R-format:ALU, Register File

--I-format: Sign Extender, Data Memory

--J-format:ALU #2 for target address compn.

Trick: Delayed branch to make pipeline efficient

H f B k W k!

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Su L17 Processor Datapath