Chapter 5 – The Processor, Datapath and Control

7/27/2019 Chapter 5 The Processor, Datapath and Control

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Chapter 5 The Processor:

Datapath and

Control


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Implementation of Instruction sets

An instruction set architecture is an interface that definesthe hardware operations which are available to software.

Any instruction set can be implemented in many different

ways. Over the next few weeks well see several possibilities.

In a basic single-cycle implementation all operations

take the same amount of timea single cycle.

In a multicycle implementation all instructions is

executed in multiple clock cycles.

Finally, pipelining lets a processor overlap the execution

of several instructions, potentially leading to bigperformance gains.


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BUILDING A DATAPATH

Datapath element - A funtional unit which is

used to operate on or hold data within a

pracessor.

1 . Program counter [ PC ] - The register

which holds the address of current instruction.

PC


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Instruction Memory

Memory unit to storeinstructions of a program andsupply instructions given anaddress.


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Instruction Fetching

The CPU is always in an infiniteloop, fetching instructions from

memory and executing them.

The program counter or PC

register holds the address of the

current instruction.

MIPS instructions are each

four bytes long, so the PC

should be incremented by four

to read the next instruction in

sequence.


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Register File

Our register file stores thirty-two 32-bit values. Each register specifier is 5 bits long. You can read from two registers at atime. RegWrite is 1 if a register should bewritten.

Heres a simple ALU with fiveoperations, selected by ALU controlsignal which is 4 bits wide.


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Executing an R-type instruction

1. Read an instruction from the

instruction memory.2. The source registers, specified byinstruction fields rs and rt, should beread from the register file.3. The ALU performs the desired

operation.4. Its result is stored in the destinationregister, which is specified by fieldrd of the instruction word.


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R Type


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Executing an I- Type Instructions

1. Read an instruction from theinstruction memory.

2. For an instruction like lw $t0, 4($s2),the base register $s2 is added withthe sign-extended constant [ 4 ] to geta data memory address.

5.Data is read from data memory by

supplying an address.4. Its result is stored in the destination

register, which is specified by fieldrt of the instruction word.


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rs

rt


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Need of Multiplexors

The arithmetic and logical instructions use the ALU

with inputs coming from two registers.The

memory instructions use ALU to do address

calculation. 1 input register , 2nd

input signextend.

The value stored into destination register comes

from ALU(R Type instructions) or memory (load).


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Steps in executing branches

1. Fetch the instruction, like beq $s1, $s2,offset from memory.2. Read the source registers, $s1 and $s2,from the register file.

3. Compare the values by subtracting themin the ALU.4. If the subtraction result is 0, the sourceoperands were equal and the PCshould be loaded with the target address,

PC + 4 + (offset x 4).5. Otherwise the branch should not betaken, and the PC should just beincremented to PC + 4 to fetch the nextinstruction sequentially.


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Need for additional multiplexors

An additional multiplexor is required to select either

the sequentially following instruction address (PC+4)

or branch target address to be written into the PC.

The destination register is in one of the 2 places.For aload, it is in bit positions 20:16(rt), while for an R

Type instruction, it is in bit positions 15:11(rd).Thus

we will need to add a multiplexor to select which

field of instruction is used to indicate the registernumber to be written .


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Branching Hardware


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R-Type Instruction Path


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Lw instruction datapath


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Sw instruction Datapath


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beq instruction datapath


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J - Format

31 26 25 o

For j instructionTarget address = PC[31-28] (offset

address


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Datapath with control unit


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ALU control lines Function

0000 AND

0001

0010

0110

0111

1100

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Chapter 5 – The Processor, Datapath and Control