100+ GHz Transistor Electronics: Present and Projected Capabilities

rodwell@ece.ucsb.edu 805-893-3244, 805-893-5705 fax

2010 IEEE International Topical Meeting on Microwave Photonics, October 5-6, 2010, Montreal

Mark Rodwell University of California, Santa Barbara

THz Transistors

Why Build THz Transistors ?

THz amplifiers→ THz radios→ imaging, sensing, communications

precision analog design at microwave frequencies→ high-performance receivers

500 GHz digital logic→ fiber optics

Higher-Resolution Microwave ADCs, DACs, DDSs

Transistor figures of Merit / Cutoff Frequencies

H21=short-circuit current gain

gain

s, d

B

MAG = maximum available power gain:impedance-matched

U= unilateral power gain:feedback nulled, impedance-matched

fmaxpower-gaincutoff frequency

fcurrent-gaincutoff frequency

What Determines Digital Gate Delay ?

CV/I terms dominate

)./5.05.0(

)/5.05.05.0(

)/5.05.0)(/(

)66)(/(

LCfcbijebb

LCfcbicbxex

LCfcbicbxjeC

wirecbicbxjeCLfgate

VICCR

VICCR

VICCCqIkT

CCCCIVT

analog ICs have somewhat similar bandwidth considerations...

→

How to Make THz Transistors

High-Speed Transistor Design

AR contact /

Bulk and Contact Resistances

Depletion Layers

TAC

vT2

2max )(4

TVv

AI applsat

Thermal Resistance

Fringing Capacitances

~/ LC finging~/ LC finging

LKWL

LKR

ththth

1ln1

dominate rmscontact te

Frequency Limitsand Scaling Laws of (most) Electron Devices

widthlengthlog

lengthpower

thicknessarea /

lengthwidth

4area

area/thickness/area

thickness

2limit-charge-space max,

T

I

R

RC

sheetcontactbottom

contacttop

To double bandwidth, reduce thicknesses 2:1 Improve contacts 4:1reduce width 4:1, keep constant lengthincrease current density 4:1

topR

bottomR

PIN photodiode

FET parameter changegate length decrease 2:1

current density (mA/m), gm (mS/m) increase 2:1

channel 2DEG electron density increase 2:1gate-channel capacitance density increase 2:1 dielectric equivalent thickness decrease 2:1 channel thickness decrease 2:1 channel density of states increase 2:1source & drain contact resistivities decrease 4:1

Changes required to double transistor bandwidth

GW widthgate

GL

HBT parameter changeemitter & collector junction widths decrease 4:1current density (mA/m2) increase 4:1current density (mA/m) constantcollector depletion thickness decrease 2:1base thickness decrease 1.4:1emitter & base contact resistivities decrease 4:1

eW

ELlength emitter

constant voltage, constant velocity scaling

nearly constant junction temperature → linewidths vary as (1 / bandwidth)2

fringing capacitance does not scale → linewidths scale as (1 / bandwidth )

Electron Plasma Resonance: Not a Dominant Limit

*2kinetic1nmqA

TL TAC

ntdisplaceme

m

scattering LRf

21

21

frequency scattering

kinetic

bulk

mnmqATR

*2bulk1

21

2/1frequency relaxation dielectric

bulkntdisplaceme

RC

fdielectricntdisplacemekinetic

2/1frequencyplasma

CLf plasma

THz 800 THz 7 THz 74319 cm/105.3

InGaAs-

n

319 cm/107

InGaAs-

pTHz 80 THz 12 THz 13

0

20

40

60

80

100

120

140

100 200 300 400 500 600 700

junc

tion

tem

pera

ture

rise

, Kel

vin

master-slave D-Flip-Flop clock frequency, GHz

substrate: cylindrical+spherical regions

substrate: planar region

package

total

Thermal Resistance Scaling : Transistor, Substrate, Package

2substrate

2/11lnDDT

KP

DLKP

WL

LKPT sub

InPEInPe

e

EInP

junctionnear flowheat lcylindrica

eLr for flow spherical

2/for flowplanar

HBTDr

callylogarithmi increases

variationantinsignific

constant is iflly quadratica increases

subT

.)(bandwidth

as scalesdensity,Power

h.1/bandwidt as scalelenghts Wiring

2

chipCu

chippackage WK

PT

1

41

)/GHz 150( m 40 clocksub fT

IC CML HBT-2000

0

20

40

60

80

100

120

140

100 200 300 400 500 600 700

junc

tion

tem

pera

ture

rise

, Kel

vin

master-slave D-Flip-Flop clock frequency, GHz

substrate: cylindrical+spherical regions

substrate: planar region

package

total

Thermal Resistance Scaling : Transistor, Substrate, Package

2substrate

2/11lnDDT

KP

DLKP

WL

LKPT sub

InPEInPe

e

EInP

junctionnear flowheat lcylindrica

eLr for flow spherical

2/for flowplanar

HBTDr

callylogarithmi increases

variationantinsignific

constant is iflly quadratica increases

subT

.)(bandwidth

as scalesdensity,Power

h.1/bandwidt as scalelenghts Wiring

2

chipCu

chippackage WK

PT

1

41

)/GHz 150( m 40 clocksub fT

IC CML HBT-2000Probable best solution: Thermal Vias ~500 nm below InP subcollector...over full active IC area.

BipolarTransistors

256 nm InP HBT

0

10

20

30

109 1010 1011 1012

109

1010

1011

1012

dB

Hz

f = 560 GHz

fmax

= 560 GHz

U

H21

0

10

20

30

40

109 1010 1011 1012

dB

Hz

UH21

f = 424 GHz

fmax

= 780 GHz

0

5

10

15

20

0 1 2 3 4V

ce

mA

/m

2

150 nm thick collector

70 nm thick collector340 GHz VCO

340 GHz dynamic frequency divider

Vout

VEE VBB

Vtune

Vout

VEE VBB

Vtune

324 GHz amplifier

Z. Griffith

J. Hacker, TSCIMS 2010

Z. Griffith

E. Lind

M. Seo, UCSB/TSCIMS 2010

M. Seo, UCSB/TSC

204 GHz staticfrequency dividerZ. Griffith, TSCCSIC 2010:to be presented

0

10

20

30

40

109 1010 1011 1012

dB

Hz

U

H21

ft = 660 GHz

fmax

= 218 GHz

0

10

20

30

0 1 2 3

mA/

m2

Vce much better results in press ...

InP Bipolar Transistor Scaling Roadmap

emitter 512 256 128 64 32 nm width16 8 4 2 1 m2 access

base 300 175 120 60 30 nm contact width, 20 10 5 2.5 1.25 m2 contact

collector 150 106 75 53 37.5 nm thick, 4.5 9 18 36 72 mA/m2 current density4.9 4 3.3 2.75 2-2.5 V, breakdown

f 370 520 730 1000 1400 GHzfmax 490 850 1300 2000 2800 GHz

power amplifiers 245 430 660 1000 1400 GHz digital 2:1 divider 150 240 330 480 660 GHz

eW

bcWcTbT

Fabrication Process for 128 nm & 64 nm InP HBTs

Initial Results: Refractory-Contact HBT Process

Chart 17

0

5

10

15

20

25

30

109 1010 1011 1012

Gai

n (d

B)

freq (Hz)

ft = 430 GHz

fmax

= 800 GHz

U

H21

Aje

= 0.27m x 3.5m

0

5

10

15

20

25

30

109 1010 1011 1012

Gai

n (d

B)

Freq (Hz)

ft = 370 GHz

fmax

= 700 GHz

U

H21

Aje = 0.11 m x 3.5 m

Need to add E-beam defined base, best base contact technology

110 nm emitter width 270 nm emitter width

InP DHBTs: August 2010

)( ),/( ),/( ),/(

hence , :digital

gain, associated ,F :amplifiers noise low

mW/ gain, associated PAE,

:amplifierspower

)11(

2/) (alone or

min

1max

max

max

max

cb

cbb

cex

ccb

clock

ττVIRVIRIVC

f

m

ff

ff

ffff

:metrics better much

:metrics popular

0

200

400

600

800

1000

0 200 400 600 800 1000

Teledyne DHBT

UIUC DHBT

NTT DBHT

ETHZ DHBT

UIUC SHBT

UCSB DHBT

NGST DHBT

HRL DHBT

IBM SiGe

Vitesse DHBT

f max

(GH

z)

ft (GHz)

600 GHz

500GHz maxff

Updated Aug 2010

800 GHz

900 GHz

700 GHz

400GHz

250 nm

600nm

350 nm

250 nm

200 nm

110 nm

670 GHz Transceiver Simulations in 128 nm InP HBT

transmitter exciter

receiver

128nm 64nm 32nm

(a) (b) (c)

-8 -6 -4 -2 0 2 4 6 8-10 10

-5

0

5

10

15

-10

20

Pin

PoutGain

-14-12-10-8 -6 -4 -2 0 2 4-16 6

-5

0

5

10

15

-10

20

Pin

Pout

-10 -8 -6 -4 -2 0 2 4 6-12 8

-5

0

5

10

15

-10

20

Pin

PoutGain

LNA: 9.5 dB Fmin at 670 GHz

640 660 680 700620 720

10

20

0

30

SP.freq, GHz

dB(S

(2,1)

)

freq, GHz

nf(2)

820 840 860 880800 900

10

20

30

0

35

SP.freq, GHz

dB(S

(2,1

))

freq, GHz

nf(2)

128nm 64nm 32nm

(a) (b) (c)

3-layer thin-film THz interconnects thick-substrate--> high-Q TMIC thin -> high-density digital

Simulations @ 670 GHz (128 nm HBT)

PA: 9.1 dBm Pout at 670 GHz

VCO:-50 dBc (1 Hz) @ 100 Hz offsetat 620 GHz (phase 1)

-150

-100

-50

0

50

101 102 103 104 105 106 107

PLL

sin

gle-

side

band

ph

ase

nois

e sp

ectr

al d

ensi

ty, d

Bc

(1 H

z)

offset from carrier, Hz

free-running VCO

closed-loop VCO noise

multiplied reference noise

Total PLLphase noise

-1.2

-1.15

-1.1

-1.05

-1

-0.95

-0.9

195 10-12 197.5 10-12 200 10-12

690 GHz Input

Vou

t , V

out_

bar

time, seconds

-1.2

-1.15

-1.1

-1.05

-1

-0.95

-0.9

195 10-12 197.5 10-12 200 10-12

950 GHz Input

Vou

t, V

out_

bar

time, seconds

Dynamic divider:novel design,simulates to 950 GHz

-10.00 -5.000 0.0000 5.000 -15.00 10.00

05

10152025

-5

30

LO Power

Noise

Figu

re, C

onve

rsion

Gain

(dB)Mixer:

10.4 dB noise figure11.9 dB gain

THz Field-Effect Transistors

(THz HEMTs)

laws in constant-voltage limit:

FET Scaling Laws

GW widthgate

GL

FET parameter changegate length decrease 2:1current density (mA/m), gm (mS/m) increase 2:1channel 2DEG electron density increase 2:1electron mass in transport direction constantgate-channel capacitance density increase 2:1 dielectric equivalent thickness decrease 2:1 channel thickness decrease 2:1 channel density of states increase 2:1source & drain contact resistivities decrease 4:1

Changes required to double device / circuit bandwidth.

HEMT/MOSFET Scaling: Four Major Challenges

gate dielectric:need thinner barriers→ tunneling leakage

contact regions:need reduced access resistivity

channel:need higher charge densityyet keep high carrier velocity

channel:need thinner layers

THz FET Scaling Roadmap

Gate length nm 35 25 18 13 9 Gate barrier EOT nm 0.83 0.58 0.41 0.29 0.21 well thickness nm 5.7 4.0 2.8 2.0 1.4 S/D resistance m 150 100 74 53 37 effective mass *m0 0.05 0.05 0.08 0.08 0.08

# band minima 1 1 2 3 3f GHz 700 770 1100 1600 2300fmax GHz 810 930 1400 2000 2900fdivider GHz 150 220 300 430 580Id /Wg mA/m 0.54 0.69 0.95 1.4 1.8

@ 200 mV overdrive

high-K gate dielectrics source / drain regrowth -L transport

source-coupled logic

?

III-V MOSFETs with Source/Drain Regrowth

27 nm InGaAs MOSFET

RegardingMixed-Signal ICs

&Waveform Generation

Clock Timing Jitter in ADCs and DACs

Timing jitter is quantitatively specifiedby the single-sideband phase noise spectral density L(f).

IC oscillator phase noise varies as ~1/f2 or ~1/f3 near carrier

Impact on ADCs and DACs: imposition of 1/fn sidebands on signal of relative amplitude L(f) ...not creation of a broadband noise floor.

Dynamic range of electronic DACs & ADCs is limited by factors other than the phase noise of the sampling clock

Why ADC Resolution Decreases With Sample Rate

dynamic hysteresis

Dynamic Range Determined by Circuit Settling Time vs. Clock Period

1bits#

latchsamplef

metastability

IC time constants→ Resolution decreases at high sample rates

Fast IC Waveform Generation: General Prospects

Waveform generator → fast digital memory & DAC

Parallel digital memory and 200 Gb/s MUX is feasiblecost limits: power & system complexity vs. # bits, GS/s

Performance limit: speed vs. resolution of DACfaster technologies → increased sample rates

Feasible ADC resolution: 12 SNR bits @ 4 GS/s feasible using 500 nm (400GHz) InP HBT. Feasible sample rate will scale with technology speed..

THz Transistors&

Mixed-Signal ICs

Few-THz Transistors

Scaling limits: contact resistivities, device and IC thermal resistances.Few-THz InP Bipolar Transistors: can it be done ?

62 nm (1 THz f, 1.5 THz fmax ) scaling generation is feasible.700 GHz amplifiers, 450 GHz digital logic

Is the 32 nm (1 THz amplifiers) generation feasible ?

Few-THz InP Field-Effect Transistors: can it be done?

challenges are gate barrier, vertical scaling,source/drain access resistance, channel density of states.

2DEG carrier concentrations must increase.

S/D regrowth offers a path to lower access resistance.

Solutions needed for gate barrier: possibly high-k (MOSFET)

Implications: 1 THz radio ICs, ~200-400 GHz digital ICs, 20 GHz ADCs/DACs