7/30/2019 10.1.1.94.6881

1/6

Modeling and Analysis of Circuit Performance ofBallistic CNFET

Bipul C Paul, Shinobu Fujita, Masaki Okajima, and Thomas Lee

Center for Integrated SystemsStanford University

420 Via PalouStanford, CA 94305-4070

Toshiba America Research Inc.2590 Orchard ParkwaySan Jose, CA 95131

Email: bpaul@tari.toshiba.com

ABSTRACTWith the advent of carbon nanotube technology, evaluating circuitand system performance using these devices is becomingextremely important. In this paper, we propose a quasi-analyticaldevice model for intrinsic ballistic CNFET, which can be used inany conventional circuit simulator like SPICE. This simple quasi-analytical model is seen to be effective in a wide variety ofCNFET structures as well as for a wide range of operating

conditions in the digital circuit application domain. We alsoprovide an insight how the parasitic fringe capacitance in state-of-the-art CNFET geometries impacts the overall performance ofCNFET circuits. We show that unless the device width can besignificantly reduced, the effective gate capacitance of CNFETwill be strongly dominated by the parasitic fringe capacitancesand the superior performance of intrinsic CNFET over siliconMOSFET cannot be achieved in circuit.

Categories and Subject DescriptorsI.6.5 [Simulation and Modeling]: Model Development modelingmethodologies.

General Terms Design, Performance.

KeywordsBallistic carbon nanotube FET (CNFET), circuit compatiblemodel, parasitic capacitance, circuit performance.

1. INTRODUCTIONAs silicon technology is approaching to its limit, several emergingdevices are studied to find a suitable alternative to silicon. Carbonnanotube FETs (CNFET) are shown to have potential of takingthis place in the post silicon era. Its interesting structural andelectrostatic properties (e.g., near ballistic transport) make itattractive for the future integrated circuit applications [1].Consequently, interests have grown to predict the performance ofthese devices in circuits and systems [2-6]. However, circuit

simulation using CNFET at present is a difficult task, becausemost of the developed device models are numerical [2, 7], whichconventional circuit simulators like SPICE can not handle. Agood analytical model to express the electrostatic properties (e.g.,I-V and C-V characteristics) of these devices is thus extremelynecessary for circuit simulation.A recent attempt has been made to achieve empirical analyticalexpressions to represent electrostatic properties of CNFET [6].

However, because of its underlying assumptions, this modelcannot accurately predict the device characteristics at all operatingconditions.In this paper, we propose a circuit compatible quasi-analyticaldevice model, which can be used for different semiconductingCNFET structures at all operating conditions in the digital circuitapplication domain. This compact model will greatly facilitate thecircuit simulation using any conventional simulator like SPICE.The model is developed assuming the ballistic transport ofCNFET [2] and shown to have close agreement with physicalmodel.We further provide in this paper, a quantitative analysis on thegeometry dependent parasitic capacitances of state-of-the-artCNFET structures and their impact on the circuit performance.Because of its high drive current (due to ballistic transport) the

intrinsic performance of CNFET has been predicted to be as highas in the range of Terahertz [3, 8, 9]. The effective circuit

performance in reality, is however, governed by the effective gatecapacitance of the device, which includes both (1) the intrinsicand (2) extrinsic (parasitic) capacitances. While the intrinsiccapacitance of CNFET has theoretically been shown to be only afew atto-farads [8-11], the parasitic capacitance, however, is astrong function of the device geometry. We show that the

performance of CNFET is limited by the process (the currenttechnique to fabricate CNFET) and that the device width needs to

be significantly reduced, in order to achieve the superiorperformance of intrinsic CNFET over silicon MOSFET in circuits.This analysis not only provides a realistic estimation of the

performance of CNFET circuits but also draws a very effectiveguideline to device design and optimization as well as processdevelopment.The rest of the paper is organized as follows. In section 2 wedescribe the proposed compact model of CNFET for circuitsimulation. Section 3 discuses the parasitic capacitances in state-of-the-art CNFET structures and its impact on circuit performancefollowed by a conclusion in section 4.

2. COMPACT MODEL OF CNFETFor circuit simulation using conventional simulator like SPICEwe need an analytical expression for device (e.g., I-Vand C-V)

Permission to make digital or hard copies of all or part of this work forpersonal or classroom use is granted without fee provided that copies

are not made or distributed for profit or commercial advantage and thatcopies bear this notice and the full citation on the first page. To copyotherwise, or republish, to post on servers or to redistribute to lists,

requires prior specific permission and/or a fee.DAC 2006, July 2428, 2006, San Francisco, California, USA.Copyright 2006 ACM 1-59593-381-6/06/0007$5.00.

41.2

717

7/30/2019 10.1.1.94.6881

2/6

characteristics in terms of applied terminal voltages (e.g., Vgs, Vds:see Fig. 1). However, it is impossible to obtain exact closed formexpressions directly by solving self consistent device equations [2,7]. We therefore, employ appropriate approximations toanalytically solve the device equations. We assume ballistictransport in MOSFET like single-walled CNFET with one-dimensional (1D) electrostatics [12]. Short channel MOSFET like

CNFETs are of particular interest because they are shown toprovide near ballistic current, thereby indicating maximumperformance [13, 14]. The carrier density for any sub-band (pth)of such nanotube transistor can be expressed as [2],

[ ]dEEfEfED

n dsE

p

ppc

)()(2

)(

,

+=

(1)

where )(ds is the source (drain) Fermi level, pcE , be the

conduction band minimum for the pth sub-band, )(Ef is theprobability that a state with energy E is occupied and )(ED is the

nanotube density-of-states, which can be approximated as2

,

2

0 || pcEEED for low bias [15]. )3/(80 bVD = , where

V and b are respectively, the carbon-carbon bonding energy and

the distance. Normalizing all energies and voltages by

( qTkB ) and substituting22

,2 zpc = ( E= ), Eq. (1)

can be written as,

2,

1

00

,0 )(

0 2,

2

DN

e

dzNn

dsiispcvvv

vzp

=

+

= =

+

(2)

wheres

( s ), vs and vd are the normalized surface, source

and drain potentials, respectively. Though solving Eq. (2)analytically is not possible, an approximate closed from solutioncan be obtained by dividing the operating condition into two parts.

ForTs < (below threshold), when 1

2

,

2>>+ spcz (for

all z: 0 ), Eq. (2) can be approximated to calculate thecharge as,

( ) sdspc eedzeqNQ vp

z

CNT

+

+

= 100

2,

2

se +

= 0 (3)

We consider the source potential as the reference potential and Vdsis the drain potential with respect to source. It is observed that

2/, = qE pcT is a good choice for the above

approximation. The integral of Eq. (3) can be precomputed

numerically and 0 can be analytically obtained for any drainvoltage. For qE pcsT /, , though a similar approximate solution can beachieved following the above approach with carefully expandingin series, we however, observed that Eq. (5) also efficiently

predicts the charge. Fig. 2 shows QCNTverses s obtained fromphysics model [numerical solution of Eq. (2)] and the aboveapproximate analytical model [Eq. (3) and (5)]. It can be seen that

the analytical models (with [Eq. (5)] and without correctionfactors [polynomial of order 4]) closely match with physics modelin both below [Fig. 2(a)] and above threshold [Fig. 2(b)].QCNTis further related to terminal voltage, Vgs (neglecting the flat-

band voltage; see Fig. 1(a)) as,

INS

CNTgsINSgss

C

QVVV == (6)

whereINS

C is the insulator capacitance. SubstitutingCNTQ in (6) an

analytical closed form expression forVg- s can be obtained as

=

+ )/( 01

gs

V

INS

gss eC

lambertwV

forTgs

VV

[ ]

22

21

022

2

11

22

11

2

)]([4)(

2

)(

TgsINSINS

INS

Ts

VCC

C

++

+=

forTgs VV >

(7)

s, QCNT

Vgs

CNT Channel

VINSIds

Gate

Cgd

Drain

Source

Rd

Cgs Rs

VFB

(a) (b)

Figure 1. (a) Schematic of a carbon nanotube transistor;

(b) Equivalent circuit of a ballistic one dimensional CNFETfor circuit simulation. Rs andRd are the source and drain

contact resistance, respectively.

718

7/30/2019 10.1.1.94.6881

3/6

where VT is the gate voltage (threshold voltage) corresponding to

T and can be obtained from Eqs. (3) and (6) with Ts = .

Knowings in terms of the terminal voltages the drain current,

Ids and gate input capacitance, CG (Fig. 1) can be easily obtainedas follows [6].

[ ] ++=p

Bds

ds eeh

TqkI )1ln()1ln(

4

and

gs

CNTG

V

QC

=

(8)

whereTk

qVEqB

ipcsi

= , ( dsi ,= ) and h is the Plancks

constant. Further, typical values forRs andRd(Fig. 1) can be usedbased on the experimental results for circuit simulation.Fig. 3 shows theI-V(Id-Vg andId-Vd) characteristics of a CNFETwith 2nm diameter and 48.3 pF/m insulator capacitance. It can beseen from the figure that while the model proposed in [6] does notmatch with the physical model for large bias conditions, our

proposed model matches closely for a wide range of biasconditions. Also note that since we did not make any abruptapproximation in our model, no discontinuity arises around thethreshold. We also verified our model for different nanotubediameters (1, 1.6, 1.7, 2 and 3nm) and obtained close match with

physical model in all cases. Note that we used physical model

with numerical solutions to compare our model due to theunavailability of adequate experimentally measured data withdifferent nanotube dimensions.Fig. 4 shows the SPICE simulation result of a two input NANDgate driving three identical gates [CNT: diameter=2nm andLch=20nm (Vdd= 0.9V)]. We used one nanotube for PCNFET andtwo parallel nanotubes for series connected NCNFETs. As can beseen from the figure, a considerably fast response time (2.52ps)was obtained using the intrinsic devices compared to theconventional ITRS 45nm CMOS technology prediction.

0 0.5 1 1.510

10

105

Vgs

(Volts)

Ids

(A/tube)

Physical

Analytical (prev.)

Proposed

Vds

=50mV

Vds

=0.5V

(a)

0 0.1 0.2 0.3 0.4 0.50

1

2

3

4

5

6

Vds

(Volts)

Ids

(A/tube)

Physical

Analytical (prev.)

Proposed

Vgs=0.25V

Vgs=0.5V

Vgs=0.35V

Vgs=1V

(b)

Figure 3.I-Vcharacteristics of CNFET with diameter =

2nm and CINS= 48.3 pF/m, VT=0.3V (T=300oK); (a)Ids-Vgs

for different Vds; (b)Ids-Vds for different Vgs.

0 0.05 0.1 0.15 0.2 0.25-34

-32

-30

-28

-26

-24

-22

s(volts)

ln(QCNT)

(Coulomb)

Physical [Eq. (2)]

Analytical [Eq. (3)]

T

0.15 0.2 0.250

1

2

3

4

s(volts)

QCNT

(x10-11Coulomb)

Physical [Eq. (2)]

Analytical (a)

Analytical (b)

(a) (b)

Figure 2. Charge vs. channel potential of a ballistic carbon nanotube FET. Physical model represents the numerical solution of

Eq. (2). (a)Ts

< ; (b)Ts

> ; the curve Analytical (a) represents the charge obtained from Eq. (5) (with correctionfactors), and Analytical (b) is the charge obtained from the polynomial expression of order 4 without using any empirical

parameter.

719

7/30/2019 10.1.1.94.6881

4/6

3. IMPACT OF PARASITICS ON CIRCUIT

PERFORMANCEIn this section we analyze the impact of parasitic capacitances onthe CNFET circuit performance. We first describe the effectivegeometry dependent parasitic components in state-of-the-artCNFET structures followed by a discussion on the overall circuit

performance with parasitics.

3.1 Geometry Dependent Parasitic

CapacitanceFig. 5(a) shows the schematic cross-section of a state-of-the-arttop gated CNFET structure [16, 17]. In this self aligned processthe gate electrode metal (height, Tg) is separated from the

source/drain (length, Lsd) metal approximately by sdox HT in

the vertical direction (Tox: oxide thickness,Hsd: source/drain metalthickness) and by the thin oxide (Lun) in the horizontal direction,that is used to isolate the gate metal during source/drain metaldeposition. The cross-sectional view of the electrostatic geometryof the device can be represented as shown in Fig. 5(b). The

parasitic capacitance in this structure, hence, consists of mainlythe gate/source and gate/drain fringe capacitances. The othercomponents such as gate to substrate and source/drain to substratecapacitances are expected to be very small (due to large SiO2thickness) and hence, are neglected in this analysis. The fringecapacitance (Cfr) of this geometry can be analytically calculatedusing the following equation [18].

dsgun

dsgun

TL

TL

dsgun

dsgun

gdsggungdsg

fr

eTL

WWk

TL

TTTLTTWC

/,

/,

2

/,

2

/,

/,22

/,

ln

2)(ln

2

+

++

+

++++=

(6)

Wheresdgdsggununsd

LTTTLLL /,

22 2exp +++= and

sdoxdsg HTT =/, . is the permittivity of medium, W is the

device width and kand are constants. A detail descriptionabout the above formulation can be found in [18]. In this analysis,we used SiO2 as the medium outside the device.

3.2 Analysis of Fringe CapacitanceFig. 6 shows the variation in Cfr with Tg (gate height) and Tox(oxide thickness). Cfr has two components; outer (Cof) and inner

(Cif) fringe capacitances. Unlike conventional MOSFET, inCNFET both Cofand Cif will substantially contribute to the totalfringe capacitance due to very narrow channel region (typicallyone nanotube in one micrometer width). Cofand Cfrare calculatedfollowing Eq. (6). It can be seen from the figure that for a typicalgeometry (Tg~30nm, Tox~8nm, Lun~1nm, Lsd~250nm, Hsd~7nm),Cfr is about two orders of magnitude larger than the typical deviceintrinsic capacitance (~1.5aF for 50nm gate [8]). The typicalwidth (W) of a state-of-the-art CNFET device is about 1m. Thisis necessary to ensure the nanotube channel under the gate. Hence,the circuit performance will be dominated by the parasitic fringecapacitances and the effectiveness of very low intrinsiccapacitance of CNFET can not be utilized in reality. Further, dueto the logarithmic dependency, Cfr is not a very sensitive functionofTg [Fig. 6(a)]. Tgalso can not be very thin since it increases thegate resistance drastically [18]. Cfr has a similar dependency onLsddue to the geometric symmetry and hence, varyingLsdwill notimpact Cfr significantly [Fig. 6(b)]. Cfr however, has a strongdependency on the gate oxide thickness (Tox) of the transistor. Itcan be seen from Fig. 6(c) that Cfr reduces steeply with theincrease in Tox around 8nm. This is because the electric fluxstrongly depends on the nearest distance between the electrodes.This implies that the use of high-K gate oxide will lead to lowereffective gate capacitance by employing larger Tox while stillhaving good gate control. Separating source and drain from thegate has also been tried by means of doping the nanotube outside

of gate region [19]. We studied the impact of this structure(analogous to underlap device) on Cfrby varyingLun. Though Cfrcan be reduced significantly by increasing Lun, it still remainssignificantly higher than intrinsic device capacitance [Fig. 6(d)]. Itis hence, evident from Fig. 6 that Cfr can not be reduced to theorder of intrinsic device capacitance by optimizing Tg, Tox,LsdandLun. One way to effectively reduce Cfris to reduce the width of thedevice (W). However, this not only calls for the improvement inthe control of nanotube fabrication but also requires improvementin lithography process. With present lithography equipmentachieving such small W(order of 10nm) is extremely difficult.

Si-substrate

SiO2

SOURCE DRAIN

Insulator

GATE

CNT

(a)

Cof

Cif

Si-substrate

SiO2

SOURCE DRAIN

Insulator

GATE

CNT

(a)

Si-substrate

SiO2

SOURCE DRAIN

Insulator

GATE

CNTSi-substrate

SiO2

SOURCE DRAIN

Insulator

GATE

CNT

(a)

Cof

Cof

CifCif

Gatemetal(T

g)

S/D metal (Lsd

)

Electric field

Tox-Hsd

Lun

(b)

Gatemetal(T

g)

S/D metal (Lsd

)

Electric field

Tox-Hsd

Lun

(b)

Al

Back gate

S D

SiO2

CNT Al2O3

Al

Back gate

S D

SiO2

CNT Al2O3

SOURCE D

RAIN

CNT

GATE

SOURCE D

RAIN

SOURCE D

RAIN

CNT

GATE

(c) (d)

Figure 5. (a) Schematic of a self-aligned top gated carbonnanotube transistor. (b) Electrostatic geometry for the

fringing field of the device. (c) Schematic of a dual-gate

(bottom) CNFET. (d) Schematic of a multiple FIN

CNFET equivalent to five parallel CNT channel.

Voltage(V)

0

1

0.6

0.2

0.8

0.4

11090 100 120Time (ps)

Output

Input

Delay=2.52ps

Voltage(V)

0

1

0.6

0.2

0.8

0.4

11090 100 120Time (ps)

Output

InputVoltage(V)

0

1

0.6

0.2

0.8

0.4

11090 100 120Time (ps)

Output

Input

Delay=2.52ps

Figure 4. Input/Output waveform of a 2 input NAND

driving three identical gates.

720

7/30/2019 10.1.1.94.6881

5/6

A dual (bottom) gate CNFET structure is also recently proposedfor improved performance [8, 20], in which the active gate isdeposited on top of the back SiO2 gate (below the nanotubechannel) and separated from the source and drain by a largedistance [Fig. 5(c)]. In this structure though the gate tosource/drain parasitic capacitances are expected to reduceconsiderably, the parasitic capacitance between the active and the

back gates is however, expected to be large if the back gate iscontrolled independently. It will consist of both overlap and fringecapacitances as shown in Fig. 5(c). For a typical structure withgate length 50nm and height 20nm, the parasitic capacitance wasfound to be 2.8x10-16 F with 1m width, which is much largerthan the intrinsic capacitance. On the other hand, if the back gateswitches with the active gate, though the capacitance between

them will be negligible, the overlap and fringe capacitancesbetween back gate and source/drain will be significantly high.

Efforts have also been put into increasing the transistor drivecurrent by introducing multiple nanotubes between the source anddrain (parallel nanotube channels). One such geometry has been

proposed in [16] (see Fig. 5(d)). In this self-aligned process onenanotube acts as multiple channels between the source and drain.We analyzed one such structure to understand its effectiveness inimproving the circuit performance. In a typical process, the gate

0 20 40 60600

650

700

750

800

Tg

(nm)

Cfr

[aF/m(

width)]

Lsd=250nmHsd

=7nm

Lun

=1nm

Tox

=8nm

0 100 200 300 400702

704

706

708

710

712

714

Lsd

(nm)

Cfr

[aF/m(

width)]

Tg=30nm

Hsd

=7nm

Lun

=1nm

Tox

=8nm

(a) (b)

5 10 15 20300

400

500

600

700

800

Tox

(nm)

Cfr

[aF/m(w

idth)]

Tg=30nm

Hsd

=7nm

Lun

=1nm

Lsd

=250nm

0 10 20 30 40 500

200

400

600

800

Lun

(nm)

Cfr

[aF/m(w

idth)]

Tg=30nm

Hsd

=7nm

Tox

=9nm

Lsd

=250nm

(c) (d)

Figure 6. Variation in fringe capacitance with device geometry; (a) with gate metal thickness, (b) with source/drain length, (c)

with oxide thickness and (d) with underlap.

Voltage(V)

0

1

0.6

0.2

0.8

0.4

500100 300 700

Time (ps)

1000

Intrinsic

CNFET

With parasitic CNFET

Si CMOS (45nm)

Voltage(V)

0

1

0.6

0.2

0.8

0.4

500100 300 700

Time (ps)

1000

Intrinsic

CNFET

With parasitic CNFET

Si CMOS (45nm)

Figure 7. Input/Output waveform of a 2 input NAND gatewith fanout 3 using CNFET (20nm gate length) and CMOS

BPTM 45nm technology.

721

7/30/2019 10.1.1.94.6881

6/6

FINs are separated by approximately 250nm and hence, besideseach individual gate FIN, the gate metal connecting the FINs alsocontributes to the total fringe capacitance. Hence, theimprovement in drive current will be masked by the increase incapacitance degrading the overall performance.To further analyze the impact of parasitic capacitance wesimulated a 2 input CNFET (20nm gate length) NAND gate

driving 3 identical gates and compared the same with siliconBPTM 45nm technology. The circuit simulation with CNFET wasperformed with the developed compact model discussed in section2. It can be seen from Fig. 7 that while the intrinsic delay ofCNFET NAND gate is very small (2.52ps) the delay with

parasitics (344ps) is much larger than silicon CMOS delay(165ps). This is because in 45nm technology the minimumtransistor size (NMOS transistor width=240nm in 2-input NAND)was much smaller than CNFET width (~1m). Further, thejunction capacitance was not considered in Si CMOS transistors.The above result confirms that the performance will be indeeddominated by the fringe capacitance, which is also expected todominate the effective gate capacitance in silicon [18].In the above analysis we have not taken interconnect into account.Interconnect may further limit the performance of CNFET circuits.

However, a quantitative analysis of performance withinterconnect, we feel, is too abstract at this point when there is toolittle information available about CNFET circuit layoutconfiguration.

4. CONCLUSIONSIn this paper, we provided a quasi-analytical circuit compatiblemodel for intrinsic ballistic CNFET. This model is seen to be veryeffective for various CNFET structures with a wide range of biasconditions, which can be used in conventional circuit simulators.We also provided a quantitative analysis on the parasiticcapacitance of state-of-the-art CNFET structures. We show thatthe parasitic capacitance cannot be significantly reduced byoptimizing gate metal thickness, gate oxide thickness orsource/drain length and that it can be effectively reduced only bydecreasing the width.

5. ACKNOWLEDGEMENTWe would like to thank Arijit Raychowdhury of PurdueUniversity and Jie Ding and Arash Hazeghi of StanfordUniversity for valuable discussions.

6. REFERENCES[1]P. Avouris, Supertubes: the unique properties of carbon

nanotubes may make them the natural successor to siliconmicroelectronics, IEEE Spectrum, pp. 40-45, Aug. 2004.

[2]J. Guo, S. Datta, and M. Lundstrom, Assesment of siliconMOS and carbon nanotube FET performance limits using ageneral theory of ballistic transistors, IEDM tech. digest, pp.29.3.1-29.3.4, 2002.

[3]J. Guo, A. Javey, H. Dai, and M. Lundstrom, Performanceanalysis and design optimization of near ballistic carbonnanotube FETs, IEDM tech. digest, pp. 703-706, 2004.

[4]G. Pennington, and N. Goldsman, Semiclassical transportand phonon scattering of electrons in semiconducting carbon

nanotubes, Physical Review B, vol. 68, pp. 045426-1-045426-11, 2003.

[5]C. Dwyer, M. Cheung, and D J. Sorin, Semi-empiricalSPICE Models for Carbon Nanotube FET Logic, IEEENano Letters, vol. 4, pp. 35-39, 2004.

[6]A. Raychowdhury, S. Mukhopadhyay, and K. Roy, Acircuit compatible model of ballistic carbon nanotube FETs,

IEEE Trans. on CAD, vol. 23, pp. 1411-1420, 2004.[7]K. Natori, Y. Kimura, and T. Shimizu, Characteristics of acarbon nanotube field-effect transistor analyzed as a ballisticnanowire field-effect transistor, Journal of Applied Physics,vol. 97, pp. 034306-1-034306-7, Jan, 2005.

[8]Y. Lin, J. Appenzeller, Z. Chen, Z. G. Chen, H. M. Cheng,and P. Avouris, High-performance dual-gate carbonnanotube FETs with 40-nm gate length, IEEE ElectronDevice Lett., vol. 26, n-11, Nov, 2005.

[9]K. Alam, and R. Lake, Performance of 2nm gate lengthcarbon nanotube field-effect transistors with source/drainunderlaps, Applied Physics Letters, vol. 87, pp. 073104-1-3,2005.

[10]D. L. John, L. C. Castro, and D. L. Pulfrey, Quantumcapacitance in nanoscale device modeling, Journal of

Applied Physics, vol. 96, n-9, pp. 5180-5184, 2004.[11]S. Rosenblatt, Y. Yaish, J. Park, J. Gore, V. Sazonova, and P.

L. McEuen, High performance electrolyte gated carbonnanotube transistors, Nano Letters, vol. 2, n-8, pp. 869-872,2002.

[12]P. L. McEuen, M. S. Fuhrer, and H. Park, Single walledcarbon nanotube electronics, IEEE Trans. on

Nanotechnology, vol. 1, pp. 78-85, 2002.[13]A. Javey, J. Guo, Q. Wang, M. Lundstrom, and H. Dai,

Ballistic carbon nanotube field-effect transistor, Nature,vol. 424, pp. 654-657, 2003.

[14]S. J. Wind, J. Appenzeller, and P. Avouris, Lateral scalingin carbon nanotube field-effect transistors, Physical ReviewLetters, vol. 91, pp. 058301-1-058301-4, Aug. 2003.

[15]J. W. Mintmire, and C. T. White, Universal density of states

for carbon nanotubes, Physical Rev. Lett., vol. 81, pp. 2506-2509, 1998.

[16]A. Javey, J. Guo, D. B. Farmer, Q. Wang, E. Yenilmez, R. G.Gordon, M. Lundstrom, and H. Dai, Self-aligned ballisticmolecular transistors and electrically parallel nanotubearrays, Nano Letters, vol. 4, n. 7, pp. 1319-1322, 2004.

[17]S. J. Wing, J. Appenzeller, R. Martel, V. Derycke, and P.Avouris, Vertical scaling of carbon nanotube field-effecttransistors using top gate electrodes, Applied Physics Lett.,vol. 80, pp. 3817, 2002.

[18]A. Bansal, B. C. Paul, and K. Roy, Modeling andoptimization of fringe capacitance of nanoscale DGMOSdevices, IEEE Trans. on Electron Devices, vol. 52, n 2, pp.256-262, 2005.

[19]J. Chen, C. Klinke, A. Afzali, and P. Avouris, Self-alignedcarbon nanotube transistors with charge transfer doping,Applied Physics Letters, vol. 86, pp. 123108-1-3, 2005.

[20]Y. Lin, J. Appenzeller, J. Knoch, and P. Avouris, High-performance carbon nanotube field-effect transistor withtunable polarities, IEEE Trans. on Nanotechnology, vol. 4,n-5, Sept, 2005.

722