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Digital Integrated Circuits2nd Inverter

Digital IntegratedDigital Integrated

CircuitsCircuits

A Design PerspectiveA Design Perspective

Basic Circuits forBasic Circuits forDigitalDigitalSystemsSystems

Dr. J. Raja Paul Perinbam

Dept. of ECEAnna University

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CMOS InverterCMOS Inverter

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The CMOS Inverter: A First GlanceThe CMOS Inverter: A First Glance

Vin Vout

CL

VDD

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Polysilicon

In Out

VDD

GND

PMOS2

Metal 1

NMOS

OutIn

VDD

PMOS

NMOS

Contacts

N Well

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Two InvertersTwo Inverters

Connect in Metal

Share power and ground

Abut cells

VDD

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First-Order DC AnalsisFirst-Order DC Analsis

VOL= 0

VOH= VDDVM= f(Rn, Rp)

VDD VDD

Vin 5 VDD Vin 5 0

VoutVout

Rn

Rp

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7/97 Digital Integrated Circuits2nd Inverter

CMOS Inverter: Transient !esponseCMOS Inverter: Transient !esponse

tpHL= f(Ron.CL)

= 0.69 RonCL

VoutVout

Rn

Rp

VDDVDD

Vin5VDDVin 5 0

(a) Low-to-high (b) High-to-low

CLCL

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"oltage Trans#er"oltage Trans#erCharacteristicCharacteristic

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PMOS $oad $inesPMOS $oad $ines

VDSp

IDp

VGSp=-!"

VGSp=-1VDSp

IDnVin=#

Vin=1!"

Vout

IDnVin=#

Vin=1!"

Vin= VDD$VGSpIDn= - IDp

Vout= VDD$VDSp

Vout

IDnVin= VDD$VGSpIDn= - IDp

Vout= VDD$VDSp

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CMOS Inverter $oad CharacteristicsCMOS Inverter $oad Characteristics

IDn

Vout

Vin= 2.5

Vin

= 2

Vin= 1.5

Vin= 0

Vin

= 0.5

Vin= 1

NMOS

Vin= 0

Vin= 0.5

Vin= 1Vin = 1.5

Vin = 2

Vin= 2.5

Vin= 1Vin= 1.5

PMOS

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CMOS Inverter "TCCMOS Inverter "TC

Vout

Vin0 . 5 1 1 . 5 2 2 . 5

0.

5

1

1.

5

2

2.

5

NMOS resPMOS off

NMOS satPMOS sat

NMOS offPMOS res

NMOS satPMOS res

NMOS resPMOS sat

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Deter%ining "Deter%ining "I&I&and "and "I$I$

VOH

VOLVin

Vout

VM

VIL VIH

A simplifed approach

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Propagation DelaPropagation Dela

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CMOS Inverter Propagation DelaCMOS Inverter Propagation Dela

Approach 'Approach 'VDD

Vout

Vin= VDD

C%Iav

tpHL= CLVs!n"#2

Iav

CL

$nV%%

&

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CMOS Inverter Propagation DelaCMOS Inverter Propagation Dela

Approach (Approach (VDD

Vout

Vin= VDD

Ron

C%

tpHL= f(Ron.CL)

= 0.69 RonCL

t

out

DD

RonC!

"

#.$

ln%#.$&

#.'(

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CMOS InvertersCMOS Inverters

Polysilicon

InOut

Metal'

VDD

GND

PMOS

NMOS

'.2=2

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Dela as a #unction o# "Dela as a #unction o# "DDDD

0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.41

1.5

2

2.5

3

3.5

4

4.5

5

5.5

VDD(V)

tp(normalized)

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I%pact o# !ise Ti%e on DelaI%pact o# !ise Ti%e on Dela

tpHL(n

se)

0.*+

0.*

0.2+

0.2

0.'+

t,!se(nse)'0.-0.60.0.20

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Inverter Si)ingInverter Si)ing

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Inverter ChainInverter Chain

CL

)f CLis given*

+,o- many stages are neee to minimi/e t0e elay1+,o- to si/e t0e inverters1

2ay nee some aitional constraints.

)n 3ut

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Inverter DelaInverter Dela

42inimum lengt0 evices5 !6#.7$m4Assume t0at for WP6 7WN =7W

4same pull+up an pull+o-n currents

4appro8. e9ual resistancesRN6RP4appro8. e9ual rise tpLHan fall tpHLelays

4Analy/e as an RC net-or:

WN

unit

Nunit

unit

PunitP RR

W

WR

W

WRR ==

=

11

tpHL= (ln 2)RNCL tpLH= (ln 2)RPCLDelay %D&*

7W

W

unit

unit

gin C

W

WC 3=!oa for t0e ne8t stage*

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Inverter with $oadInverter with $oad

!oa %CL&

Delay

Assumptions* no loa +; /ero elay

CL

tp= kRWCL

RW

RW

Wunit

6 "

kis a constant5 e9ual to #.(C"0as to be evenly istribute across N6 ' stages*

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Opti%u% ,##ective FanoutOpti%u% ,##ective Fanout ff

3ptimum f for given process efine by ( )ff += 1e$%

fopt6 '.(

for6"

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.u##er Design.u##er Design

"

"

"

"

(

(

(

(

7.

"(

77.(

N f tp

' 6 6+

2 - '-

* '+

2.- '+.*

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Power DissipationPower Dissipation

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/here Does Power Go in CMOS0/here Does Power Go in CMOS0

/ %0na(!) Poe, Cons1(pt!on

/ S2o,t C!,)1!t C1,,ents

/ Lea$a"e

C2a,"!n" an3 %!s)2a,"!n" Capa)!to,s

S2o,t C!,)1!t Pat2 4eteen S1ppl0 Ra!ls 31,!n" S!t)2!n"

Lea$!n" 3!o3es an3 t,ans!sto,s

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Dna%ic Power DissipationDna%ic Power Dissipation

&nergy'transition = C% ( Vdd

Power = &nergy'transition (f = C%( Vdd* f

)eed to reduce C%* Vdd* andfto reduce power!

Vin Vout

C%

V&&

)ot a +unction o+ transistor si,es

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Modification for Circuits with Reduced Swing

CL

Vdd

Vdd

Vdd -Vt

E0 1 CL Vdd Vdd Vt( )=

Can exploit reduced swing to lower power

(e.g., reduced bit-line swing in memory)

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Static Power ConsumptionStatic Power Consumption

Vin=5V

Vout

CL

Vdd

Istat

Pstat= P(In=1).Vdd. Istat

'aste& ener *S#oul& +e a,oi&e& in al-ost all ases

+ut oul& #el% re&uin ener in ot#ers (e.. sense a-%s)

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Principles #or Power !eductionPrinciples #or Power !eduction

Prime c0oice* Reuce voltage Recent years 0ave seen an acceleration in

supply voltage reuction

Design at very lo- voltages still open 9uestion

%#.( @ #.< by 7#"#&

Reuce s-itc0ing activity

Reuce p0ysical capacitance

Device Si/ing* for !67#F fopt%energy&6'.$'5 fopt%performance&6.G

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I%pact o#I%pact o#

TechnologTechnolog

ScalingScaling

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Technolog ScalingTechnolog Scaling

Hoals of scaling t0e imensions by '#I*

Reuce gate elay by '#I %increase operating

fre9uency by 'I&

Double transistor ensity Reuce energy per transition by ($I %$#I po-er

savings 'I increase in fre9uency

Die si/e use to increase by "I per

generation

Kec0nology generation spans 7+' years

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Technolog Scaling ModelsTechnolog Scaling Models

/ 51ll Sal!n" (Constant let,!al 5!el3)

/ 5!7e3 Volta"e Sal!n"

/ 8ene,al Sal!n"

!3eal o3el 3!ens!ons an3 volta"e sale

to"ete, 4 te sae fato, S

ost oon o3el 1nt!l ,eentl

onl 3!ens!ons sale: volta"es ,ea!n onstant

ost ,eal!st! fo, to3as s!t1at!on volta"es an3 3!ens!ons sale !t 3!ffe,ent fato,s

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DesignDesign$aout !ules$aout !ules

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CMOS ProcessCMOS Process

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A Modern CMOS ProcessA Modern CMOS Process

%/"ell n/"ell

%0

%/e%i

SiO2

1lu

%ol)

n0

SiO2

%0

(ate/o$i&e

.ungsten

3iSi2

Dual+ell Krenc0+)solate C23S ProcessDual+ell Krenc0+)solate C23S Process

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Circuit 1nder DesignCircuit 1nder Design

VDD VDD

Vin

Vout

M1

M2

M3

M4

Vout2

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Its $aout "iewIts $aout "iew

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2D Perspective2D Perspective

Polysilicon Aluminum

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Design !ulesDesign !ules

)nterface bet-een esigner an process

engineer

Huielines for constructing process mas:s Unit imension* 2inimum line -it0

scalable esign rules* lamba parameter

absolute imensions %micron rules&

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CMOS Process $aersCMOS Process $aers

Lae,

Polysilicon

2etal"

2etal7

Contact Ko Poly

Contact Ko Diffusion

ia

ell %p5n&

Active Area %n=5p=&

Colo, Rep,esentat!on

Lello-

Hreen

Re

Blue

2agenta

Blac:

Blac:

Blac:

Select %p=5n=& Hreen

i

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$aers in 34(5$aers in 34(5 % CMOS process% CMOS process

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Intra-$aer Design !ulesIntra-$aer Design !ules

Metal2

*

10

90

Well

Active3

3

Polysilicon

2

2

Different PotentialSame Potential

Metal1 3

3

2

Contactor Via

Select

2

or6

2Hole

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Transistor $aoutTransistor $aout

1

2

5

3

Transistor

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"ias and Contacts"ias and Contacts

1

2

1

Via

Metal toPoly ContactMetal to

Active Contact

1

2

5

4

3 2

2

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Select $aerSelect $aer

1

3 3

2

2

2

WellSubstrate

Select

3

5

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CMOS Inverter $aoutCMOS Inverter $aout

A A

np-substrate Field

Oxidep+

n+

In

Out

GND VDD

(a) Layout

(b) Cross-Section along A-A

A A

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$aout ,ditor$aout ,ditor

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Design !ule Chec6erDesign !ule Chec6er

pol;not;fet to all;3!ff !n!1 spa!n" = 0.' 1.

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Stic6s Diagra%Stic6s Diagra%

1

3

In Out

VDD

GND

St!$ 3!a",a of !nve,te,

4Dimensionless layout entities43nly topology is important4inal layout generate by

McompactionN program

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Construction o#Construction o#

%ultipleers7%ultipleers7

trans%ission gates7trans%ission gates7latches7 #lip-#lopslatches7 #lip-#lops

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Se8uential $ogicSe8uential $ogic

2 sto,a"e ean!ss

/ pos!t!ve fee34a$

/ a,"e

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$atch versus !egister$atch versus !egister

!atc0stores ata -0en

cloc: is lo-

D

l4

D

l4

Registerstores ata -0en

cloc: rises

l4 l4

D D

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$atches$atches

In

clk

In

Out

Positive Latch

CLK

D

G

Q

Out

Outstable

Outfollows In

In

clk

In

Out

Negative Latch

CLK

D

G

Q

Out

Outstable

Outfollows In

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$atch-.ased Design$atch-.ased Design

6N lat# is trans%arent

"#en = 06P lat# is trans%arent

"#en = 1

N

7at#7oi

7oi

P

7at#

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Ti%ing De#initionsTi%ing De#initions

t

CLK

t

D

tc.q

tholdtsu

t

Q DATA

TA!L"

DATATA!L"

'egister

CLK

D Q

i i d+ 6 i S +iliP iti F d+ 6 .i St +ilit

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Positive Feed+ac6: .i-Sta+ilitPositive Feed+ac6: .i-Sta+ilit/i1 /o.

/o.=/i1

/o1=/i.

/o1

/i.5/o1

/i.5/o1

/i1

A

#

/o.

/i1 =/o.

/o1 /i.

/i. =/o1

M S +iliM t St +ilit

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Meta-Sta+ilitMeta-Sta+ilit

#$in s%oul& 'e l$e t%$n * in t%e t$nsition e

A

#

/i.5/o1

/i1 5/o.

A

#

/i.5/o1

/i1 5/o.

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/riting into a Static $atch/riting into a Static $atch

L*

L*

L*

,

+ ,

L*

L*

,

onerting into a "23orcing the state(can implement as %"!-onl4)

se the cloc as a decopling signal6that distingishes between the transparent and opa7e states

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M . d $ t hM . d $ t h

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Mu-.ased $atchMu-.ased $atch

L*

L*

L*

,

+

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Mu-.ased $atchMu-.ased $atch

L*

L*

L*

L*

+"

+"

%"! onl4 %on-oerlapping clocs

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Master-Slave 9,dge-TriggeredMaster-Slave 9,dge-Triggered

!egister!egister

1

0D

CLK

QM

"aster

0

1

CLK

Q

lae

QM

Q

D

&wo opposite latches trigger on edgeAlso called master-slae latch pair

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Master-Slave !egisterMaster-Slave !egister

QM

Q

D

CLK

T.I.

T1I1

I8 T9I5

T8I9

I:

"ltipleer-based latch pair

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Cl6-; DelaCl6-; Dela

D

Q

CLK

. 0;5

0;5

1;5

.;5

tc.q(lh

0;5 1 1;5 . .;50

time6 nsec

/olts

tc.q(hl

O h h < i C( OS

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Other $atches

M1

D Q

M3CLK

M8

M2

CLK

VDD

CL1

X

CL2

Master Stae

M5

M9CLK

CLK M!

M:

VDD

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Ti%ing andTi%ing andFan-outFan-out

considerationsconsiderations

h

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$atch Para%eters$atch Para%eters

D

l4

D

l4

t!"

t#ol$

PW%t&u

t$!"

D"#$%& '$n " iff"*"nt fo* *i&ing $n f$##ing $t$ t*$n&ition&

'

i

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!egister Para%eters!egister Para%eters

D

l4

D

l4

t!"

t#ol$

'

t&u

D"#$%& '$n " iff"*"nt fo* *i&ing $n f$##ing $t$ t*$n&ition&

Cl 6 1 i i

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Cloc6 1ncertaintiesCloc6 1ncertainties

7

'

Po+"* Supp#%

Int"*'onn"'t

$ "-p"*$tu*"

( C$p$'iti." Lo$

G Coup#ing to $'"nt Lin"&

" C#o'k 1"n"*$tion

D".i'"&

Sou*'"& of '#o'k un'"*t$int%

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l 6 6 d iCl 6 S6 d =i

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Cloc6 S6ew and =itterCloc6 S6ew and =itter

Bot0 s:e- an jitter affect t0e effective cycle time

3nly s:e- affects t0e race margin

l4

l4

tS2

t3S

Cl 6 S6Cl 6 S6

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Cloc6 S6ewCloc6 S6ew

o eistes

Clk&el$y1nsetion &el$y

$3 Clks4e-

"$liest occuenceo Clke&eomin$l 5 >.

L$test occuenceo Clke&e

omin$l + >.

P i i d * i S6P iti d * ti S6

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Positive and *egative S6ewPositive and *egative S6ew

R"In

%a& Positive s:e-

Co-in$tion$#Logi'

D Q

tCL2CLK

3ela

tCL24

R7

D QCo-in$tion$#

Logi'

tCL25

R'

6 6 6D Q

3ela

R"In

%b& ?egative s:e-

Co-in$tion$#Logi'

D Q

tCL2

3ela

tCL24

R7

D QCo-in$tion$#

Logi'

tCL25

R'

6 6 6D Q

P i i S6P iti S6

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Positive S6ewPositive S6ew

CLK1

CLK2

CL2

CL2+

+t7

7

"

L$un'7ing "g" $**i."& "fo*" t7" *"'"i.ing "g"

* ti S6* ti S6

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*egative S6ew*egative S6ew

CL2

CL24

CL2

CL2

7

"

'

R"'"i.ing "g" $**i."& "fo*" t7" #$un'7ing "g"

Ti i C t i tTi i C t i t

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Ti%ing ConstraintsTi%ing Constraints

R"

D QCo-in$tion$#

Logi'

In

CLK tCL2

R7

D Q

tCL24

t' 9t' 9, ' t&u,t7o#

t#ogi't

Mini-u- '%'#" ti-":

= t'9 t&u t#ogi'

Wo*&t '$&" i& +7"n *"'"i.ing "g" $**i."& "$*#% (po&iti." )

Ti i C t i tTi i C t i t

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Ti%ing ConstraintsTi%ing Constraints

R"D Q

Co-in$tion$#Logi'

In

CLK tCL2

R7D Q

tCL24

t' 9t' 9, '

t&u,t7o#

t#ogi't

Ho# ti-" 'on&t*$int:

t('9, ') t(#ogi', ')< t7o#

Wo*&t '$&" i& +7"n *"'"i.ing "g" $**i."& #$t"

R$'" "t+""n $t$ $n '#o'k

I t # =ittI t # =itt

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I%pact o# =itterI%pact o# =itter

CLK

+tjit te r

'C LK

tj itter

CLK

InCo%(inational

Logi

tc-q

, tc-q, cd

tlog ic

tlog ic, cdtsu, thold

REHS

tjit ter

Fli Fl . d Ti iFlip Flop .ased Ti%ing

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Flip-Flop > .ased Ti%ingFlip-Flop > .ased Ti%ing

;li%flo%

7oi

= 1 = 0

3lip-opdela4

ew

Logic dela4

')*'

Clk!Q

R"p*"&"nt$tion $ft"*

M Ho*o+it>, VLSI Ci*'uit& ??@

Fli Fl d D i $ iFlip Flops and Dna%ic $ogic

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Flip-Flops and Dna%ic $ogicFlip-Flops and Dna%ic $ogic

= 1 = 0

Logic dela4

')*'Clk!Q

= 1 = 0

Logic dela4

')*'Clk!Q

Prec0argeEvaluateEvaluatePrec0arge

lip+flops are use only -it0 static logic

$ t h ti i$atch ti%ing

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$atch ti%ing$atch ti%ing

D

Cl4

tD7

tCl47

8%en &$t$ $i,esto t$nsp$ent l$tc%

8%en &$t$ $i,es

to close& l$tc%

D$t$ %$s to 'e e7l$unc%e&:

L$tc% is $ sot: '$ie

Single Phase Cloc6 ith $atchesSingle Phase Cloc6 with $atches

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Single-Phase Cloc6 with $atchesSingle-Phase Cloc6 with $atches

7at#

7oi

l4

P

PW

'&kl '&kl '&kt'&kt

$atch .ased Design$atch .ased Design

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$atch-.ased Design$atch-.ased Design

71

7at#7oi

7oi

72

7at#

71 lat# istrans%arent

"#en = 0

72 lat# is trans%arent"#en = 1

$atch .ased Ti%ing$atch .ased Ti%ing

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$atch-.ased Ti%ing$atch-.ased Ti%ing

71

7at#7oi

7oi

72

7at#

= 1

= 0

L1 latch

L. latch

ew

C$n tole$te s4e-;

Longpath

hortpath

Static logic

Fan in and Fan outFan in and Fan out

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Fan-in and Fan-outFan-in and Fan-out

N

an+out N an+in M

M

The Ideal GateThe Ideal Gate

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The Ideal GateThe Ideal Gate

Ri 6

Ro 6 #anout 6 ?2,6 ?2!6 DD>7

g6

Vin

Vout

7/24/2019 4909278 CMOS Inverter

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Than6 ou ?Than6 ou ?

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4909278 CMOS Inverter