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SRAM BASED DELAY BUFFER USING GATED DRIVERTREE

1.2 MEMORY ORGANISATION:

emory organi/ation is t!o$fold. ,irst !e discuss the hard!are (physical)

organi/ation then the internal architecture. The type of computer and its si/e do not

reflect the type of memories that the computer uses. Some computers have a mixture of

memory types. ,or example they may use some type of magnetic memory (core or film)

and also a semiconductor memory (static or dynamic). They also have a read$only

memory !hich is usually a part of the *01. emory in a computer can vary from one or

more modules to one or more pcb2s depending on the computer type. The larger

mainframe computers use the modular arrangement multiple modules (four or more) to

make up their memories. 'hereas minicomputers and microcomputers use chassis

or assemblies cages or racks and motherboard or backplane arrangements. inis

and micros use multiple components on one pcb or groups of pcb2s to form the

memory.

There are several !ays to organise memories !ith respect to the !ay they are

connected to the cache

1.2.1 ONE-WORD-WIDE MEMORY ORGANISATION

The memory is one !ord !ide and connected via a one !ord !ide bus to the

cache.

1.2.2 WIDE MEMORY ORGANISATION

The memory is more than one !ord !ide (usually four !ords !ide) and

connected by an e#ually !ide bus to the lo! level cache (!hich is also !ide). ,rom the

cache multiple busses of one !ord !ide go to a 13 !hich selects the correct bus to

connect to the high level cache.

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1.2.3 INTERLEAVED MEMORY ORGANISATION

There are several memory banks !hich are one !ord !ide and one one !ord

!ide bus. There is some logic in the memory that selects the correct bank to use !hen the

memory gets accessed by the cache.

emory interleaving is a !ay to distribute individual addresses over memory

modules. Its aim is to keep the most of modules busy as computations proceed. 'ith

memory interleaving the lo!$order k bits of the memory address select a module and the

high$order m bits name a location !ithin that module. 4ence consecutive addresses are

located in successive modules. % re#uest to access consecutive memory locations can

keep several modules busy at the same time.

1.2.4 INDEPENDENT MEMORY ORGANISATION

There are several banks !hich can all be accessed simultaneously by several

buses.

Mem!" #eme$!":

In the design of modern personal computers memory geometry describes the

internal structure of random$access memory. emory geometry is of concern to

consumers upgrading their computers since older memory controllers may not be

compatible !ith later products. emory geometry terminology can be confusing because

of the number of overlapping terms.

1.3 PHYSICAL FEATURES

emory geometry describes the logical configuration of a -% module but

consumers !ill al!ays find it easiest to grasp the physical configuration. uch of the

confusion surrounding memory geometry occurs !hen the physical configuration

obfuscates the logical configuration. The first defining feature of -% is form factor.

-% modules can be in compact S"$5I form for space constrained applications like

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laptopsprinters embeddedcomputers and smallformfactor computers and in 5I

format !hich is used in most desktops.

The other physical characteristic determine !ith by physical examination are the

number of memory chips and !hether both sides of the memory 6stick6 are populated. If

7 is a factor of the number of memory devices or chips (or more generally a po!er of

t!o) then the module does not feature 8** if 9 is a factor of the number of memory

chips (or one more than a po!er of t!o) then the module does. -% modules are :keyed:

by indentations on the sides and along the bottom of the module. This determines the

technology and classification of the modules for instance !hether it is 55-; or 55-


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that for each module in any one channel there is a logically identical module in the same

location on each of the other populated channels.

+ingston describes each module as having a geometry of ;>x?7

meaning that each one has ?7 bits ;> million deep e#ualing >.9; billion bits or

.;7 @igabytes. +ingston describes each 6device6 or chip as having a geometry of

?7x> so each module has four banks. So from the *4 0"V!hen there are 7

@= modules it sees ; channels each !ith > banks.

1.% HIERARCHY OF ORGANI&ATION

1.%.1 MEMORY CHIP

The lo!est form of organi/ation covered by memory geometry sometimes

called 6memory device6. These are the component I*s that make up each module

or module of -%. The most important measurement of a chip is its density

measured in bits. =ecause memory bus !idth is usually larger than the number of

chips most chips are designed to have !idth meaning that they are divided into

e#ual parts internally and !hen one address 6depth6 is called up instead of

returning Aust one value more than one value is returned. In addition to the depth a

second addressing dimension has been added at the chip level banks. =anks allo!

one bank to be available !hile another bank is unavailable because it is refreshing.

%n example of chip notation is ?7b (depth) 3 > (!idth) 3 > =anks.

1.%.2 MEMORY MODULE

Some measurements of modules are si/e !idth speed and latency. %

memory module consists of a multiple of the memory chips to e#ual the desired

module !idth. So a $bit !ide (x>)

chips. %s noted in the memory channel part one physical module can be made up of

one or more logical ranks. If that $bit chips

the simm !ould have t!o ranks. %n example of odule notation is ;>b x ?7$bit.

1.%.3 MEMORY CHANNEL

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% memory channel is made up of ranks. 0hysically a memory channel !ith Aust

one memory module might present itself as having one or more logical ranks.

1.%.4 CONTROLLER ORGANI&ATION

This is the highest level. In a typical computer there !ill only be a single memory

controller !ith only one or t!o channels. The logical features section described &1%

configurations !hich can take the form of a net!ork of memory controllers. ,or

example each socket of a t!o socket %5 +> can have a t!o channel memory

controller giving the system a total of four memory channels.

1.%.% RANDOM-ACCESS MEMORY

-andom$access memory (-%) is a form of computer data storage. Today it

takes the form of integrated circuits that allo! stored datato be accessed in any order

(that is at random). 6-andom6 refers to the idea that any piece of data can be returned in

aconstant time regardless of its physical location and !hether it is related to the previous

piece of data.BC

The !ord 6-%6 is often associated !ith volatile types of memory such as

5-%(memory modules) !here the information is lost after the po!er is s!itched off.

any other types of memory are -% as !ell including most types of -"and a type

of flash memorycalled&"-$,lash.

1.%.' TYPES OF RAM

odern types of !ritable -% generally store abit of datain either the state of a

flip$flop as in S-%(static -%) or as a chargein a capacitor(or transistorgate) as in

5-% (dynamic -%) 80-" 880-" and ,lash. Some types have circuitry to

detect andDor correct random faults called memory errors in the stored data using parity

bits or error correction codes.-% of the read$only type -" instead uses a metal

mask to permanently enableDdisable selected transistors instead of storing a charge inthem. "f special consideration is a SI and 5I memory module.

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S-% and 5-% are volatile. "ther forms of computer storage such as disks

andmagnetic tapes have been used aspersistent storage. any ne!er products instead

rely on flash memory to maintain data !hen not in use such as 05%sor small music

players. *ertainpersonal computers such as manyrugged computersand netbooks have

also replaced magnetic disks !ith flash drives. 'ith flash memory only the&"- typeis

capable of true random access allo!ing direct code execution and is therefore often used

instead of -"E the lo!er cost &%&5 type is commonly used for bulk storage in

memory cardsand solid$state drives. % memory chip is an integrated circuit (I*) made of

millions of transistors and capacitors. In the most common form of computer memory

dynamic random access memory (5-%) a transistor and a capacitor are paired to

create a memory cell !hich represents a single bit of data. The capacitor holds the bit of

information F a or a . The transistor acts as a s!itch that lets the control circuitry on

the memory chip read the capacitor or change its state.

Mem!" ()e!*!+(":

any computer systems have a memory hierarchy consisting of *01 registers

on$die S-%caches external caches 5-%paging systems and virtual memoryor

s!ap spaceon a hard drive. This entire pool of memory may be referred to as 6-%6 by

many developers even though the various subsystems can have very different access

times violating the original concept behind the random access term in -%. 8ven !ithin

a hierarchy level such as 5-% the specific ro! column bank rank channel or

interleaveorgani/ation of the components make the access time variable although not to

the extent that rotating storage media or a tape is variable. The overall goal of using a

memory hierarchy is to obtain the higher possible average access performance !hile

minimi/ing the total cost of the entire memory system (generally the memory hierarchy

follo!s the access time !ith the fast *01 registers at the top and the slo! hard drive at

the bottom).

In many modern personal computers the -% comes in an easily upgraded form

of modules called memory modulesor 5-% modules about the si/e of a fe! sticks of

che!ing gum. These can #uickly be replaced should they become damaged or !hen

changing needs demand more storage capacity. %s suggested above smaller amounts of

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-% (mostly S-%) are also integrated in the *01and other I*son the motherboard

as !ell as in hard$drives *5$-"sand several other parts of the computer system.

=y convention bus and net!ork data rates are denoted either in bitDs (bits per

second) or byteDs(bytes per second). In generalparallelinterfaces are #uoted in byteDs

and serialinbitDs. The more commonly used is sho!n belo! in bold type.

"n devices like modems bytes may be more than > bits long because they may be

individually padded out !ith additional start and stop bitsE the figures belo! !ill reflect

this. 'here channels use line codes (such as 8thernet Serial %T% and 0*I 8xpress)

#uoted rates are for the decoded signal.

The figures belo! are simplexdata rates !hich may conflict !ith the duplex rates

vendors sometimes use in promotional materials. 'here t!o values are listed the first

value is the do!nstream rate and the second value is the upstream rate.

%ll #uoted figures are in metric decimal units!hereG

=yte H > bit

kbitDs H ;7 bitDs

bitDs H ;7 kbitDs

@bitDs H ;7 bitDs

k=Ds H ;7 =yteDs

=Ds H ;7 +=yteDs

@=Ds H ;7 =yteDs

T=Ds H ;7 @=yteDs

These decimal prefixes have been established in data communications for long

time also before 99> !hen I8* and other organi/ations tried to make it standard for all

computing applications and introduced ne! binary prefixes.

1.%., MEMORY SYSTEM

emory in a computer system is re#uired for storage and subse#uent retrieval of

the instructions and data. % computer system uses variety of devices for storing these

instructions and data !hich are re#uired for its operations. &ormally !e classify the

information to be stored on computer in t!o basic categoriesG 5ata and the Instructions.

6The storage devices along !ith the algorithm or information on ho! to control andmanage these storage devices constitute the memory system of a computer.6

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% memory system is a very simple system yet it exhibits a !ide range of

technology and types. The basic obAective of a computer system is to increase the speed

of computation. Like!ise the basic obAective of a memory system is to provide fast

uninterrupted access by the processor to the memory such that the processor can operate

at the speed it is expected to !ork.

=ut does this kind of technology !here there is no speed gap bet!een processor

and memory speed exist. The ans!er is yes they do but unfortunately as the access time

(time taken by *01 to access a location in memory) becomes less and less the cost per bit

of memory becomes increasingly higher. In addition normally these memories re#uire

po!er supply till the information need to be stored. =oth these things are not very

convenient but on the other hand the memories !ith smaller cost have very high access

time !hich !ill result in slo!er operation of the *01. Thus the cost vs access time

anomaly has lead to a hierarchy of memory !here !e supplement fast memories !ith

larger cheaper slo!er memories. These memory units may have very different physical

and operational characteristics therefore making the memory system very diverse in

type cost organisation technology and performance.

*. I$e!* P!+e//! Mem!)e/G

These consist of the small set of high speed registers !hich are internal to a

processor and are used as temporary locations !here actual processing is done. This !ill

be covered in greater details in =lock ;.

0. P!)m*!" Mem!" ! M*) Mem!"G

It is a large memory !hich is fast but not as fast as internal processor memory.

This memory is accessed directly by the processor. It is mainly based on integrated

circuits. Secondary emoryD%uxiliary emoryD=acking StoreG %uxiliary memory in fact

is much larger in si/e than main memory but is slo!er than main memory. It normally

stores system programs (programs !hich are used by system to perform various

operational functions) other instructions programs and data files. Secondary memory can

also be used as an overflo! memory in case the main memory capacity has beenexceeded. Secondary memories cannot be accessed directly by a processor. ,irst the

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information of these memories is transferred to the main memory and then the

information can be accessed as the information of main memory.

There is another kind of memory !hich is increasingly being used in modern

computers this is called *ache memory. It is logically positioned bet!een the internal

memory (registers) and main memory. It stores or catches some of the content of the main

memory !hich is currently in use of the processor. 'e !ill discuss about this memory in

greater details in a subse#uent section of this unit.

=efore discussing more about these memories let us first discuss the technological

terms commonly used in defining and accessing the memory.

1.%. CHARACTERISTICS TERMS FOR VARIOUS MEMORY DEVICES

The follo!ing terms are most commonly used for identifying comparative

behaviour of various memory devices and technologies.

1.%..1 STORAGE CAPACITY:

It is a representative of the si/e of the memory. The capacity of internal memory

and main memory can be expressed in terms of number of !ords or bytes. The storage

capacity of external memory is normally measured in terms of bytes.

U)$ $!*/e!:

1nit of transfer is defined as the number of bits read in or out of the memory in a

single read or !rite operation ,or main memory and internal memory the normal unit of

transfer of information is e#ual to the !ord length of a processor. In fact it depends on

number of data lines in and out of the memory module. ('hyJ) In general these lines are

kept e#ual to the !ord si/e of the processor. 'hat is a !ordJ Kou have already learnt

about this term in 1nit of this block. The unit of transfer of external memory is

normally #uite large ('hyJ Kou !ill find the ans!er to this #uestion later in this unit)

and>is referred to as block of data.

1.%..2 ACCESS MODES:

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"nce !e have defined the unit of transfer next important characteristics is the

access mode in !hich the information is accessed from the memory. % memory is

considered to consist of various memory locations. The information from memory

devices can be accessed in the follo!ing !ays.

1.%..3 RANDOM ACCESS MEMORY RAM:

It is the mode in !hich any memory location can be accessed in any order in the

same amount of time. ,errite and Semiconductor memories !hich generally constitute

main memory are of this nature. The storage locations can he accessed independently and

there exist separate access mechanism for each location.

1.%..4 SE5UENTIAL ACCESS:

"n the other hand !e have memories !hich can be accessed in pre$defined

se#uences for exampleE the songs stored on a cassette can be accessed only one by one.

The example of se#uential access memory is agnetic Tape. 4ere the access mechanism

needs to be shared among different locations. Thus either the location or the readD!rite

head or both should be moved to access the desired location.

1.%..% DIRECT ACCESS:

In certain c apses the information is neither accessed randomly nor in se#uence

but something in bet!een. In this kind of access a separate readD!rite head exist for a

track and on a track the information can be accessed serially. These semi$random modes

of operation exist in magnetic disks.

1.%..' ACCESS TIME:

The access time is the time re#uired bet!een the re#uest made for a read or !rite

operation till the time the data is made available or !ritten at the re#uested location.

&ormally it is measured for read operation. The access time depends on the physicalcharacteristics and access mode used for that device. 0ermanence or StorageG Is it

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0ossible to lose information by the memories over a period of time. The reasons of the

loss of information and !hat should be done to avoid it. There are several reasons for

information destruction these are destructive readout dynamic storage volatility and

hard!are failure.

If for a particular memory the reading process destroys the stored information. !e

call it 5estructive readout. In such memories the information has to be !ritten back on

the same location from !hich it had been read after each read operation. The reading

process !here the data is not destroyed on reading are referred to as &on$destructive

readout. There can be some memories !here the stored looses its strength to become

over a period of time. These kind of memories re#uire refreshing. The memories !hich

re#uire refreshing are termed as dynamic memories. In contrast the memories !hich do

not re#uire refreshing are called static memories.

%nother factor !hich can destroy the contents is die presence and absence of

electricity. The memories !hich loses their content on failure of po!er am armed as

volatile memories those !hich do not are called non$volatile. agnetic memories are

non$volatile and semiconductor main memories am volatile in nature.

C"+e T)me:

It is defined as the minimum time elapsed bet!een t!o consecutive read re#uests.

Is it e#ual to access timeJ Kes for most of the memories except the ones in !hich

destructive readout is encountered. *ycle time for such memories is the access time (time

elapsed !hen a read re#uest is made available) plus !riting time as after the data has been

made available the information has to be !ritten back in the same memory location as the

previous value has been destroyed by reading. =ut for most of the commonly used

semiconductor memories cycle time is e#ual to the access time

2. DELAY 6UFFERS2.1 DELAY 6UFFERS

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This section describes 085I%:s implementation of delay buffer. 5elay buffer

!orks #uite similarly like a fixed Aitter buffer that is it !ill delay the frame retrieval by

some interval so that caller !ill get continuous frame from the buffer. This can be useful

!hen the operations are not evenly interleaved for example !hen caller performs burst of

put() operations and then follo!ed by burst of operations. 'ith using this delay buffer

the buffer !ill put the burst frames into a buffer so that get() operations !ill al!ays get a

frame from the buffer (assuming that the number of get() and put() are matched).

The buffer is adaptive that is it continuously learns the optimal delay to be

applied to the audio flo! at run$time. "nce the optimal delay has been learned the delay

buffer !ill apply this delay to the audio flo! expanding or shrinking the audio samples as

necessary !hen the actual audio samples in the buffer are too lo! or too high.

F)# 2.1:=uffer

2.2 E7ISTING TECHNI5UE:

F)# 2.2:8xisting =lock "f emory "rganisation

2.2.1 INPUT 6UFFER:

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The Input buffer is also commonly kno!n as the input area or input block.

'hen referring to computer memory the input buffer is a location that holds all incoming

information before it continues to the *01 for processing.

Input buffer can be also used to describe various other hard!are or soft!are

buffers used to store information before it is processed.

Some scanners (such as those !hich support MincludeN files) re#uire reading from

several input streams. %s flex scanners do a large amount of buffering one cannot control

!here the next input !ill be read from by simply !riting a KKOI&01T() !hich is

sensitive to the scanning context. KKOI&01T() is only called !hen the scanner reaches

the end of its buffer !hich may be a long time after scanning a statement such as an

include statement !hich re#uires s!itching the input source.

a

b

F)# 2.3: Input=uffer

T*0e 2.1: Truth Table ,or

ux

2.2.2 MEMORY 6LOC8:

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S I I; "ut

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(-%) -andom$access memory (-%) is a form of computer data storage.

Today it takes the form of integrated circuitsthat allo! stored datato be accessed in any

order (that is at random). 6-andom6 refers to the idea that any piece of data can be

returned in a constant time regardless of its physical location and !hether it is related to

the previous piece of data.

The !ord 6-%6 is often associated !ith volatile types of memory such as

5-%(memory modules) !here the information is lost after the po!er is s!itched off.

any other types of memory are -% as !ell including most types of -"and a type

of flash memorycalled&"-$,lash.

Scan design has been the backbone of design for testability (5,T) in industry for

about three decades because scan$based design can successfully obtain controllability and

observability for flip$flops. Serial Scan design has dominated the test architecture because

it is convenient to build. 4o!ever the serial scan design causes unnecessary s!itching

activity during testing !hich induce unnecessarily enormous po!er dissipation. The test

time also increases dramatically !ith the continuously increasing number of flip$flops in

large se#uential circuits even using multiple scan chain architecture. %n alternate to serial

scan architecture is -andom %ccess Scan (-%S). In -%S flip$flops !ork as addressable

memory elements in the test mode !hich is a similar fashion as random access memory

(-%). This approach reduces the time of setting and observing the flip$flop states but

re#uires a large overhead both in gates and test pins. 5espite of these dra!backs the -%S

!as paid attention by many researchers in these years. This paper takes a vie! of recently

published papers on -%S and reAuvenates the random access scan as a 5,T method that

simultaneously address three limitations of the traditional serial scan namely test data

volume test application time and test po!er.

% 5ecoder is used to address every ,,. The -%S allo!s reading or !riting of any

flip$flop using address bits !here MnN is the number of scanned flip$flops !hen the

address is applied the address decoder produces a scan enable signal to the corresponding

flip$flop needed to be placed !ith a data from the scan$in. In this techni#ue the scan

function is implemented as a random$access memory. 4ence at every given time only one,, is accessed !hile other ,,s retain their state. The architectures described in most

Sri Sunfower College O Engineering & Te!nolog" #$ge %)
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literatures mainly consists of a scan$in signal that is broadcasted to every ,, a test

control signal that is broadcasted to all ,,s and a uni#ue decoder signal from the decoder

to every ,,.

% more feasible decoder has been designed. The grid architecture sho!n in ,ig ;.P

is one efficient !ay to layout the decoders. 'ith a minimum of t!o layers of metal

routing the ro! !ires can be accommodated !ithin the channel in bet!een the cell ro!s

and the column !ires can be routed over the cell in the next metal layer. 4ence there !ill

be an increase of one track per channel (assuming m channels) and n tracks that are

routed on the next metal layer.

F)# 2.4:5esign "f -%S

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F)# 2.%: 5ecoder 5esign

In those t!o decoder structures suppose there are &ff flip$flops in the circuit. In

,igure there !ill be &ff $ address !ires to those & flip$flops. *ompared to ,igure

there are onlyNff

address !ires to &$ffs in ,igure ;. %lthough this structure need both

ro! decoder and column decoder !hen only one decoder is used in ,igure the

hard!are overhead reduced greatly using structure ;.

2.3 COMMON RAM MEMORY TYPES:

S-% $ Static random access memory uses multiple transistors typically four to

six for each memory cell but doesn:t have a capacitor in each cell. It is used primarily for

cache.

5-% $ 5ynamic random access memory has memory cells !ith a paired

transistor and capacitor re#uiring constant refreshing.

,0 5-% $ ,ast page mode dynamic random access memory !as the original

form of 5-%. It !aits through the entire process of locating a bit of data by column and

ro! and then reading the bit before it starts on the next bit. aximum transfer rate to L;

cache is approximately Q? megabytes per second.

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85" 5-% $ 8xtended data$out dynamic random access memory does not !ait

for all of the processing of the first bit before continuing to the next one. %s soon as the

address of the first bit is located 85" 5-% begins looking for the next bit. It is about

five percent faster than ,0. aximum transfer rate to L; cache is approximately ;?7

megabytes per second.

S5-% $ Synchronous dynamic random access memory takes advantage of the

burst mode concept to greatly improve performance. It does this by staying on the ro!

containing the re#uested bit and moving rapidly through the columns reading each bit as

it goes. The idea is that most of the time the data needed by the *01 !ill be in se#uence.

S5-% is about five percent faster than 85" -% and is the most common form in

desktops today. aximum transfer rate to L; cache is approximately P;> megabytes per

second.

-5-% $ -ambus dynamic random access memory is a radical departure from

the previous 5-% architecture. 5esigned by -ambus -5-% uses a -ambus in$line

memory module (-I) !hich is similar in si/e and pin configuration to a standard

5I. 'hat makes -5-% so different is its use of a special high$speed data bus

called the -ambus channel. -5-% memory chips !ork in parallel to achieve a data

rate of > 4/.

*redit *ard emory $ 0roprietary self$contained 5-% memory module that

plugs into a special slot for use in notebook computers.

0**I% emory *ard $ %nother self$contained 5-% module for notebooks. *ards of

this type are not proprietary and should !ork !ith any notebook computer !hose system

bus matches the memory card:s configuration.

,lash -% $ % generic term for the small amount of memory used by devices like

TVs V*-s and car radios to maintain custom information. 8ven !hen these items are

turned off they dra! a tiny amount of po!er to refresh the contents of their memory. This

is !hy every time the po!er flickersE the V*- blinks ;G. It:s also !hy you lose all

presets on your radio !hen your car battery diesR Kour computer has ,lash -% toremember things like hard disk settings $$ see for details.

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V-% Video -% also kno!n as multiport dynamic random access memory

(05-%) is a type of -% used specifically for video adaptersor


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they discharge. To do this the memory controller reads the memory and then !rites it

right back. This refresh operation happens automatically thousands of times per second.

This refresh operation is !here dynamic -% gets its name. 5ynamic -% has to be

dynamically refreshed all of the time or it forgets !hat it is holding. The do!nside of all

of this refreshing is that it takes time and slo!s do!n the memory.

emory cells are etched onto a silicon !afer in an array of columns (bit lines) and

ro!s (!ord lines). The intersection of a bit line and !ord line constitutes the address of

the memory cell.

5-% !orks by sending a charge through the appropriate column (*%S) to

activate the transistor at each bit in the column. 'hen !riting the ro! lines contain the

state the capacitor should take on. 'hen readingG the sense$amplifier determines the level

of charge in the capacitor. If it is more than P it reads it as a other!ise as a /ero. The

counter tracks the refresh se#uence based on !hich ro!s have been accessed in !hat

order. The length of time necessary to do all this is so short that it is expressed in

nanoseconds (billionths of a second). % memory chip rating of Qns means that it takes Q

nanoseconds to completely read and recharge each cell.

emory cells alone !ould be !orthless !ithout some !ay to get information in

and out of them. So the memory cells have a !hole support infrastructure of other

speciali/ed circuits.

These circuits perform functions such asG

Identifying each ro! (ro! address select or -%S) and column (column address

select or *%S) keeping track of the refresh se#uence (counter) reading and restoring the

signal from a cell (sense amplifier) telling a cell !hether it should take a charge or not

(!rite enable).

"ther functions of the memory controller include a series of tasks that include

identifying the type speed and amount of memory and checking for errors.

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Static -% uses a completely different technology. In static -% a form of flip$

flop holds each bit of memory (see 4o! =oolean @ates 'orkfor detail on flip$flops). %

flip$flop for a memory cell takes 7 or ? transistors along !ith some !iring but never has

to be refreshed. This makes static -% significantly faster than dynamic -%.

4o!ever because it has more parts a static memory cell takes a lot more space on a chip

than a dynamic memory cell. Therefore you get less memory per chip and that makes

static -% a lot more expensive.

So static -% is fast and expensive and dynamic -% is less expensive and

slo!er. Therefore static -% is used to create the *01:s speed$sensitive cache !hile

dynamic -% forms the larger system -% space.

In computer it uses 5-% (dynamic -%) for the main memory. I have also

heard of static -%. 'hat is the difference and !hy are there t!o kinds

Kour computer probably uses both static -% and dynamic -% at the same

time but it uses them for different reasons because of the cost difference bet!een the t!o

types. If you understand ho! dynamic -% and static -% chips !ork inside it is easy

to see !hy the cost difference is there and you can also understand the names.

5ynamic -% is the most common type of memory in use today. Inside a

dynamic -% chip each memory cell holds one bit of information and is made up of

t!o partsG a transistor and a capacitor. These are of course extremely small transistors

and capacitors so that millions of them can fit on a single memory chip. The capacitor

holds the bit of information $$ a or a (see 4o! =its and =ytes 'ork for information on

bits). The transistor acts as a s!itch that lets the control circuitry on the memory chip read

the capacitor or change its state.

% capacitor is like a small bucket that is able to store electrons. To store a in the

memory cell the bucket is filled !ith electrons. To store a it is emptied. The problem

!ith the capacitor:s bucket is that it has a leak. In a matter of a fe! milliseconds a full

bucket becomes empty. Therefore for dynamic memory to !ork either the *01 or thememory controller has to come along and recharge all of the capacitors holding a before

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they discharge. To do this the memory controller reads the memory and then !rites it

right back. This refresh operation happens automatically thousands of times per second.

This refresh operation is !here dynamic -% gets its name. 5ynamic -% has

to be dynamically refreshed all of the time or it forgets !hat it is holding. The do!nside

of all of this refreshing is that it takes time and slo!s do!n the memory.

Static -% uses a completely different technology. In static -% a form of flip$

flop holds each bit of memory (see 4o! =oolean @ates 'ork for detail on flip$flops). %

flip$flop for a memory cell takes 7 or ? transistors along !ith some !iring but never has

to be refreshed. This makes static -% significantly faster than dynamic -%.

4o!ever because it has more parts a static memory cell takes a lot more space on a chip

than a dynamic memory cell. Therefore you get less memory per chip and that makes

static -% a lot more expensive.

So static -% is fast and expensive and dynamic -% is less expensive and

slo!er. Therefore static -% is used to create the *01:s speed$sensitive cache !hile

dynamic -% forms the larger system -% space.

4o! ,lash emory 'orks

8lectronic memory comes in a variety of forms to serve a variety of purposes.

,lash memory is used for easy and fast information storage in such devices as digital

cameras and home video game consoles. It is used more as a hard drivethan as-%. In

fact ,lash memory is considered a solid state storage device. Solid state means that there

are no moving parts $$ everything is electronic instead of mechanical.

4ere are a fe! examples of ,lash memoryG

Kour computer:s =I"S chip

*ompact,lash (most often found in digital cameras)

Smart edia (most often found in digital cameras)

emory Stick (most often found in digital cameras)

0**I% Type I and Type II memory cards (used as solid$state disks in laptops)

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emory cards for video game consoles

,lash memory is a type of 880-" chip. It has a grid of columns and ro!s !ith

a cell that has t!o transistors at each intersection (,igure ). The t!o transistors are

separated from each other by a thin oxide layer. "ne of transistors is kno!n as a floating

gate and the other one is the control gate. The floating gate:s only link to the ro! or !ord

line is through the control gate. %s long as this link is in place the cell has a value of 66.

To change the value to a 66 re#uires a curious process called ,o!ler$&ordheimtunneling.

Tunnelling is used to alter the placement of electrons in the floating gate. %n electrical

charge usually $< volts is applied to the floating gate. The charge comes from the

column or bitline enters the floating gate and drains to a ground.

This charge causes the floating gate transistor to act like an electron gun. The

excited electrons are pushed through and trapped on other side of the thin oxide layer

giving it a negative charge. These negatively charged electrons act as a barrier bet!een

the control gate and the floating gate. % special device called a cell sensor monitors the

level of the charge passing through the floating gate. If the flo! through the gate is

greater than fifty percent of the charge it has a value of 66. 'hen the charge passing

through drops belo! the fifty percent thresholdG the value changes to 66. % blank

80-" has all of the gates fully open giving each cell a value of 66.

1p to a point adding -% (-andom %ccess emory) !ill normally cause your

computer to feel faster on certain types of operations. The reason !hy -% is important

because of an operating system component called the virtual memory manager.

'hen you run a program like a !ord processor or an internet bro!ser the

microprocessor in your computer pulls the executable file off the hard disk and loads it

into -%. In the case of a big program like icrosoft 'ord or 8xcel the 838 consumes

about P megabytes. The microprocessor also pulls in a number of shared 5LLs (5ynamic

Link Libraries) $ shared pieces of code used by multiple applications. The 5LLs might

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megabytes of -% space to run. "n my machine at any given time the follo!ing

applications runningG

% !ord processor

% spreadsheet

% 5"S prompt

%n email program

% dra!ing program

< or 7 bro!ser !indo!s

% ,ax program

% Telnet session

=esides all of those applications the operating system itself is taking up a good bit

of space. Those programs together might need to P megabytes or -% but my

computer only has ?7 megabytes of -% installed.

The extra space is created by the virtual memory manager. The V looks at

-% and finds sections of -% that are not currently needed. It puts these sections of

-% in a place called the s!ap file on the hard disk. ,or example even though I have

my email program open I haven:t looked at email in the last 7P minutes. So the V

moves all of the bytes making up the email program:s 838 5LLs and data out to the

hard disk. That is called s!apping out the program. The next time I click on the email

program the V !ill s!ap in all of its bytes from the hard disk and probably in the

process s!ap something else out. =ecause the hard disk is slo! relative to -% the act

of s!apping things in and out causes a noticeable delay.

If you have a very small amount of -% (say ? megabytes) then the V is

al!ays s!apping things in and out to get anything done. In that case your computer feels

like it is cra!ling. %s you add more -% you get to a point !here you only notice the

s!apping !hen you load a ne! program or change !indo!s. If you !ere to put ;P?

megabytes of -% in your computer the V !ould have plenty of room and you

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!ould never see it s!apping anything. That is as fast as things get. If you added more

-% it !ould have no effect.

Some applications (things like 0hotoshop many compilers most film editing and

animation packages etc.) needs tons of -% to do their Aob. If you run them on a

machine !ith too little -% they s!ap constantly and run very slo!ly. Kou can get a

huge speed boost by adding enough -% to eliminate the s!apping. 0rograms like these

may run to P times faster once they have enough -%.

2.4 RING COUNTER:

% !)# +9$e! is a type of counter composed of a circular shift register. The

output of the last shift register is fed to the input of the first register.

There are t!o types of ring countersG

%straight ring counteror Overbeck counterconnects the output of the last shift

register to the first shift register input and circulates a single one (or /ero) bit around the

ring. ,or example in a 7$register one$hotcounter !ith initial register values of the

repeating pattern isG ... . &ote that one of the registers must

be pre$loaded !ith a (or ) in order to operate properly.

% twisted ring counter(also calledJohnson counterorMoebius counter) connects

the complement of the output of the last shift register to its input and circulates a stream

of ones follo!ed by /eros around the ring. ,or example in a 7$register counter !ith

initial register values of the repeating pattern isG

... .

If the output of a shift register is fed back to the input. aringcounter results. The

data pattern contained !ithin the shift register !ill recirculate as long as clock pulses are

applied. ,or example the data pattern !ill repeat every four clock pulses in the figure

belo!. 4o!ever !e must load a data pattern. %ll :s or all 1:s doesn:t count.

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F)#2.': -ing *ounter 1sing Shift

-egister

'e make provisions for loading data into the parallel$inD serial$out shift register

configured as a ring counter belo!. %ny random pattern may be loaded. The most

generally useful pattern is a single 1.

F)# 2.,:-ing counter In 0arallel in Serial out Shift -egister

Loading binary 1 into the ring counter above prior to shifting yields a

vie!able pattern. The data pattern for a single stage repeats every four clock pulses in our

7$stage example. The !aveforms for all four stages look the same except for the one

clock time delay from one stage to the next. See figure belo!.

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F)# 2.:-ing *ounter 'ith S- ,lip$,lops

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The above block diagram sho!s the po!er controlled -ing counter. ,irst total

block is divided into t!o blocks. 8ach block is having one S- ,LI0,L"0 controller

S R 5$-1 5

3

3

T*0e 2.2:S- ,lip ,lop Truth Table

3. PROPOSED DELAY 6UFFERS

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F)# 3.1:=lock 5iagram ,or 0roposed 5elay =uffer

3.1 GATED DRIVER TREE:

F)# 3.2:@ated 5river Tree

@ated driver tree derived from the same clock gating signals of the blocks that

they drive. Thus in a #uad$tree clock distribution net!ork the MgateN signal of the gate

driver at the level (*+8 ) should be asserted !hen the active 58T Uip$Uop.

3.2 MODIFIED RING COUNTER:

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F)# 3.3:odified -ing *ounter

DET D90e e;#e $!)##e!e; )


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The uller C-eeme$ or uller *$gate is a commonly used asynchronous logic

component originally designed by 5avid 8. uller. It applies logical operations on the

inputs and has hysteresis. The output of the *$element reflects the inputs !hen the states

of all inputs match. The output then remains in this state until the inputs all transition to

the other state. This model can be extended to the %symmetric *$element!here some

inputs only effect the operation in one of the transitions (positive or negative). The figure

sho!s the gate$level and transistor$level implementations and symbol of the *$element.

4ere is the truth table for a ;$input c$gate. Yn denotes a 6no change6 condition.

F)# 3.4:*$ 8lement T*0e 3.1:Truth Table ,or *$8lement

The *$element stores its previous state !ith t!o cross$coupled inverters similar

to an S-%cell. "ne of the inverters is !eaker than the rest of the circuit so it can be

overpo!ered by thepull$up and pull$do!n net!orks.

If both inputs are then the pull$up net!ork changes the latch:s state and the *$element outputs a . If both inputs are then the pull$do!n net!ork changes the latch:s

state making the *$element output a . "ther!ise the input of the latch is not connected

to either Vdd or ground and so the !eak inverter (dra!n smaller in the diagram)

dominates and the latch outputs its previous state.

uller C-eeme$!as first used in the arithmetic logic unit (%L1) of the

ILLI%* IIsupercomputer proposed in 9P> and operational in 9?;.

4. DEVICE SPECIFICATIONS

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The above figure indicates the device specifications

POWER REPORT:

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E7ISTING:

POWER REPORTG

PROPOSED

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%. CONCLUSION AND FUTURE SCOPE

In this paper !e presented a lo!$po!er delay buffer architecture !hich adopts

several novel techni#ues to reduce po!er consumption. The ring counter !ith clock gated

by the *$elements can effectively eliminate the excessive data transition !ithout

increasing loading on the global clock signal. The gated$driver tree techni#ue used for theclock distribution net!orks can eliminate the po!er !asted on drivers that need not be

activated. %nother gated$demultiplexer tree and a gated$multiplexer tree are used for the

input and output driving circuitry to decrease the loading of the input and output data bus.

%ll gating signals are easily generated by a *$element taking inputs from some 58T flip$

flop outputs of the ring counter. easurement results indicate that the proposed

architecture consumes only about $ m *"S technology. ,urther simulations also demonstrate its advantages

in nanometer *"S technology.'e believe that !ith more experienced layout techni#ues

the cell si/e of the proposed delay buffer can be further reduced making it very useful in

all kinds of multimediaDcommunication signal processing I*s.

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B>C +. Xhang 1. =hattacharya X. *hen ,. 4am/aoglu 5. urray &.Vallepalli K.'ang

=. Xheng and . =ohr MS-% design on ?P$nm *"S technology !ith dynamic sleep

transistor for leakage reductionN IEEE J. Solid-State Circuits vol. 7 no. 7 pp. >9P

9 %pr.;P

APPENDI7 A

VHDL INTRODUCTION:

% design engineer in electronic industry uses hard!are description language to

keep pace !ith the productivity of the competitors. 'ith V45L !e can #uickly describe

and synthesi/e circuits of several thousand gates. In addition V45L provides the

capabilities described as follo!sG

0o!er and flexibility

V45L has po!erful language constructs !ith !hich to !rite succinct code

description of complex control logic. It also has multiple levels of design description for

controlling design implementation. It supports design libraries and creation of

reusable components. It provides 5esign hierarchies to create modular designs. It is one

language fort design and simulation.

5evice Independent design

V45L permits to create a design !ithout having to first choose a device foe

implementation. 'ith one design description !e can target many device architectures.

'ithout being familiar !ith it !e can optimi/e our design for resource or performance. It

permits multiple style of design description.

P!$*0))$":

V45L portability permits to simulate the same design description that !e have

synthesi/ed. Simulating a large design description before synthesi/ing can save

considerable time. %s V45L is a standard design description can be taken from one

simulator to another one synthesis tool to anotherE one platform to another$means

description can be used in multiple proAects.

=enchmarking capabilities

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5eviceindependent design and portability allo!s benchmarking a design using

different device architectures and different synthesis tool. 'e can take a complete design

description and synthesi/e it create logic for it evaluate the results and finally choose the

device$a *0L5 or an ,0@% that fits our re#uirements.

%SI* igration

The efficiency that V45L generates allo!s our product to hit the market #uickly

if it has been synthesi/ed on a *0L5 or ,0@%. 'hen production value reaches

appropriate levels V45L facilitates the development of application specific integrated

circuit (%SI*). Sometimes the exact code used !ith the 0L5 can be used !ith the %SI*

and because V45L is a !ell$defined language !e can be assured that out %SI* vendor

!ill deliver a device !ith expected functionality.

VHDL DESCRIPTION

In the search of a standard design and documentation for the Very 4igh Speed

Integrated *ircuits (V4SI*) program the 1nited States 5epartment of 5efense (5"5) in

9>sponsored a !orkshop on 4ard!are 5escription Languages (45L) at 'oods 4ole

assachusetts. In 9> and as an associated

=*!+()$e+$9!e 0;">. The declaration specifies its interface and is used by architecture

bodies of design entities at upper levels of hierarchy. The architecture body describes the

operation of a design entity by specifying its interconnection !ith other design entities

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?=/$!9+$9!* ;e/+!)by its behavior?=0e(*)!* ;e/+!) or by a mixture of

both. The V45L language groups sub programs or design entities by use of packages.

,or customi/ing generic descriptions of design entities +)#9!*$)/ are used.

V45L also supports libraries and contains constructs for accessing packages design

entities or configurations from various libraries.

E$)$)e/ *; A!+()$e+$9!e/:

E$)$" De+*!*$):

The 8&TITK declaration declares the name direction and data type of each port of

component.

Syntax: entity name is

0art ( )E

8nd nameG

A!+()$e+$9!e De+*!*$):

The %-*4IT8*T1-8 portion of a V45L description describes the behavior of the

component.

S"$*B: architecture BarchC Yentity name Z of Yentity nameZ is

=egin

The [begin2 that follo!s the signal declaration marks the start of the architecture

body. The follo!s a process declaration marked by the key!ord 0-"*8SS and an

ensuring =8@I&.

The 8&5 statement ending the architecture must be accompanies by the name of

the architecture !hich must match the name sho!n in the first of the architecture.

Se9e$)* P!+e//)#:

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Se#uential statements are statements that execute serially one after other. In

architecture for an entity all statement are concurrent in V45L the process statements

can exist in the architecture !here all statements are se#uential.

S"$*B:

Bprocess$labelGC process B(sensitivity list)C

0rocess$declarative$partE

=egin

0rocess$statement$partGGH

Se#uential statements\E

8nd process Bprocess$labelCE

% process statement has a declaration section and a statement part in declaration

section types variables constants subprograms etc. can be declared. Statements part

contains only se#uential statements !hich consist of *%S8 statements I, T48& 8LS8

statements L""0 statements etc.

Se/)$))$" )/$:

This list defines the signals that !ill cause the statements inside the process

statements to execute !henever one or more elements of the list change value i.e. list of

signal that the process is sensitive to. *hanges in the values of these signals !ill cause to

process to be invoked.

Se9e$)* S$*$eme$/:

Se#uential statements exist inside the boundaries of a process statement as !ell as

in sub programs. The se#uential statements that are generally used areG

IF

CASE

LOOP

ASSERT

WAITIF /$*$eme$

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S"$*B:

I, (condition) T48&

Se#uenceOofOstatementsE

B8LS8 condition T48&

Se#uence ofO statements E\

B8LS8

Se#uenceOofOstatementsEC

8&5 I,E

The I, statement start !ith the key!ord I, and ends !ith the key!ords 8&5 I,.

There are also t!o optional clausesG they are the 8LS8I, clause and the 8LS8

clause. The conditional construct in all cases is a =oolean expression. This is an

expression that evaluates to either true or false. 'henever the condition evaluates to a

true value the se#uence of statements follo!ing are executed. I, condition is true or false

the se#uence of statements for the 8LS8 clause is executed if one exits. The I, statement

can have multiple 8LS8 I, statements parts only one 8LS8 statement part bet!een each

statement part can exist more than one se#uential statement.

CASE S$*$eme$:

The *%S8 statement is used !henever a single expression value can be used

to select bet!een a numbers of actions.

S"$*BG

*%S8 expression is

*aseOstatemantOalternativeE

]*aseOstatemantOalternative E\

8&5 *%S8E

A$e!*$)e:

'48& choiceHZ

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'here choiceGGH

simpleOexpression

discreteOrange

elementOsimple Oname

"T48-S

% *%S8 statement consists of the keyboard *%S8 follo!ed by an expression and

the keyboard is. The expression !ill either return a value that matches one of the choices

in a '48& statement part or a match an others clause. %fter these statements are

executed control is transferred to the statements follo!ing the 8&5 *%S8 clause

The *%S8 statement !ill execute the proper statement depending on the value of

input )/$!9+$).If the value of )/$!9+$)is one of the choices listed in the '48&

clause is executed.

LOOP STATEMENT:

The L""0 statement is used !henever an operation needs to be operated. L""0

statements are used !hen po!erful iteration capability is needed to implement a model.

S"$*B:

BLoopOlabelGCBiterationOschemeCLoop


8&5 L""0 Bloop$labelCE

'here iterationOschemeGG H

'4IL8 condition

,or loopOparametrOspecificationE

%nd LoopOparameterOspecificationGGH

Identifier I& discreteOrange

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The loop statement has optional label !hich can be used to identify the L""0

statement has an optional )$e!*$) /+(eme that determines !hich kind of L""0

statement is being used. The )$e!*$) /+(eme includes t!o types of L""0 statements a

['4IL8 condition2 L""0 statement and a [,"- identifier I& discrete range2 statement.

The ,"- loop !ill loop as many times as specified in the discrete range unless the loop

is excited from the '4IL8 condition L""0 statement !ill loop as long as the condition

expression is T-18.

In some languages the loop index can be assigned value inside its loop to change

its value. V45L does not allo! any assignment to the index. This also precludes the loop

index existing as the return value of a function or an out in out parameter of the

procedure.

NE7T S$*$eme$:

There are cases !hen it is necessary to stop executing the statements inside

the loop for this iteration and go to the next iteration. V45L includes a construct that !ill

accomplish this. The &83T statement allo!s the designer to stop processing this iteration

and skip to the successor. 'hen the &83T statement is executed processing of the model

stops at the current point and is transferred to the beginning of the loop statement.

8xecution !ill begin !ith the first statement in the loop but the loop variable !ill be

incremented to the next iteration value. If iteration limit has been reached processing !ill

stop else the execution !ill continue.

E7IT S$*$eme$:

5uring the execution of the loop statement it may be necessary to Aump

out of the loop. This can occur because a significant error has occurred during the

execution of the model or all if he processing has already finished early. The V45L 83IT

statement allo!s the designer to exit or Aump out of a L""0 statement currently in

execution. The 83IT statement causes execution of halt at the location of the 83IT

statement. 8xecution !ill continue at the follo!ing the L""0 statement.

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The exit statement has three basic types of operations. The first involves an 83IT

statement !ithout a loop label or a '48& condition. If these conditions are true then

the 83IT statement !ill behave as follo!sG the 83IT statement !ill exit from the most

current L""0 statement encounters. If an exit statement is inside L""0 that is nested

inside a L""0 statement the 83IT statement !ill exit only the inner L""0 statement.

8xecution !ill still remain in the outer L""0 statement.

ASSERT S$*$eme$:

The %SS8-T statement is a very useful statement for reporting textual

strings to the designer. The %SS8-T statement checks the value of =oolean expression

for true or false. If the value is true the statement does nothing. If the value is false the

%SS8-T statement !ill output a user$defined string to the standard output of the

terminal.

The designer can also specify a severity level !ith !hich the text string.

The four levels are in increasing level of severityG $e@ *!)#@ e!!! and *)9!e. The

severity level allo!s the designer the capability to classify messages into proper

categories.

The $e category is full for relaying information to the user about !hat is

currently happening in the model. %ssertions of category *!)#can be used to alert the

designer of conditions that can cause erroneous behavior. %ssertions of severity level

error are used to alert the designer of the conditions that !ill cause the model to !ork

incorrectly or not !ork at all. %ssertions of severity level failure are used to alert the

designer of the conditions !ithin the model that have disastrous effects.

The %SS8-T statement is currently ignored by synthesis tools. Since the

%SSS8-T statement is mainly for exception handling !hile !riting a model no hard!are

is built.

S"$*B: %SS8-T conditionB-80"-T expressionC

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BS8V8-ITK expressionCE

The key!ord [%SS8-T2 is follo!ed by a =oolean$valued expression called a

+;)$). The condition determines !hether the text expression specified by the

-80"-T clause is output or not. If false the text expression is outputE the text expression

is not output .

The -80"-T and S8V8-ITK clauses are optional -80"-T clause allo!s the

designer the capability to specify the value of a text expression to output. The S8V8-ITK

clause allo!s the designer to specify the severity level of the %SS8-T statement. If the

report clause is not specified the default value for the %SS8-T statement is *//e!$)

)*$). if the severity clause is not specified the default value is e!!r.

WAIT S$*$eme$:

The '%IT statement allo!s the design the capability of suspending the

execution of process of subprogram. The conditions for resuming execution of the

suspended process or subprogram can be specified by three different means. These areG

'%IT on signal changes

'%IT 1&TIL an expression is true

'%IT ,"- a specific amount of time

'%IT statement can be used for number of different purposes. The most

common use is for specifying clock inputs to synthesi/e tools Dthe '%IT statement

specifies the clock for a process statement that is read by synthesis tool to create

se#uential logic such as register and flip$flops. "ther uses of '%IT are to delay process

execution for an amount of tome or to modify the sensitivity list of the process

dynamically.

WAIT ON /)#*:

The '%IT "& signal clause specifies a list of one for more signals upon !hich the

'%IT statement !ill !aits for events.

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WAIT UNTIL eB

The '%IT 1&TIL =oolean$expression clause !ill suspend execution of the process

until the expression returns a value of true.

'%IT ,"- time$expression

The '%IT 1&TIL $)me-eB

for the specified by the time expression. %fter the time specified in the time expression

has elapsed execution !ill continue on the statement follo!ing the '%IT statement.

M9$)Subprograms

In many programming languages subprograms are used to simplify

coding modularity and readability of descriptions. V45L uses subprograms for these

applications for these applications as !ell as for those that are more specific to hard!are

descriptions. -egardless of the application behavior soft!arelike constructs are allo!ed

in subprograms. V45L allo!s t!o forms of subprograms functions and procedures.

,unctions return value cannot alter the values of the parameters. % procedure on the other

hand is used as a statement and can after the values of the parameters.

,unctions can be declared in V45L by specifyingG

. The name of the function

;. The input parameters if any


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;. The input and output parameters if any


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^,ile declaration

^%lias declaration

^*omponent declaration

^%ttribute declaration a user$defined attribute

^5isconnection specification

^1se clause

%ll of the items declared in the package declaration section are visible to any

design that uses the package !ith a 1S8 clause. The interface to a package consists of

any subprograms or deferred constants declared in the package declaration. The

subprogram and deferred constant must have a corresponding subprogram body and

deferred constants value in the package body or an error !ill result.

D*$* O0e+$/:

% data obAects holds a value of a specified type. 8very data obAects belong to one of

the follo!ing three classesG

C/$*$/:

The obAect of a constant class can hold a single value of a given type. This value is

assigned before simulation and cannot be changed during the course of simulation.

S"$*B:constant identifierG typeG HvalueE

V*!)*0e/:

%n obAect variable class can also hold a single value of a given type. 4o!ever

different values can be assigned to the obAect at different times. Variable can be declared

only inside a process.

S"$*BG variable identifierG typeBGHvalueCE

S)#*/:

%n obAect of the signal class has a past history of values a current value and a set

of future values. Signal obAects are typically used to model !ires and flip$flops !hich

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variables and constants are used to model the behavior of the circuit. Signals cannot be

declared in a process statement.

S"$*BGsyntax identifierG type BG HvalueCE

F)e/:

,iles contain values of a specified type. 'e use files to read in stimulus and to !rite

data !hen using test benches.

D*$* $"


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I& the 3ilinx soft!are !e can do simulation and synthesis .The entire processor

!ill be implemented using the 3ilinx ,0@%s so you !on:t have to spend time !iring up

that part of the circuit. Kou !ill ho!ever have to !ire the s!itches and lights that are

used to control the processor and have to !ire the 3ilinx part itself to the s!itches and

lights but this shouldn:t be too bad. Kou !ill also use the backplane bus in your lab kit so

that the Triscuit !ill be built on t!o boardsG one for the 3ilinx chip and one for the

s!itches and lights.

The 45L 8ditor feature provides extensive edit and search capabilities !ith

language$specific color coding of key!ords as !ell as integrated on$line syntax checking

to scan V45L code for errors. The Language %ssistant feature speeds design entry by

providing a lookup list of typical language constructs and commonly used synthesis

modules like counters accumulators and adders.

Documents

7. Modified Project