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NPL Management Ltd - Internal
Innovative Navigation using new GNSS SIGnals with Hybridised Technologies
A Digitally Configurable
Receiver for
Multi-Constellation GNSS
www.insight-gnss.org 12th July 2012, Teddington NPL Management Ltd - Internal
Westminster Contributors
• Prof. Izzet Kale
• Dr. Yacine Adane
• Dr. Alper Ucar
• Mr. Burak Bardak
• Mr. Ilker Yavuz
www.insight-gnss.org 12th July 2012, Teddington NPL Management Ltd - Internal
Overview
• Introduction
– Overview of a Typical GNSS Receiver
– Next Generation GNSS
– Sub-Nyquist Sampling (Subsampling) Receivers
• A Digitally Configurable Receiver (DCR) for Multi-
Constellation GNSS
– Dual RF Front-end Architecture
– Digital Baseband Processor
• Conclusions
• Future Work
www.insight-gnss.org 12th July 2012, Teddington NPL Management Ltd - Internal
A Typical GNSS Receiver
Antenna
ADC
DSP
Position
(x,y,z)Acquisition Tracking Demodulation
Range
ProcessingRF Front-
end
• Received signal is below the thermal noise floor
– –128.5dBm for GPS L1 C/A
– SNR in 2.046MHz bandwidth @2900K is -17.63dB
• The RF front-end down-converts the signals to an IF
– Heterodyne RF Front-end (Dual or Triple Down-conversion)
– Low-IF RF Front-end (Single down-conversion)
– Sub-Nyquist Sampling (Subsampling) RF Front-end (Down-
conversion via intentional aliasing)
• A/D conversion at IF (1 to 3 bits) From RF
Front-endS/H To DSP
Quantizer
~~~AAF
n-bit
www.insight-gnss.org 12th July 2012, Teddington NPL Management Ltd - Internal
Next Generation GNSS
• Faster chipping rates lead to a sharper
main peak in the auto-correlation
function
– Better range precision
– Better multipath performance
• Longer codes have narrower frequency
bin spacing
– Reduced vulnerability to narrowband
interference since the amount of power
per frequency bin is reduced
• Signals from multiple frequencies
enable ionosphere estimation
– by measuring the delay between EM
waves
300–300
Correlation
Distance [m]0
30–30Distance [m]
0
multipath
component
multipath
component
GPS L1 C/A
GPS L5
main
peak
main
peak
Correlation
ARNS
1575,42 MHz1191,795 MHz 1278,75 MHz
1575,42 MHz1227,6 MHz1176,45 MHz
GPS (Bloc III)
Galileo
Galileo E5a Galileo E5b
Galileo E5
GPS L5
Galileo E6
GPS L2
Galileo L1
GPS L1
ARNS
www.insight-gnss.org 12th July 2012, Teddington NPL Management Ltd - Internal
Subsampling Receivers
• ADC should be placed as near to the
antenna as possible in a Digitally
Configured Radio (DCR)
• Frequency translation via intentional
aliasing
– Eliminating the need for analogue mixers
– Shifting the IF stage into the digital
domain, hence eliminating the need for IF
analogue filters
– Minimizing the signal distortion caused by
analogue impairments
– Key Components
• Anti-aliasing RF Filter(s)
• Low Jitter ADC
GPS L1 Receiver IC, Gramegna et.al., IEEE Journal of Solid-state
Circuits, vol. 41, no. 3, 2006
~~~ ADC DSP
Tunable
BPF
Wideband
Antenna
The Concept of SDR
G
Gain
f0
Magnitude
fUfL
Df
FrequencyfS
www.insight-gnss.org 12th July 2012, Teddington NPL Management Ltd - Internal
A Digitally Configurable Receiver
for Multi-Constellation GNSS
www.insight-gnss.org 12th July 2012, Teddington NPL Management Ltd - Internal
Digitally Configurable Receiver
• Requirements
– Dual-channel RF front-end for left/right-Hand
polarized antennas
– Fast update rate (down to 500 ms)
– Multi-constellation
• GPS L1/L2C (CDMA)
• GLONASS G1/G2 (FDMA)
• GALILEO E1 can be easily added
– Correlation outputs (Early/Prompt/Late) at each
code epoch (1 to 10 ms)
– Programmable correlator spacing and loop filter
bandwidth
www.insight-gnss.org 12th July 2012, Teddington NPL Management Ltd - Internal
Digitally Configurable Receiver
• Two separate RF channels synchronised with a single
master atomic (Cs/Rb) clocks
• Both RF channels are connected to a high-speed dual-
channel ADC, which digitizes and down-converts each
of the incoming RF into an IF
• Digital signal processing is performed with a HW/SW
co-design approach (FPGA/Linux Workstation)
Dual Multi-
Frequency
RF Frond-End
Horizontal
Polarization
Antenna
Vertical
Polarization
Antenna
GPS L1/L2C,
Glonass G1/G2
Galileo E1
Virtex 5
FPGA4-bit
Linux
Workstation
- Data Capture
- Tracking Loops
PCIe
- FFT Acquisition
- Code/Carrier Discriminators
- User Interface
- RINEX File
Du
al-C
ha
nn
el
ADC
4Gbit/s
LO
Cs/Rb Oscillator 10MHz
-115dBc/Hz@100Hz
Ho
rizo
nta
l
Ch
an
ne
l
Ve
rtica
l
Ch
an
ne
l
www.insight-gnss.org 12th July 2012, Teddington NPL Management Ltd - Internal
Dual Channel RF Front-End
www.insight-gnss.org 12th July 2012, Teddington NPL Management Ltd - Internal
Anti Aliasing RF Filters
• Home-made micro-strip filters
– High flexibility, low cost, good rejection, flat group delay,
low insertion loss, compact size
• Dually-diplexed folded resonators
• Good performance when used with cascaded
amplifiers
1.0 1.2 1.4 1.6 1.80.8 2.0
-60
-40
-20
0
20
-80
40
freq, GHz
dB
(S(2
,1))
Readout
m2
Readout
m3
Readout
m5
Readout
m6
m2freq=dB(S(2,1))=20.333
1.187GHzm3freq=dB(S(2,1))=20.365
1.281GHz
m5freq=dB(S(2,1))=19.470
1.574GHzm6freq=dB(S(2,1))=19.505
1.633GHz
Measured Filter Response
Dual-band Micro-strip RF Filters
www.insight-gnss.org 12th July 2012, Teddington NPL Management Ltd - Internal
Low-Jitter High Speed Clock
• Ability to generate a master
clock from 10 MHz to 500
MHz
• Chip Scale Atomic Clock
(CSAC) oscillator as a
reference ensures a superior
stability
• @250 MHz the clock jitter is
σc=150 fs
Phase Noise Plot
www.insight-gnss.org 12th July 2012, Teddington NPL Management Ltd - Internal
Low Jitter High Speed Clock
• Precision clock
conditioner that provides
low-noise jitter cleaning,
clock multiplication
• Two cascaded PLL
– PLL1 provides a low-noise
jitter cleaner function
– PLL2 performs the clock
generation
www.insight-gnss.org 12th July 2012, Teddington NPL Management Ltd - Internal
High Speed Dual ADC
• Sampling rate range up to 500
MS/s
• RF input bandwidth up to 1.6
GHz
• 1:2 demultiplexer feeds two
LVDS buses
• Time-Interleaved
– The output data rate
reduced in each bus to half
the sampling rate.
• Aperture Jitter 0.4 ps
www.insight-gnss.org 12th July 2012, Teddington NPL Management Ltd - Internal
Dual-Channel RF Front-End
Dual Channel RF Frond-end PCB RF Frond-end Connected to the Clock Board and the Virtex-5 FPGA
Channel 0
Channel 1
www.insight-gnss.org 12th July 2012, Teddington NPL Management Ltd - Internal
The Baseband Processor
www.insight-gnss.org 12th July 2012, Teddington NPL Management Ltd - Internal
The Baseband Processor
• Hardware/Software Co-design Approach
– Correlations calculated on the FPGA to enable
real-time satellite tracking
– FPGA connected to Linux workstation via high-
speed PCIe
– Post-processing done
on Linux workstation Virtex-5 FPGA
RF Front-End
Dual Multi-
Frequency
RF Frond-End
Horizontal
Polarization
Antenna
Vertical
Polarization
Antenna
GPS L1/L2C,
Glonass G1/G2
Galileo E1
Virtex 5
FPGA4-bit
Linux
Workstation
- Data Capture
- Tracking Loops
PCIe
- FFT Acquisition
- Code/Carrier Discriminators
- User Interface
- RINEX File
Du
al-C
ha
nn
el
ADC
4Gbit/s
LO
Cs/Rb Oscillator 10MHz
-115dBc/Hz@100Hz
Ho
rizo
nta
l
Ch
an
ne
l
Ve
rtica
l
Ch
an
ne
l
www.insight-gnss.org 12th July 2012, Teddington NPL Management Ltd - Internal
HW/SW Design Flow
Digital Front-
end
FFT Acquisition
ADC
Tracking
Processor
Tracking Co-
Processor
PLL
FPGA
PCIe
Measurements
PC
FPGA
PC
PC
1
Acquire
2
Carrier Pull-in
3
Track
4
RINEX & Other
Outputs
# of Acquired
Satellites > 4
– Equivalent # of Sequential
Correlations via IFFT
– Doppler Search Interval
(Default: 500Hz)
– Acquisition Threshold
– Carrier Frequency Resolution
(Default: 10Hz)
– Position Update Interval
– Correlator Spacing
– Code/Carrier Loop Filter Bandwidth
– Discriminator Type
C/N0 > 30dB-Hz
# of Acquired Satellites < 4
Simplified Signal Processing Flowchart
www.insight-gnss.org 12th July 2012, Teddington NPL Management Ltd - Internal
The Digital Front-End
• Delivers signals of interest from the ADC to the
baseband processor with minimum aliasing and a
low sampling rate
235 240 245 2500
20
40
60
80
100
120
140
X: 241
Y: 22.98
Sampling Frequency [MHz]
Resultin
g I
F [
MH
z]
Glonass G2
Glonass G1
GPS L1
GPS L2C
41.53
84.23
23.34
G1
L1
110.52
L2C
G2
Ladder Diagram for Signals of Interest to Find the Minimum Sub-Nyquist Sampling Rate
1.15 1.2 1.25 1.3 1.35 1.4 1.45 1.5 1.55 1.6-120
-100
-80
-60
-40
-20
0
20
Frequency (GHz)
Pow
er/
frequ
ency (
dB
/Hz)
Welch Power Spectral Density Estimate
L5/E5aE5b
L2
G2
E6
L1
G1
L-Band Spectrum after RF Filters (Simulated)
www.insight-gnss.org 12th July 2012, Teddington NPL Management Ltd - Internal
The Digital Front-End (2)
24.08MS/s (GLONASS G2)
Bandpass
Filter GPS L1_1
Fro
m A
DC
12
0.4
1M
S/s
Bandpass
Filter GPS L1_2
Bandpass
Filter GPS L2_1
Bandpass
Filter GPS L2_1
Bandpass
Filter GLONASS
G1_1
Bandpass
Filter GLONASS
G1_2
Bandpass
Filter GLONASS
G2_1
Bandpass
Filter GLONASS
G2_2
D2S
4
4DI_p
DI_n
DQ_p
DQ_n
Differential Single-ended
120.41MS/s
MUX4
240.83MS/s
18
18
18
18
8
8
10
10
MUXShift
Register 64
44
CLK
MUX
CLK
MUX
13
.37
MS
/s3
0.1
0M
S/s
24
.08M
S/s
DCM
13.37MS/s (GPS L1/L2C)
30.10MS/s (GLONASS G1)
Fro
m P
LL
D2S
FIFO
PCIe
0 20 40 60 80 100 120-130
-120
-110
-100
-90
-80
-70
-60
-50
Frequency (MHz)
Pow
er/
frequ
ency
(dB
/Hz)
Welch Power Spectral Density Estimate
L2G2
L1
G1
Spectrum after Sub-Nyquist Sampling at 240.82MS/s (Simulated)
www.insight-gnss.org 12th July 2012, Teddington NPL Management Ltd - Internal
Signal Acquisition
Acquired Signal (PRN01)
200400
600800
1000
3.555
3.56
3.565
3.57
2
4
6
8
x 105
Code Offset [chips]
SVN 1
Frequency [MHz]
Magnitude
• 2D search (code offset/carrier frequency bins) to
initialize the code generator and carrier NCO in the
tracking channels
– Time-domain search (time consuming)
– Frequency-domain search (fast/computationally
expensive/large Silicon area for eventual integration)
– DCR cold start acquisition (7 to 30s)
– DCR warm start acquisition (3 to 12s)
Frequency-domain acquisition
0
p / 2
From
ADC NCO | . |
2 Correlation
Values
I
Q
FFT
DFT
Code
Generator
Complex
Conjugate
IFFT
500 Hz
increments
DFT
Code Phase Resolution : 1 Sample
:
www.insight-gnss.org 12th July 2012, Teddington NPL Management Ltd - Internal
Signal Tracking (1)
4
Shift
Register
P
Accumulate
& Dump
Accumulate
& Dump
Accumulate
& Dump
Accumulate
& Dump
Accumulate
& Dump
Accumulate
& Dump
FIFO
QE
IL
IP
IE
QP
QL
Code
Generator
Code NCO
Carrier NCO
COSSIN
X
X
X
X
IE
X
X
IP
E
L
X IL
QL
X QE
QP
I
Q
PC
Ie C
ore
4 8
1 1
8
8
8
8
21
21
CarrierPhase
Counter
4
Code Phase
Counter
Offset
Register
Epoch
Counter
11
11
21
21
21
21
1
32
21
From Digital
Front-End
To Linux
Workstation8
Enable
Mixer
Mixer
1
DUMP
TIC
Position Update Rate
Programmable
Correlator Spacing
Single Tracking Channel (Virtex-5 FPGA)
Code Loop
Discriminator
RAMPC
Ie
Co
ntr
olle
r
Code
Loop
FilterS
Code NCO Bias
Carrier Loop
Discriminator
Carrier
Loop
FilterS
Carrier NCO Bias
Programmable
Tracking Coprocessor (Linux Workstation)
•PCIe Controller •Code/Carrier Filter •Code/Carrier Discriminator •Pseudorange Calculator •RINEX writer
www.insight-gnss.org 12th July 2012, Teddington NPL Management Ltd - Internal
Signal Tracking (3)
Constellation 0Constellation 0
Constellation 0
Tracking
Processor 0TIC
PC
Tracking
Processor 1
Tracking
Processor 11
I & Q [21]
Carrier Register [32]
Code Register [21]
PC
PC
Epoch Register [21]
PC
I & Q [32]
Carrier Register [32]
Code Register [21]
Epoch Register [21]
PC
I & Q [21]
Carrier Register [32]
Code Register [21]
Epoch Register [21]
GPS L1
GPS L2C
GLONASS G1
GLONASS G2
Virtex-5 FPGA Floorplan
Tracking Channels
FIFOs
PCIe
Core
Filters
Slice Registers
Slice LUTs
Memory IOBs
Baseband* 25% 15% 10% N/A
PCIe Core 15% 10% 9% N/A
Total 35% 25% 19% 11%
Baseband Processor for 4 constellations
*Device Utilization for 12 Tracking Channels
www.insight-gnss.org 12th July 2012, Teddington NPL Management Ltd - Internal
Signal Tracking Results
SV C/N0
[dB-Hz]Elevation[Degrees]
13 47.63 57.1
02 46.60 49.6
10 47.01 87.2
07 44.58 56.4
04 45.17 41.3
05 42.34 28.7
08 40.90 30.0
16 39.98 14.6
29 39.40 9.0
30 37.53 7.3
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
-2000
-1000
0
1000
2000
Time (s)
PRN14
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
-4000
-2000
0
2000
4000PRN01
Time (s)
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9-4000
-2000
0
2000
4000
PRN11
Time (s)
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9-4000
-2000
0
2000
4000PRN19
Time (s)
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
-2000
0
2000
PRN32
Time (s)
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
-2000
-1000
0
1000
2000
PRN28
Time (s)
Decoded Navigation Bits
• Good C/N0 performance • Successful Tracking of Satellites with an Elevation Angle down to 70
Navigation Solution
www.insight-gnss.org 12th July 2012, Teddington NPL Management Ltd - Internal
Conclusions and Future Work
• Shown good tracking performance with high C/N0
– Tracking channels driven by an atomic clock
• Tailor-made for cutting-edge research applications
– Correlator outputs available at each epoch
– Programmable correlator spacing, loop filter bandwidth to
change the parameters at will
– Two-highly synchronized receivers
• Acquisition implemented on the FPGA with novel
reduced-complexity FFT approach (Poster session)
• Fully-integrated Receiver (RF+DSP) on CMOS IC to
follow
NPL Management Ltd - Internal
Thanks for attention!
Questions?