A Low-Power Fully-Differential CMOS OperationalTransconductance Amplifier for A/D Converters

Andrea Gerosa and David A. Sobel

ABSTRACTThe design of a fully differential CMOS

transconductance amplifier is presented in this paper.This amplifier is to be used in the first stage of a 13-bitpipelined A/D converter, and was designed to meet thenecessary specifications at a minimum level of powerconsumption. The amplifier presented below was basedon a two-stage design of a telescopic cascode input stagefollowed by a common-source output gain stage. Theamplifier was compensated with a variation of Millercompensation in order to achieve maximum bandwidth.The amplifier designed meets all performancespecifications and consumes less than 2 mW of power.

1 INTRODUCTIONPipelined analog-to-digital converters (A/D’s)

convert an analog input to a high-resolution digitaloutput (i.e. high number of output bits) through apipelined cascade of lower-resolution A/D converters,each with a resolution of typically 1 to 1.5 bits. Eachpipeline stage calculates the digital output for its input,and then passes on its analog error residue to the nextstage for a similar conversion. In order to ease theconversion process for later stages, an inter-stage gainof two is applied to the error residue to keep this signalat a reasonable magnitude.

Hence, aside from the actual comparator, pipelinedA/D’s also require a circuit that can provide an addingfunction and accurate gain. Both of these functions canbe provided by an operational transconductanceamplifier (OTA) connected in a switched-capacitor(SC) gain configuration. It is worth noting two factsabout the performance requirements for an OTA withina pipelined A/D converter. First, the circuitspecifications are determined by the overallperformance metrics of the entire A/D converter.Therefore, pipelined A/D converters with high bitresolutions require more precise analog circuits thanthose converters with low-bit resolutions. Also, thesecircuit requirements are relaxed as the signalpropagates down the pipeline. Hence, the performancespecifications are most rigorous for the OTA in the firstpipeline stage of the converter and scaling techniquescan be used in subsequent stages of the A/D in order tominimize power dissipation [Cho95].

In this project, we designed a fully-differential OTAto be used as the first stage of a 13-bit pipelined A/Dconverter. The specifications to be met can be seen inTable 1, and the circuit has to be robust over processvariations.

Supply 3VDynamic Range > 80 dBOpen-loop gain > 10,000Settling Time < 100nsAccuracy > 0.01%Power Minimum

Table 1: OTA specifications

The rest of this paper proceeds as follows: Section 2includes a discussion of circuit topology considerationsfor low power. Section 3 outlines the approach we tookto meeting the required specifications at a minimumpower level. Section 4 presents our two-stage OTAdesign and the simulation results. Section 5 concludesthis paper with a discussion of the practicality of ourdesign and its effectiveness at achieving a low-powersolution.

2 TOPOLOGY CONSIDERATIONS FORLOW POWER

An a priori design decision was the choice of a classA amplifier. While this choice does increase powerdissipation, the tradeoff of much simpler circuit designwas viewed as a net gain. With this decision in mind,the circuit specifications present the followingconsiderations in choosing an OTA topology.

2.1 Transistor network topologyWith the process parameters given, an open-loop

gain of 10,000 is on the order of (gmro)3. Therefore, at

least 3 gain devices must be placed within the signalpath in order to achieve the necessary gain. Thefollowing topologies are candidates for such aspecification:

• A single-stage “regulated” cascode OTA• A cascaded three-stage common-source OTA• A two-stage folded cascode/common-source

OTA

2

• A two-stage telescopic cascode/common-source OTA

The high dynamic range requirement of the circuitis significantly easier to meet with a larger outputsignal swing. Therefore, the regulated cascode, with itscascoded devices on its output node, was deemed to bea less favorable topology.

The three-stage common source cascade presentsthree main disadvantages to its implementation. First,its nested Miller compensation will narrow-band thesystem, as each level of compensation tends to reducethe bandwidth by a factor of two. Second, as the gainof the first stage is only on the order (gmro) noisecontributions from the second stage will beappreciable. Finally, as this OTA is to be fullydifferential, a common-mode feedback circuit isnecessary for all topologies. It seems feasible that asingle CMFB circuit may not be enough to keep allthree stages in saturation [Flores96].

The tradeoffs between the other two topologies—folded-cascode/common-source and telescopic-cascode/common-source—are more subtle. Before thetradeoffs are considered, we should first introduce theprimary characteristics desired for a two-stage OTA forminimum power: [Feldman97]

1) minimum number of current legs,2) minimum number of devices contributing

significant thermal noise, and3) an all NMOS signal path

A folded-cascode stage has extra current legs whichdissipate more static power than a similar telescopicstage. For a given settling constraint and a fixedcompensation technique, this extra current leg will ineffect double the power dissipated in the first stage ofthe folded cascode in comparison to a similartelescopic stage. Therefore, by criterion (1) presentedabove, a telescopic stage is favorable to a folded stage.

A folded-cascode stage also has more deviceswhich contribute significant input-referred thermalnoise to the signal. The extra current source transistorscomprising the “fold” add directly to the noise factor ofthe input stage. While the Vdsat’s of these transistor canbe increased to minimize the added noise, the extranoise inserted requires a commensurate increase inpower dissipation for a fixed dynamic rangespecification. Therefore, according to criterion (2)listed above, the telescopic stage is preferable to thefolded stage.

With careful biasing, however, an OTA with afolded-cascode first stage can consist of an all-NMOSsignal path while still achieving reasonable outputswing [Flores96]. An OTA with a telescopic first stagecannot achieve such a signal path without either

severely degrading output swing or introducing acomplicated dynamic level-shifting scheme[Feldman97]. An OTA with a telescopic first stagewould most likely have a PMOS first stage and anNMOS second stage in order to create a more stabletopology. Therefore, for a given settling constraint anda fixed compensation technique, an OTA with a PMOSfirst stage would consume roughly (µn/µp) more powerthan an OTA with an NMOS first stage. For theprocess parameters given, this ratio roughly equals 2.5.

Therefore, it can be seen from a power perspective,the two topologies are roughly equivalent; the powerincrease for the folded first-stage demanded bycriterion (1) and (2) are roughly balanced by the powerincrease demanded by criterion (3) for the telescopicfirst-stage. As there is no clear power advantage tochoosing one topology over another, we decided on theOTA with the telescopic cascode as it seemed easier toimplement.

It is worth noting that two main advantages of thefolded first-stage unrelated to power consumption arenot relevant in this circuit. Namely, the folded-firststage allows for a greater input common-mode rangeand a greater output swing. As the required inputcommon-mode range of the circuit is not specified, andcommon-mode feedback is employed, the common-mode input range of the telescopic first-stage is morethan sufficient. Also, the gain of the second stage of theOTA will be high enough such that the limited outputrange of the telescopic first stage has no effect on theoverall output swing of the OTA.

2.2 Compensation TopologyAs the OTA topology selected is multi-stage a

compensation technique is necessary. As described inappendix C, we sought to design an OTA with 70degrees phase margin at the unity-gain frequency of theloop configuration. Standard Miller compensation canbe employed for a simple solution, but thiscompensation technique introduces a zero is the righthalf-plane. In order to increase phase margin,techniques to push that zero out to infinity wereexplored. Putting a resistor in the feedback path is onepossible solution. In order to achieve a reasonablysized resistance without consuming an excessiveamount of chip area, transistors operating in triodewould be needed to be placed in the compensationfeedback path. This can be troublesome in low-voltagetopologies, as it can be difficult to maintain a linearresistance in a triode device without a very high gatevoltage. Furthermore, the extra devices were deemedan unnecessarily complex addition and alternatesolutions were looked into. Unilateral feedback couldalso be employed, but it has been shown that such atechnique not only adds to total static powerconsumption, but it also can limit slew rate and hence

3

degrade settling time. It was determined that the extrapower consumption needed to make the slew ratelimitation negligible was too excessive for the low-power constraints of the design.

Instead, a variant of standard Miller compensationwas employed where the compensation capacitor isconnected to the drain of the input device (rather thatthe drain of the cascode device). It has been determinedthat such a technique pushes the right half-plane zeroout to infinity while adding another non-dominant poleat the complex conjugate of the primary non-dominantpole [Nakamura95]. As is shown in appendix C, thistechnique will result in a better phase margin thanstandard Miller compensation techniques and can leadto a more power-conscious compensation technique.

3 DESIGN ANALYSIS ANDOPTIMIZATION

In this section, we present the results from ouranalysis of the tradeoffs involved in meeting thespecifications presented. We will use these results inpresenting our device sizing in Section 4.

3.1 Dynamic RangeThe design of high resolution A/D converters sets

serious limitations on the allowable noise in the OTAin order to keep the overall system resolution.

A typical requirement for this kind of system is adynamic range (DR) greater than 80 dB. Note that thisspecification refers only to the amplifier noise and notto noise of the overall system. Therefore the samplingnoise from switches, necessarily present in theswitched capacitor (SC) circuits, is not considered inthe following analysis.

DR depends on both the output swing and theoutput noise power. Therefore a tradeoff betweenachievable swing and injected noise has to be found. Inour design approach, the output swing was fixed to2.2V (single-ended), considering the power supplyvalue and reliable values for the saturation voltages ofoutput stage devices.

As shown in appendix A, the output power forthermal noise is given by:

CFB

f

thCf

nKTv

1

3

222 = ,

where CC is the compensation capacitor, nf is the noisefactor of the amplifier and fFB is the feedback factor.This relation clearly shows that a lower limit on thesize of CC is imposed, in order to limit the noise level.Also, there is a lower limit on the sampling capacitor(CS) even though CS does not appear explicitly in theformula: indeed if CS is too small with respect to theinput pair gate capacitance, the 1/f term would beappreciably higher than 3 and would result in a higher

noise level (refer to appendix A for the precise math).Finally it is worth considering that the noise level willbe increased by the flicker noise contribution; thisexpression for flicker noise power is:

⋅

+

=

Hz

f

g

g

LW

K

LW

K

Cfv H

m

mfnfp

oxFBfo 1

ln11

21

27

7711

2

2/1,

The total noise power is the sum of these twocontributions.

3.2 Settling TimeThe specification of settling time requires a settling

accuracy of 0.01% within a period of 100ns. Thisspecification can be directly translated into a trade-offbetween ωu and the vdsat of the input pair, as a greaterωu reduces the linear settling time and a greater vdsat

cuts down on the slewing time for a given voltageswing.

As shown in appendix B, the settling time can beexpressed by the following equation:

⋅

−

−=

dsat

i

uFBFBdsat

i

usettle

v

v

ffv

vt ξ

ωωln

1

2

12

where vi is the maximum input swing seen, fFB is thefeedback factor (slightly greater than 3, due to theparasitic input capacitance of the OTA), and ξ is therequired settling accuracy.

3.3 Open-loop Voltage GainAs shown in appendix D, the gain of the telescopic-

cascode/common-source OTA is on the order of(gmro)

3. A more first-order precise calculation of gain,leads to the following expression:

( ) ( ) 1

931

3

212 −

⋅⋅= satd

satd

satdvo vvvA λαα

where α1, α2 < 1 to account for the loading effects ofthe current source loads of the first and second stages,respectively. In order to maximize gain, it is desired tokeep the loading factors as close to unity as possible.This is achieved by making the load transistors longerthan minimum length.

3.4 Summary of Design Tradeoffs andOptimization

As can be seen in the above analysis, each of theOTA specifications present a set of constraints to bemet by setting circuit parameters appropriately. Thesespecifications put conflicting sets of constraints on thecircuit parameters, and an optimal (i.e. minimal power)solution must be found within the subspace ofacceptable circuit parameter sets. This is a difficultprocess not amenable to simple hand calculations asthe constraints cannot be reduced to a closed-form

4

problem. Therefore, in our design process, we usedsimple hand calculations to set rough limitations onacceptable parameters, and then we developed andused a computer optimization technique to find anapproximate optimal solution. This process is describedin detail in appendix E. The results of the optimizationprocedure are summarized in Table 2: all the saturationvoltages and currents for the circuit are determined,therefore the OTA dimensioning can be now easilyobtained. These values refer to Figure 1 and theexpected performances for slow process parameters arereported in Table 3.

Vdsat [mV] gm [mS]M1/M2M3/M4M5/M6M7/M8M9/M10M11/M12

160100100320350300

0.9831.51.5

0.461

IssI2

150uA200uA

CcCs

1.5 pF0.8 pF

Table 2: Results of optimization process

Dynamic Range 81.5 dBGain 468,750Settling time 72 nsPhase margin 71°Output Swing (s.e.) 2.3V

Table 3: Theoretical results for slow parametersfrom optimization parameters

M 1 2

M 1 0

V -oV +

o

CS

CS

CC

CC

M 11

M 9 M 8

M 6

M 4

M 2 V -i

V +i

M 0

M 7

M 5

M 3

M 1

V g 0

V g3

V g5

V g7

V g1 1

V g1 1

VD D

Figure 1: Two-Stage OTA

4 TWO-STAGE OTAAlthough the design developed in the previous

section meets all the specifications according to handcalculations, the real behavior of the used technologydeviates from the simple models used for handanalysis. In fact the more precise models used bySPICE have underlined some important differences

between the previewed and the actual performance,which are summarized in the following section.

4.1 Design modificationsOne of the parameters deviating significantly from

the ideal hand-analysis behavior has been thetransconductance of the input stage, which was roughly20% lower than originally expected. This is due to thefact that our optimization procedure did not account forweak inversion effects; as in any power-consciousdesign the input devices reside near the transition to theweak inversion region. We accounted for thetransconductance sag by increasing the current of theinput pair slightly. It is worth noting that—beforecompensating with an increased bias current—thiseffect was significantly reducing the unity gainbandwidth, therefore causing the system to be slowerthan predicted.

Another deviation from ideal behavior isrepresented by variation of λ as the width of the devicevaries. This phenomenon directly reduces the secondstage gain. In the first approach, the length of outputdevices was increased to enhance their resistance;however the width was also increased in order to keepconstant the saturation voltage, and this resulted in abalancing effect on λ, leaving the resistanceunchanged. Therefore in order to meet the gainspecification in worst-case conditions (fast parametersprocess) a scaling of saturation voltages was necessary,according to the relations developed in appendix D.

As a consequence of this last modification theoutput swing is decreased; moreover in the idealcalculation the minimum drain to source voltage acrossthe output devices was assumed to be exactly theirsaturation voltage. In reality the output resistance of thetransistors starts to drop before such critical voltage isreached. Therefore the overall gain is greater than10,000 only for smaller voltage swing than predicted.This drop accounts for a safety margin included in thedynamic range calculation.

With this last modification, the OTA isdimensioned and the device size and main parametersare summarized in Table 4. The simulations result,reported in Section 4.4 will show the performanceobtained by this design.

Size(µm)

vdsat

(mV)Ibias

(µA)gm

(mS)M1-M2 91.6/0.6 160 80 0.821M3-M4 213.8/0.6 100 80 1.13M5-M6 91.6/0.6 100 80M7-M8 17.6/2.2 320 80M9-M10 33/0.6 300 245 1.02M11-M12 608/4.8 330 245

Table 4: Final Device Parameters

5

4.2 Common Mode FeedbackAs shown in Figure 2 dynamic switch capacitor

common mode feedback circuit (CMFB) wasintegrated into the OTA. As the OTA is a two-stageamplifier, the common-mode gain from input to outputis a positive value, and therefore CMFB cannot beapplied directly from output to input; instead aninversion is needed. The necessary inversion is createdby utilizing a differential pair; for instance, as thecommon mode output goes down, transistor MF1 stealsadditional bias current from the input pair, which inturn raises the common mode output back to itsnominal value. As shown in Figure 3, the CMFBcircuit has an open loop gain of 11,000 and unity gainfrequency of 9.5 MHz. While this is lower than theunity gain frequency of the OTA, it should besufficient as long as the common-mode input signaldoes not have significant signal strength above theCMFB circuit’s unity gain frequency.

V +o

V -o

C M F B re fA

V C M 0

C M F B re fB

V C M 0

C M F B re fB

C M B ia s

M F 1M F 2

VD D

Figure 2: Common-mode Feedback Circuit

Figure 3: CMFB open-loop response

4.3 Bias NetworkThe design of the bias network is a fundamental

step in the OTA project, as this part ensures that alldevices are working in the expected conditions. Thesub-circuits of the OTA which require to be biased are:

• second stage active load (M11/M12)• input pair current source (M0)• first stage cascode active load (M5 to M8)• first stage input pair cascode (M3/M4)• CMFB circuit

The bias network is shown in Figure 4, and isexplained in detail below.

MC6MC7MC1

MC2

MC3

MC4MC5

Vg5

Vg7CMBias

CMFBRefBCMFBRef

AMB4

MB5

MB3

Vg3

Ir ef

MB1Vg11

VD D

Figure 4: Bias Network

The second stage active load has been biased usinga mirrored version of the reference current, as the gateof Mb1 is directly connected to the gates of M11 andM12. The reference current is mirrored in the sameway in the input pair and in all the other bias lags. Notethat non-minimum current and devices have beenchosen, in order to overcome mismatch in the mirroredcurrents. Moreover it would be more difficult toovercome current differences using cascoded currentmirrors, because the power supply is quite low.

The biasing of the first stage active load isparticularly delicate: indeed, referring to the OTAschematic, the voltage across the cascode M5-M7 isfixed by the Vgs of M9, which can't be very high.Moreover, during slew rate settling, M9 is expected toturn off completely. Therefore, the voltage at the gateof M9 is expected to go below threshold while stillkeeping the first stage cascode well in saturation. Forthese reasons a high-swing biasing has been chosen togenerate Vg5 and Vg7. This part of the biasingnetwork is formed by devices from MC1 to MC9.

The current in the second stage is fixed biasingM7/M8, which is fed by a current mirror (MC2). Thegate of M5 has to be fixed at the lowest possiblevoltage, without pushing M7 to the triode region,therefore:

satdgsG Vvv

755 +=In reality we must account for a safety margin(~100mV), because the output resistance of M7 willstart to decrease before the triode threshold. In theadopted circuit the bias voltage vg5 is given by:

6

435 dsgsg vvv +=MC4 and MC5 are dimensioned in order to make Vds4equal to the Vd7sat plus the safety margin. Theequation regulating the circuit are:

( )( )

( )( )

−−⋅=

⋅=

4

5

7

5

1154

75

LW

LW

Vv

LW

LW

VV

satdds

satd

satd

The circuit has been dimensioned in order to havesat

dds Vv74

18.1 ⋅=MC3 has the same dimension of M5 and is driving thesame current, so

5353 gsgssat

dsat

d vvVV =⇒=Note that this circuit is also insensitive to body effect.

Typically, the cascoded input devices are biasedindirectly off of the common source of the input pair.In a previous revision, this was attempted, but wasdeemed unsuccessful. This is because, during slew ratesetting, one of the input devices is by definition turnedoff. Therefore, the common source no longer appearsto be a virtual ground, thus causing the bias voltage ofthe cascode device to deviate from its DC value. Thiscaused a slow-settling transient error, as the changingbias on the cascode effectively modulated the outputvoltage. Instead, a more robust biasing scheme—utilizing MB4 and MB5—was used in order to create astable bias voltage on the order of vdsatB4. An addedimprovement of this biasing scheme is theindependence of the bias voltage on VTH variations.

The references needed by the CMFB weregenerated using currents mirrors and other diodeconnected transistors.

4.4 ResultsThe circuit was simulated in SPICE and a summary

of results are as follows:

ProcessSlow Nominal Fast

DR (dB) 80.3 80.4 80.6Av0 43,700 27,500 17,000Settling time 79 ns 75 ns 68 ns

Table 5: Performance summary

As can be seen above, all specifications were met.In fact, the settling time is well under specification.Part of this is due to the fact that a fair amount of safetymargin was included in the original design in order toensure proper operation.

4.5 Power DissipationTable 6 shows the power breakdown of our circuit

as reported by SPICE. The power dissipation of thefirst and second stage are reasonably low, comprising alittle less than 2 mW under all process parameters.

ProcessSlow Nominal Fast

First Stage 480 µW 485 µW 490 µWSecond Stage 1460 µW 1480 µW 1490 µWCMFB network 165 µW 175 µW 180 µWBias network 1710 µW 1790 µW 1845 µWTotal of first andsecond stage 1.94 mW 1.96 mW 1.98 mWTotal of entireOTA 3.82 mW 3.93 mW 4.01 mW

Table 6: Power dissipation of two stage design

The bias network consumes a large amount of power incomparison to the power of the other parts of thecircuit. The power is purposefully made relativelylarge, because large bias currents are used so thatmatching problems are minimized when mirroringcurrents.

4.6 Open-Loop Gain SimulationFigure 5 to 7 show the DC open-loop gain response

of the circuit for all 3 processes. In each figure, the topplot shows the double-ended output response and thebottom plot shows the differential output. In all plots,the x-axis is the input single-ended voltage—the inputdifferential voltage is simply twice that value. As canbe observed on all three plots, the DC gain remainsabove 10,000 between +2.2V to –2,2V differentialoutput.

Figure 5: DC open-loop response, slow parameters

7

Figure 6: DC open-loop response, nominalparameters

Figure 7: DC open-loop response, fast parameters

Figure 8: AC open-loop response, slow parameters

Figure 9: AC open-loop response, nominalparameters

Figure 10: AC open-loop response, fast parameters

4.7 Frequency and Step ResponseSimulation

Figure 8 to 10 show the AC open-loop response ofthe circuit for all 3 processes. As derived in appendixC, the phase margin is

⋅

⋅⋅⋅−= −

c

s

dsat

dsatFBm

C

C

vI

vIf

12

911tan290φ

The plots show that all frequency responses have aphase margin of approximately 70 degrees at fFBωu =ωu/3. The plots show that the unity-gain frequency isslightly higher for the fast process than the slowprocess. This is to be expected, as the fast process has ahigher kp, and also has slightly higher bias currents.

Figure 11 shows the double-ended step responseused in transient simulations. The output transitionsfrom a +2.2V differential output to a –2.2V differentialoutput, with the input step applied at 350ns.

8

Figure 11: Typical step response

Figures 12 to 14 show the step response of thedifferential output for each process. In all processes,the transient settles to 0.01% of its final value within80ns. The transient does display a static settling error,but this is due to parasitic capacitive loading at theinput. In order to minimize this static error, gains muchgreater than 10,000 would be necessary.

Figure 12: Step response, slow parameters

Figure 13: Step response, nominal parameters

Figure 14: Step response, fast parameters

9

4.8 Noise SimulationIn order to evaluate the dynamic range

performances the output noise density was calculatedby simulations. Figures 15 to 17 show the obtainedoutput noise densities for the three process parameters.In Table 7, the corresponding dynamic range and noisefactor are reported. The former quantity has beencalculated integrating the noise density from 1Hz up toinfinity, due to the fact that the presence of switches inthe circuit will fold very high frequency noise into thebase band. Table 8 reports the noise power contributionfrom each device. It should be noted that, in all cases,devices other than M1/M2 and M7/M8 contributed atotal of less than 0.15% of the total noise density.

Dynamic Range Noise factorSlowNominalFast

80.3 dB80.4 dB80.6 dB

1.371.351.34

Table 7: Dynamic Range and Noise Factor

Slow Nominal FastTh 1/f Th 1/f Th 1/f

M1/M2M7/M8

72%28%

67%33%

73%27%

71%29%

74%2%6

77%23%

Table 8: Thermal and Flicker Noise Contributions,by device

Figure 15: Noise density, slow parameters

Figure 16: Noise density, nominal parameters

Figure 17: Noise density, fast parameters

4.9 Design SummaryAs shown in the previous sections, the hand

analysis of the circuit was supported by a computer-based optimization routine, in order to find theminimum power solution for the design. This analysiswas then calibrated and modified in order tocompensate for the main discrepancies between theideal model and the actual behavior of the circuit. Thisapproach has lead to a design solution which can beaddressed as minimum power while meeting thespecifications required by the specific application ofthe pipelined A/D converter. As SPICE simulations canpresent some errors, deviating from real circuitoperation, a safety margin is advisable. We can say thatthe proposed solution satisfies this criterion, with theexception of the DR values. However increasing theDR requires a substantially bigger capacitor; as thisimplies a increase the currents by the same amount, itis to be avoided.

5 CONCLUSIONSThe OTA presented is a two-stage amplifier. Its

first stage is a PMOS telescopic cascode, and thesecond stage is a common-source gain stage. It iscompensated using a variant of standard Millercompensation, where the compensation capacitor isconnected to the drain of the input device rather thanthe drain of the cascode device. The OTA meets allperformance specifications with a reasonable safetymargin across all process variations, and dissipatesslightly less than 2 mW of power.

We believe that this OTA is a good design for atwo-stage OTA with the required specifications. Asdiscussed in section 2, the use of a telescopic first stagewill give roughly the same performance/power trade-off as a folded first stage, and the compensationtechnique allows for a more power-conscious designwhile keeping 70 degrees of phase margin. It is

10

conceivable that a lower power design could beobtained with this topology for the following tworeasons. First of all, in our optimization technique, wedid not take into account weak inversion effects of theinput pair. Therefore, in modifying the design forSPICE verification, the device sizes did not “track” theoptimal transconductance/power trade-off asdetermined by SPICE. Also, our design has a gooddegree of safety margin included in it. In particular, thesettling time for the slow process has a safety marginof roughly 20%. This margin could be reduced byreducing the input pair bias current, and thus the totalpower could be reduced. Still, due to process andperformance variations not modeled by SPICE, webelieve that this safety margin makes our design morerealizable in real-world applications.

The CMRR and PSRR of this circuit will bereasonable, but not exceptional. Both of these measurescould have been improved by raising the outputresistance of the input current source. Such amodification could be achieved by cascoding the inputcurrent source. This was not pursued, as the low-voltage power supply and telescopic structure of thefirst stage did not leave enough voltage headroom forsuch a modification.

Due to the high output resolution of the A/D systembeing designed, it seems as if device matching wouldpresent a very difficult problem. Indeed, with 13-bitprecision, a single LSB error is only 268 µV.Therefore, common-centroid layout techniques andoffset-cancellation circuitry in the SC structure seem anecessity in order to keep overall system resolution.

A. NOISE ANALYSIS CALCULATIONSThe total output noise power in a two-stage

compensated OTA can be obtained by considering theinput referred noise density of the amplifier. Forsimplicity we consider thermal and flicker noiseseparately, starting with the former.

The input referred thermal noise density, can beexpressed as

1

2,

3

24

m

fthi

g

nKT

f

v=

∆,

where gm1 is the transconductance of the input device

and the noise factor, sat

d

satd

fV

Vn

7

11+= , is accounting for

the contribution to noise of other devices in theamplifier.

Approximating the frequency response of theamplifier with a single pole response, where thedominant pole in determined by the compensationcapacitance CC, the calculation of noise power can besimply expressed as the known integral of the noise

density from an RC circuit; therefore the output powernoise can be expressed as:

13

1

3

22,

gss

sFB

CFB

fTtho

CC

Cf

Cf

nKv

+=

=

where fFB is the feedback factor for the closed loopconfiguration of the amplifier.

In a similar way the input density for the flickernoise can be considered:

+=

∆ 21

27

7711

2/1, 11

m

mfnfp

ox

fi

g

g

LW

K

LW

K

Cff

v,

where f indicates a frequency and the other parametershave the usual meaning. As the corner frequency offlicker noise will be lower than the dominant pole ofthe amplifier, this noise is not band-limited by theOTA, therefore the output power is directly the integralof the noise density, multiplied by the squaredfeedback factor, to refer to the output of the amplifier.So the noise power for flicker noise becomes:

⋅

+

=

Hz

f

g

g

LW

K

LW

K

Cfv H

m

mfnfp

oxFBfo 1

ln11

21

27

7711

2

2/1,

where the upper integration limit fH has to be chosenhigher enough than the corner frequency.

Finally the total output noise power is given by thesum of the two powers calculated, multiplied by two, toaccount for the doubled structure of the differentialamplifier. The expression for dynamic range thenbecomes:

( )

+⋅=

2/1,

2,

10 2

1

2log10)(

fotho

sw

VV

VdBDR

B. SETTLING TIME CALCULATIONSSettling time consists of two components: slew rate

settling and linear settling Slew rate limited settling isdue to the class A configuration of the OTA and thelimited amount of current the first stage of theamplifier can deliver to charge up the compensationcapacitor. As derived in lecture, the slew rate is:

SR = Iss/Cc

which yields a slewing time of:

−=

FBdsat

i

uslew

fv

vt

2

12

ω

11

where vi is the maximum differential voltage swingseen at the input and fFB is the feedback factor. Themaximum voltage swing seen at the input will be 2.2V,as the output has a differential swing of 4.4V (+2.2V to–2.2V). Also, the feedback factor will be slightlygreater than 3, due to the input parasitic capacitance ofthe OTA.

The linear settling time is:

⋅

−=dsat

i

uFBlinear v

v

ft ξ

ωln

1

which yields a total settling time of:

⋅

−

−=

dsat

i

uFBFBdsat

i

usettle v

v

ffv

vt ξ

ωωln

1

2

12

The above results are based on the assumption thatthe slew rate is set by the slewing capability of the firststage and is not at all limited by the slewing of thesecond stage of the OTA. In order for this assumptionto be correct, two conditions must hold, namely:

(1) The drain of the cascode devices must be ableto completely turn off the NMOS transistor inthe second stage.

(2) The current supplied by the PMOS load of thesecond stage is sufficient to supply thenecessary current to the slew-limited firststage and simultaneously supply enoughcurrent to charge up the load capacitance.

The first condition is met by biasing the NMOSloads of the first stage with a high-swing biasingtechnique—as described in Section 4.3—to allow theoutput voltage of the first stage to go below thethreshold voltage of the second stage input. The secondcondition is met by setting the second stage biascurrent as follows:

+≥c

sc

C

CCII 12

where I2 is the bias current of M9 and M10 and I1 is thebias current of M1 and M2.

C. PHASE MARGIN CALCULATIONSDynamic range calculations discussed in appendix

A set rough guidelines on the value of Cc, and feedbackfactor requirements set rough guidelines on the valueof Cs. With the parameters set as outlined above, therequirements for 70 degree phase margin can becalculated.

The compensation technique used is not standardMiller compensation. Instead, it is a variant of this,where the compensation capacitor is attached to thedrain of the input device rather than the drain of thecascoded device. The end result of this compensation isto push the right-half plane zero out to infinity andintroduce a new non-dominant pole at the complexconjugate of the first non-dominant pole. As the zero ispushed out to infinity, there is no concern over a pole-zero doublet occurring near the frequency band ofconcern. This compensation technique increases phasemargin slightly over standard Miller compensation asthe frequency location of the Miller zero is:

um

m

g

gzero ω

1

9=

and the frequency of the new pole is:

us

c

m

m

C

C

g

gpole ω

=

1

9

Therefore, for Cc greater than Cs, (which is always thecase), the additional pole is at a higher frequency thanthe old zero. Thus, a net gain in phase margin isobtained.

As the OTA has a global feedback network with afeedback factor of roughly 1/3, the phase margin ismeasured at the location where the open-loop gain isapproximately 3. The equation for phase marginbecomes:

⋅⋅−= −

1

1tan290p

uFBm

f

ωωφ

Making some simple substitutions:

⋅

⋅⋅⋅−= −

c

s

dsat

dsatFBm C

C

vI

vIf

12

911tan290φ

This expression for phase margin, with a requirementof 70 degrees, was used in the optimization procedurein order to size the devices correctly.

D. DC GAIN CALCULATIONSIt can be shown that the DC gain for a two-stage

telescopic-cascode/common-source is as follows:

( ) ( )[ ] ( )0119975533110 rrgrgrrgrgA omomoomomv ×=

If the following substitutions are made:

IrvIg odsatm λ1 2 and ==

the equation for gain can be expressed as follows:

( ) ( ) 1

931

3

212 −

⋅⋅= satd

satd

satdvo vvvA λαα

12

where α1, α2 < 1 are attenuation factors due to theparasitic resistance of the current source loads. Theabove expression shows an inverse relationshipbetween open loop gain and the vdsat’s of the transistorsin the signal path. This relationship was used in theoptimization procedure to size the signal pathtransistors in order to meet the required gainspecification.

It is worth noting that the above expression is onlycorrect to the first order. This is due to the assumptionthat λ is independent of device width. While this isassumed to be true in first-order transistor models, itdoes not hold in actual process parameters. Therefore,the above expression was used as a guideline, but again safety margin was included in the optimizationprocedure in order to compensate for λ inaccuracies.

E. OPTIMIZATION ROUTINEIn the previous appendix, various circuit

characteristics were expressed analytically as functionsof circuit parameters. The assigned specifications canbe used with these relations in order to dimension theamplifier. However some degrees of freedom are leftand finding an optimum solution in terms of powerdissipation becomes a challenge. For this reason thevarious relations were combined to find a targetfunctions that was minimized in order to find theminimum power configuration.

As a first step the output swing and the noise factorwere fixed to some achievable values (respectively2.2V and 1.5). The value of output swing allows thecalculation of the maximum saturation voltages for theoutput stage and the amplitude of the input step forsettling time testing. Moreover fixing these parameters,from the dynamic range expression, it is possible todetermine the value for CC. CS was arbitrarily fixed at avalue that would not overly degrade the feedbackfactor.

At this point we can choose the saturation voltageof M1/M2 in order to minimize the total current. Fromappendix B, ISS results a function of ωu and Vd1sat;however ωu can be expressed as a function of Vd1sat;therefore Iss only depends on Vd1sat:

−

−≥ sat

d

stepsatd

s

csatdstep

s

Css V

VV

t

CVV

t

CI

1

11ln

3

2

32 ε

This relation is a monotonically increasing functionof Vd1sat. Therefore to minimize the current in the firststage we can minimize the saturation voltage of inputdevices. However the current in the second stage alsohas to be considered. From phase margin requirements,I2 can be expressed as a function of ISS/Vd1sat, thereforeagain as a function of only Vd1sat, which in this case ismonotonic decreasing. Moreover from slew rate

requirements, another relation limit is imposed on I2

and this time the lower limit in decreasing as a functionof Vd1sat. The two relations are reported below:

( )

+ω≥

ε−

−

ϕ−°

≥

21

ln3

232

2

90tan6

1

11

9

2

2

sCusat

d

satd

step

ssat

d

step

sm

satds

CCVI

V

V

tV

V

t

VCI

As it can be easily observed, these two constraints letus find an optimum point, where both the inequalitiesare satisfied and the current is minimum: that value hasbeen assumed for Vd1sat.

Once determined Vd1sat, Vd7sat can be fixed in orderto satisfy the requirement chosen for the noise factor.Finally the two input cascodes are to be dimensioned.Their saturation voltages have been chosen as low aspossible: this criterion leads to an easier biasing, booststhe gain (see appendix D), and helps move the secondnon-dominant pole introduced by the compensationnetwork to a higher frequency.

As mentioned in Section 3, this procedure allowedus to determine all currents and saturation voltages forthe OTA. Therefore the transistor dimensioningbecomes straightforward. According to the developedmath, these values are the minimum powercompromise which meets the required specs; in realitycurrents and capacitor values have been increased togrant a safety margin in the real circuit.

[Cho95] Cho, T. “Low-Power, Low-Voltage Analog-

to-Digital Conversion Techniques using PipelinedArchitectures.” PhD Thesis, University ofCalifornia, Berkeley. 1995.

[Flores96] Flores, A., Daniel, L., “Design of aMinimum Power, Low-Voltage Supply Fully-Differential Transconductance Amplifier for A/DConverters.” EE240 Project Report. University ofCalifornia, Berkeley. 1996.

[Feldman97] Feldman, A. R., “High-Speed, Low-Power Sigma-Delta Modulators for RF BasebandChannel Applications.” PhD Dissertation,University of California, Berkeley. 1997.

[Nakamura95] Nakamura, K., Carley, L., “An 85mW,10b, 40 Msample/s CMOS Parallel-PipelinedADC.” IEEE Journal of Solid-State Circuits, Vol.30, No. 3, March 1995.