A Low-Power HKMG CMOS Platform Compatible With Dram Node 2× and Beyond

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 61, NO. 8, AUGUST 2014 2935

A Low-Power HKMG CMOS Platform CompatibleWith Dram Node 2× and Beyond

Romain Ritzenthaler, Member, IEEE, Tom Schram, Alessio Spessot, Christian Caillat, Marc Aoulaiche,Moon Ju Cho, Kyoung Bong Noh, Yunik Son, Hoon Joo Na, Thomas Kauerauf, Bastien Douhard,

Aftab Nazir, Soon Aik Chew, Alexey P. Milenin, Efrain Altamirano-Sanchez, Geert Schoofs,Johan Albert, Farid Sebai, Emma Vecchio, Vasile Paraschiv, Wilfried Vandervorst,

Sun-Ghil Lee, Nadine Collaert, Pierre Fazan, Senior Member, IEEE,Naoto Horiguchi, and Aaron Voon-Yew Thean

Abstract— In this paper, a low-cost and low-leakage gate-firsthigh-k metal-gate CMOS integration compatible with the highthermal budget used in a 2× node dynamic random access mem-ory process flow is reported. The metal inserted polysilicon stackis based on HfO2 coupled with Al2O3 capping for pMOS devices,and with a TiN/Mg/TiN stack together with As ion implantationfor nMOS. It is demonstrated that n and pMOS performance of400 and 200 µA/µm can be obtained for an OFF-state current of10−10 A/µm, while maintaining gate and junction leakagescompatible with low-power applications. Reliability and matchingproperties are aligned with logic gate-stacks, and the proposedsolution is outperforming the La-cap-based solutions in terms ofthermal stability.

Index Terms— As ion implantation (I/I), CMOS processintegration, dynamic random access memory (DRAM) peripherytransistors, high-k metal gate (HKMG), La capping layers,Mg capping layers, MOSFET fabrication.

I. INTRODUCTION

DYNAMIC random access memory (DRAM) technolo-gies are using multiple transistors in their peripheral

circuitry to cover the different requirements of the design, as

Manuscript received April 14, 2014; revised May 28, 2014; acceptedJune 10, 2014. Date of publication July 2, 2014; date of current versionJuly 21, 2014. This work was performed as part of imec’s Core PartnerProgram. The imec Core CMOS program members, the imec pilot line andamsimec are also greatly acknowledged for their technical support. The reviewof this paper was arranged by Editor R. M. Todi.

R. Ritzenthaler, T. Schram, M. Aoulaiche, M. J. Cho, T. Kauerauf,B. Douhard, A. Nazir, S. A. Chew, A. P. Milenin, E. Altamirano-Sanchez,G. Schoofs, J. Albert, F. Sebai, E. Vecchio, V. Paraschiv, W. Vandervorst,N. Collaert, N. Horiguchi, and A. V.-Y. Thean are with imec, Leuven3001, Belgium (e-mail: [email protected]; [email protected];[email protected]; [email protected]; [email protected];[email protected]; [email protected]; [email protected];[email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected];[email protected]; [email protected]; [email protected]).

A. Spessot, C. Caillat, and P. Fazan are with Micron, Leuven3000, Belgium (e-mail: [email protected]; [email protected];[email protected]).

K. B. Noh and Y. Son are with SK-Hynix, Icheon 467-701, Korea (e-mail:[email protected]; [email protected]).

H. J. Na and S.-G. Lee are with Samsung Electronics Company, Ltd., Suwon442-600, Korea (e-mail: [email protected]; [email protected]).

Color versions of one or more of the figures in this paper are availableonline at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TED.2014.2331371

address decoders, high-voltage applications, and sense ampli-fiers [1], [2]. Currently, the DRAM periphery transistors inhigh volume manufacturing are still based on polysilicon/SiO2and are lagging behind logic in terms of scaling to keep pacewith cost. To guarantee the high performance required by thenext generations of memories, the industry roadmap expectsthat such devices will adopt characteristics already used inhigh-performance logic devices [1]. Therefore, introduction ofhigh-k metal gate (HKMG) [3] is becoming a key enablerfor 2× node DRAM periphery transistors (corresponding toLG ∼ 45 nm [4]) and beyond.

DRAM periphery transistors must also be compatible withDRAM process specifications, which implies a process costas low as possible and resistance to an extra-long DRAManneal (DA) [1]. Such anneal mimics the high thermal budgetsteps required by the fabrication of the DRAM memoryelements [storage capacitor, access transistor, and back end ofline (BEOL)], and should be seen as additional constraint forperiphery transistors design, because all the required moduleshave to be resistant to such anneal. DA also induces the needfor dedicated gate-stacks and junction tuning for nMOS andpMOS, as well as resistant thermally stable silicide. In orderto target low-power mobile applications, low leakages arealso a necessity; the transistors used in the periphery of thememory cell are typically more aggressive in terms of gateleakage [hence a thicker electrical oxide thickness (EOT)compared with logic applications] and junction leakages(OFF-state current) control.

In this paper, a high-k/metal-gate CMOS integration forDRAM periphery transistors is proposed. The gate-first inte-gration flow is presented in Section II. The gate-stack perfor-mance are shown in Section III-A and junctions related aspectsin Section III-B. The final drive current performance measuredon ring oscillators are presented in Section III-C.

II. DEVICE MANUFACTURING

The gate-first CMOS integration scheme is illustrated inFig. 1. After Shallow Trench Isolation (STI) formation andwell doping, an interfacial layer is grown (nitrided SiO2, thick-ness of 1.3 nm, using In Situ Stream Generation). A blanketlayer of Al2O3 is deposited on the whole wafer, then selec-tively removed from everywhere but pMOS gate transistors.

0018-9383 © 2014 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

2936 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 61, NO. 8, AUGUST 2014

Fig. 1. Schematic flow of the gate-first DRAM PERI anneal compatiblelow-power CMOS.

Fig. 2. Schematic presentation of the CMOS electrode integration of theprocess flow (i.e. the first highlighted block of Fig. 1 up to gate patterning).Subparts are Al2O3 deposition and masking (a), selective removal andTiN/Mg/TiN deposition (b), masking and selective removal on P-side (c)–(d),masking and As I/I Implantation (e) and Silicon deposition (f).

A 2-nm HfO2 high-k layer is subsequently deposited, followedby a Mg layer as n-type metal gate, which is selectivelyremoved from the pMOS area. Gate-stacks for nMOS andpMOS are completed by a further TiN metal gate layerand polysilicon electrode. After gate patterning, junctions areformed with lightly doped drain, halo, spacers deposition,heavily doped drain implantations, and activation. After thesource/drain silicidation, the DA is added (thermal budgetin the 600 °C–750 °C, ≥1-h range). The process flow iscompleted with conventional BEOL.

Fig. 2 highlights the CMOS electrode part of the integration.In particular, the CMOS gate-stacks are fabricated starting with

Fig. 3. eWF versus EOT for n- (As I/I only, Mg + As I/I, La capping) andp stacks (HfO2 capping below high-k). Various combinations of possible DAsare represented, highlighting the great thermal stability of Mg + As I/I andAl2O3 capping shifter schemes. W = L = 50 μm.

the deposition on the entire wafer of Al2O3 layer [Fig. 2(a)].The removal from the nMOS side is performed using apreviously described process [5], [6]. After this, the Mg dopingof the HfO2-based dielectric stack is obtained by out-diffusionof Mg from a tuned TiN/Mg/TiN sandwich [Fig. 2(b)] thatis selectively removed from the pMOS transistor area [7][Fig. 2(c) and (d)]. A uniform deposition of the TiN electrodefor both nMOS and pMOS is done [Fig. 2(e)]. After a selectiveAs gate ion implantation (I/I) on the nMOS device area [5]–[8] [Fig. 2(e)], the gate-stacks are completed with the silicondeposition [Fig. 2(f)].

III. ELECTRICAL PERFORMANCE

A. Gate-Stack

The gate-stack effective work function (eWF) for low-powerapplications should be low (resp. high) enough for nMOS(resp. pMOS) to deliver an acceptable ON-state current whilemaintaining a strict control of OFF-state currents, leading torelaxed VTH targets compared with logic applications.

In this paper, the threshold voltage of nMOS devices istuned using both Mg and As I/I in the gate-stack: the formeris expected to create dipoles diffusion toward the high-k/SiO2interface [9]–[11], whereas the latter is filling the preexistingtrap in the HKMG [5]–[12]. The addition of As I/I allowsfor a ∼100 mV VTH shift with regard to midgap, whereas itscombination with a layer of Mg sandwiched between two TiNlayers leads to a work function of 4.32 eV (Fig. 3).

For pMOS gate-stacks, the threshold voltage lowering isobtained by the incorporation of Al between the interfaciallayer and Hf-based high-k and subsequent creation of dipolesoriginated from the Al2O3 diffusion [3]–[13]. The Al2O3capping layer used in this paper is delivering a work functionof 4.85 eV (Fig. 3).

In the DRAM periphery context, a good thermal stabil-ity regarding to DAs is preferred since it induces a larger

RITZENTHALER et al.: LOW-POWER HKMG CMOS PLATFORM 2937

Fig. 4. n- and p-well gate-to-bulk accumulation capacitance (W = L =50 μm), showing measurements of 11 dies across the wafer (see inset forwafer coverage).

versatility to process changes in the DRAM cells. Suchrequirement has been assessed by combining different anneals(various thermal budgets combination with temperaturebetween 600 °C and 750 °C, ≥1-h duration, Fig. 3). Theabsence of temperature modulation in the case of the TiN + AsI/I, or Mg sandwiched + As I/I is evidenced. As a bench-mark, widely reported gate-stacks with lanthanum cappinglayers [3] + As I/I have also been fabricated. La cappinglayer-based nMOS stacks are potentially more aggressive interm of work function shift, but are not thermally stable forrealistic thermal treatment (∼100-mV anneal dependent shiftobserved for the same thermal budgets applied, Fig. 3). Thethermal stability and sufficient work function shift to low-power application justify the choice of Mg + As I/I overLa capping options for the DRAM periphery nMOS gate-stack. The origin of the higher thermal stability is likely dueto the different diffusivity of La versus Mg in the high-k.It has been proved that La is a slow diffusor in the high-k[14], [15]. Therefore, even aggressive thermal treatment interms of both temperature and duration are not preventingfurther diffusion of La-induced dipoles toward the HK/SiO2interface [16]. On the contrary, Mg is a faster diffusor, likelydue to the lighter mass of such element, so its diffusion isalready saturated with thermal budget regularly achieved bystandard CMOS fabrication, and no further threshold voltageshift is observed with the additional thermal treatments.

For low-power applications, the stringent requirement forlow gate leakage leads to the use of thicker gate-stacks thanin logic applications, preventing the use of a chemical-basedoxide. This was obtained here using an interfacial layer thickerthan the standard logic devices (>1 nm) generated by in situsteam generation. Using Hauser CVC fitting [17], the eWF andEOT are extracted. EOT values for the final CMOS integrationare, respectively, 12.9 Å for nMOS and 14.6 Å for pMOS(Fig. 4). Moreover, the overlay of the CV curves for differentdevices across the wafer surface confirms a very uniform EOTfor both the n and pMOS gate-stacks.

Fig. 5. Saturation threshold voltage VTH,SAT versus gate length LGhighlighting the VTH lowering using As I/I (open symbols: baseline; closedsymbols: baseline + As I/I) W = 1 μm and VDD = 1 V.

Fig. 6. nMOS/pMOS gate leakage versus EOT, showing the excellentperformance obtained in terms of leakage control, and in particular the verysmall penalty using As I/I. W = LG = 10 μm.

An example of VTH roll-off versus gate length is plottedin Fig. 5. Using similar junctions in wafers featuring aTiN/Mg/TiN and TiN/Mg/TiN + As I/I nMOS metal gate, itis clear that the work function shift induced by As I/I is main-tained (at least partially) down to short channel, demonstratinga good control of the VTH shift for the entire range of analyzedgeometries. In the case of TiN/Mg/TiN + As I/I metal gate,a long-channel threshold voltage of 0.4 V is obtained.

Fig. 6 shows the gate leakage JG versus EOT for then and p gate-stacks, as measured on 10 × 10 μm2 tran-sistors. To account for the different VTH, the extraction isperformed at fixed overdrive (at VTH ± 0.6 V for n/pMOS).Gate leakage is following the SiO2/polysilicon trend, and allthe values are below 0.01 A.cm−2 for both nMOS and pMOSdevices. A too high dose of Mg in the TiN could result in adegradation of gate leakage (not shown here), confirming thatthe Mg dose used in these device is compatible with the low


Fig. 7. Benchmark of high field mobility (split CV, at inversion chargenS = 1013 cm−2) versus EOT. Open points are extracted from [16], closedpoints are imec gate-first trends.

leakage requirement. Comparing the wafer with TiN only andTiN/Mg/TiN, it is clear that a good tradeoff between workfunction shift and gate leakage increase is achieved for theconsidered Mg dose. By comparing splits with and withoutAs I/I, it is measured that the application of As I/I is leadingto a small increase of gate leakage (JG × 2), well inside theacceptable range.

Regarding pMOS stacks, Al2O3 capping between interfaciallayer and high-k leads to a small JG degradation over trend(in line with results reported in [18]).

It is also known that too high dose of VTH shifter couldresult in a degradation of mobility through possible enhancedremote Coulomb scattering [20] or shifters migration in thechannel. By plotting the high field mobility (extracted atnS = 1013 cm−2) versus EOT, it is checked that the proposedn and p stacks are in line with logic gate-stacks and previouslypublished data (Fig. 7).

Furthermore, the reliability of the selected gate-stacks wasevaluated. Bias temperature instabilities (BTIs) were measuredon W×L = 10×1 μm2 transistors at 125 °C. Even with a strict30-mV VTH shift failure criterion, a 10-year BTI lifetime witha gate voltage overdrive (VG − VTH) of −0.7 V for the pMOS(Fig. 8) and 0.8 V for the nMOS (Fig. 9) was extracted. Thesevalues compare well with those obtained for metal-gate high-k-based logic gate-stacks (by definition not submitted to DA)and with previously measured DRAM periphery transistors(diamonds, Figs. 8 and 9). Negative BTI (NBTI) voltageover-drive at 10 years is linearly dependent on EOT aboveEOT = 1 nm, indicating that the defects generation andthe device degradation mechanism is field dependent. Suchdependence is mainly related to Si/SiO2 interface degradationby interface states generation. Below 1 nm of EOT, the holetrapping mechanism is dominant and NBTI voltage over-drive at 10 years reduces rapidly [21]. On the other hand,the positive BTI (PBTI) in nMOS devices occurs by elec-tron trapping into bulk defects [21]. Subsequently, an EOTscaling obtained by reducing the high-k thickness is actually

Fig. 8. Benchmark of the NBTI lifetime versus gate-stacks without DA.Threshold voltage shift criterion = 30 mV. Adapted from [21].

Fig. 9. Benchmark of the PBTI lifetime versus gate-stacks not submittedto DA. Threshold voltage shift criterion = 30 mV. Adapted from [21].

improving lifetime for EOT >1 nm. This indicates that regard-ing BTI there is an intrinsic limit of scaling for PMOS DRAMperiphery devices with bulk Si below 1 nm, while scaledNMOS DRAM periphery devices are expected to exhibit aneven better lifetime.

B. Junctions

The need to use ultrashallow junctions to keep pace with theperformance requirement have to be combined with sustainingthe prolonged anneals of a DRAM flow. Therefore, a specifictuning of preamorphization implantations [22] and junctionco-implants [23] is required due to the effect of additionalthermal budget. To optimize the junction scheme, a calibratedTCAD deck was obtained with the help of SIMS, TEM pic-tures, and scanning spreading resistance microscopy (SSRM)profiles (Fig. 10). The long and high thermal budget requiredby DRAM periphery transistors imposes additional difficulties


Fig. 10. Comparison of the 2-D dopant profile simulated using the calibratedTCAD model (left) and the resistance experimentally measured by SSRMprofile (right), for a pMOS device.

Fig. 11. VTH roll-off (median values) at VD = 1 V illustrating the variousoptions obtained by tuning the junction profiles. W = 1 μm.

accounting for various thermal diffusion process in TCADsetup [24]. Fig. 10 illustrates the good correspondence of thesimulation and experimentally observed junction profiles bySSRM [25], [26].

After checking that TCAD structure was able to pre-dict accurately the roll-off and ION/IOFF through changes inthe junctions implantation scheme, a design of experiment-based approach allowed to define several set of junctions,depending on the threshold voltage target. Fig. 11 shows theVTH roll-off curves corresponding to the tuned high perfor-mance/general purpose/low stand-by-power (LSTP) junctionconditions.

For the low-power applications targeted in this paper, thejunction scheme of interest correspond to the LSTP schemeof Fig. 11. The selected implantation condition features thehighest Halo dose, what could potentially have detrimentalimpact on matching performance [27]. Fig. 12 shows thematching coefficient AVT values obtained for the optimizedMg sandwich-based nMOS and Al2O3 cap-based pMOS stackthat are integrated in the CMOS flow. These values are

Fig. 12. Matching coefficient AVT versus inversion thickness tINV. A match-ing performance comparable with other bulk planar baselines is obtainedfor DRAM compatible devices. AVT is obtained on matched pairs, andcorresponds to σ�Vt. Benchmark data related to σVt [24], [30] are multipliedby

√2, and tINV when nonspecified are calculated by adding 4 Å to EOT.

Fig. 13. Junction leakages measured on area diodes. Area diode sur-face = 5000 μm2, VDD = ±1 V.

following the trend for bulk Si devices, and demonstrate thatthe proposed low-power junction scheme is not harmful tomatching performance.

To complete the junctions validation, junction leakages(measured on area diodes at T = 85 °C) are extracted; they,respectively, feature leakage current density of 200 nA.cm−2

for nMOS and 350 nA.cm−2 for pMOS, confirming thepotential for low-power application of the proposed junctionscheme (Fig. 13).

C. Drive Current Performance

Finally, Fig. 14 shows the transfer characteristics for thetarget nMOS and pMOS devices for the nominal gate lengthof 45 nm with adjusted symmetric VTH, in linear and saturationregime.

Fig. 15 illustrates the ION/IOFF plots obtained for nMOS(diamonds) and pMOS (squares) transistors with junction


Fig. 14. n and pMOS transfer characteristics at VD = 0.05, 1 V. LG = 45 nm,W = 1 μm. Median value of 11 within-wafer measured dies.

Fig. 15. ION/IOFF (taken at drain side) obtained for nMOS (resp. pMOS)transistors, featuring an ON current of 400 (resp. 200) μA/μm at IOFF =10−10 A/μm with optimized junction profiles. Stars: data obtained forLG = 45 nm. W = 1 μm and VD = 1 V.

profiles optimized for the targeted applications, operatingin the LSTP regime. They feature an ON current of400 (resp. 200) μA/μm at IOFF = 10−10 A/μm fornMOS (resp. pMOS), in the range of targeted performancefor DRAM periphery transistors using high-k and metalgates [1].

The good process control of the n and pMOS devices isalso confirmed by the tight variability across wafer of thenormalized gate delay for ring oscillators (Fig. 16), where then and pMOS are integrated in close proximity. For a nominalgate length of 45 nm, a static power (resp. active power) of2 × 1010 W/inverter stage (resp. 10−5 W/inverter stage) isobtained at VDD = 1 V, corresponding to a gate delay ofroughly 40 ps. It should be noted that RC delay could stillbe greatly improved by polysilicon gate predoping, which has

Fig. 16. Ring active and static power oscillators delay versus gate lengthsfor VDD = 0.8 V (squares), 1 V (diamonds), 1.2 V (triangles), and 1.4 V(circles) (11 dies tested across the wafer, see inset of Fig. 4). Ring oscillatorsfeature 41 stages, fan-out = 1, and Wp /Wn = 2.

not been done in this paper in order to measure the intrinsicperformance of HKMG gate-stacks.

IV. CONCLUSION

In this paper, we present a high-k/metal-gate CMOSintegration compatible with the high thermal budget used in a2× node DRAM process flow. The metal inserted polySiliconstack is based on HfO2 coupled with Al2O3 capping on thepMOS side, and with a TiN/Mg/TiN sandwich together withAs I/I on the n side. It is demonstrated that Mg coupledwith As I/I allows reaching the work function target, whilekeeping under control gate leakage and mobility. Mg coupledwith As I/I is also remarkably stable with regard to thermalbudget, justifying its choice over more traditional La cappednMOS stacks. Reliability (N/PBTI) and matching propertiesare also in the expected range of values and are compatiblewith high volume manufacturing requirement. Using thesestacks, n and pMOS performance of 400 and 200 μA/μmat IOFF = 10−10 A/μm can be obtained. Low-power operationis also demonstrated, with much reduced gate and junctionleakages compared with logic applications.

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Romain Ritzenthaler (M’09) received the M.Sc.degree from Ecole Nationale Superieure de Physiquede Grenoble, Grenoble, France, in 2003, and thePh.D. degree from the Institut National Poly-technique de Grenoble, Grenoble, and Laboratoired’Electronique et Technologies de l’Information,Grenoble, in 2006.

He has been a Device Engineer at imec, Leuven,Belgium, since 2011, where he is involved in theprocess and characterization of DRAM peripheryand Bulk FinFET transistors.

Tom Schram received the degree in chemical engi-neering and the Ph.D. degree in engineering fromVrije Universiteit Brussel, Brussels, Belgium, in1994 and 1999, respectively.

He is currently a Senior Scientist with imec,Leuven, Belgium, working on topics related to high-k and metal gates.

Alessio Spessot received the Laurea (cum laude)degree in physics from the University of Trieste,Trieste, Italy, in 2003, and the Ph.D. degree in solid-state physics from the University of Modena andReggio Emilia, Modena, Italy, in 2006.

He has been with Micron, Catania, Italy, since2006, and with Micron, Mouscron, Belgium, since2011.

Christian Caillat received the M.S. degree in elec-tronics from the Engineering School of Electronics,Grenoble, France, the M.S. degree in microelec-tronics from Joseph Fourier University, Grenoble,in 1995, and the Ph.D. degree in microelectronicsfrom the National Polytechnic Institute, Grenoble,in 1999.

He joined Micron, Mouscron, Belgium, in 2010,where he is involved in DRAM and emergingmemories. He is currently involved in NAND Flashdevelopment with Micron, Boise, ID, USA.

Marc Aoulaiche, photograph and biography not available at the time ofpublication.


Moon Ju Cho received the Ph.D. degree in mate-rials science and engineering from Seoul NationalUniversity, Seoul, Korea, in 2007.

She joined the Reliability Group with imec, Leu-ven, Belgium, in 2007. Her current research interestsinclude the reliability of logic planar and multiple-gate field-effect transistors.

Kyoung Bong Noh, photograph and biography not available at the time ofpublication.

Yunik Son, photograph and biography not available at the time of publication.

Hoon Joo Na, photograph and biography not available at the time ofpublication.

Thomas Kauerauf received the degree in elec-trical engineering from the Technische UniversitätIlmenau, Ilmenau, Germany, in 2001, and the Ph.D.degree from Katholieke Universiteit Leuven, Leu-ven, Belgium, in 2007.

He joined imec, Leuven, Belgium, in 2006, wherehe is currently the Team leader of the FEOL reli-ability team focusing on logic device, MOL and3D architecture reliability. He has authored and co-authored more than 100 international publications.

Bastien Douhard received the master’s degree inphysics from the Facultés Notre-Dame De La Paix,Namur, Belgium, in 2005.

He has been involved in material characteriza-tion by means of (ToF)-SIMS, XPS and differentsynchrotron-based techniques.

Aftab Nazir received the M.S. degree in nano-electronics from the Royal Institute of Technol-ogy, Stockholm, Sweden, in 2008. He is currentlypursuing the Ph.D. degree with Katholieke Univer-siteit Leuven, Leuven, Belgium, and imec, Leuven.

He is involved in the characterization and TCADmodeling/calibration of advanced CMOS devices.

Soon Aik Chew received the B.E. degree inmaterials engineering from Universiti SainsMalaysia, Penang, Malaysia, in 2001, and the M.Sc.degree in electrical and electronics engineering fromUniverisiti Teknologi Petronas, Perak, Malaysia,in 2004.

He joined imec, Leuven, Belgium, in 2011, wherehe is involved in the HKMG process development.His current research interests include CMOS FEOLprocess development, FEOL reliability, and deviceoptimization.

Alexey P. Milenin received the degree and the M.S.degree in physics of materials and components ofelectronic devices from Far Eastern State Univer-sity, Vladivostok, Russia, in 1994, and the Ph.D.degree in physics of submonolayer microstructureson Si from the Institute of Automation and ControlProcesses, Vladivostok, in 2000.

He joined imec, Leuven, Belgium, in 2007, wherehe is currently a Researcher.

Efrain Altamirano-Sanchez, photograph and biography not available at thetime of publication.

Geert Schoofs, photograph and biography not available at the time ofpublication.

Johan Albert, photograph and biography not available at the time ofpublication.

Farid Sebai, photograph and biography not available at the time ofpublication.

Emma Vecchio, photograph and biography not available at the time ofpublication.

Vasile Paraschiv, photograph and biography not available at the time ofpublication.

Wilfried Vandervorst received the M.Sc. degreein electronic engineering and the Ph.D. degreein applied physics from Katholieke UniversiteitLeuven, Leuven, Belgium, in 1977 and 1983, respec-tively.

He has been with imec, Leuven, since 1984, andKatholieke Universiteit Leuven as a Professor since1990. In 2013, he was elected as a Senior ImecFellow. He is involved in advanced research onmetrology and material (interactions) for semicon-ductor technology.

Sun-Ghil Lee, photograph and biography not available at the time ofpublication.

Nadine Collaert, photograph and biography not available at the time ofpublication.


Pierre Fazan (SM’99) received the Diploma degreein physics and the Ph.D. degree from the SwissFederal Institute of Technology, Zürich, Switzerland,in 1984 and 1988, respectively.

He founded Innovative Silicon Inc., Lausanne,Switzerland, in 2002. He acted first as the companyCEO and then as CTO. In 2010, he joined MicronTechnology, Boise, ID, USA, as the Imec AssigneeTeam On-Site Manager.

Naoto Horiguchi, photograph and biography not available at the time ofpublication.

Aaron Voon-Yew Thean is the Vice Presidentof Process Technologies and the Director of theLogic Devices Research and Development Programat imec, Leuven, Belgium. He currently directs theresearch and development of device technologiesranging from ultrascaled FinFETs to III–V/Ge Chan-nels, emerging nanodevice architectures, logic spin-tronics, and novel materials.

Documents

A Low-Power HKMG CMOS Platform Compatible With Dram Node 2× and Beyond