AKSHAY KULKARNI Minneapolis, MN 55414 kulka163@umn.edu

Cell: +1 612-298-3862 LinkedIn Profile

OBJECTIVE Graduate student seeking for full-time position from Jan 2017 which utilizes my skill set in VLSI design and verification.

EDUCATION University of Minnesota, Twin Cities: Master of Science. (Electrical Engineering)

Graduating in Dec 2016 with CGPA: 3.6 / 4

Relevant Course work: VLSI Design-I (circuit design & optimization), VLSI Design Automation - II (Techniques used for logic

synthesis, verification, testing & simulation), ASIC design & verification, Advanced computer architecture (cache & memory

optimizations, ISA & branch prediction), Advanced verification (verification methodologies & UVM, assertion based tests).

Visvesvaraya Technological University: Bachelor of Engineering (Electronics & Communication).

Graduated in 2013 with CGPA: 9.07 / 10

TECHNICAL SKILLS Physical/Custom Design: Cadence Virtuoso, Calibre verification tools (DRC / LVS / PEX).

EDA tools: Synopsys: VCS, Design Compiler, IC Compiler, Formality, TetraMAX; SimpleScalar, Multi2Sim.

Circuit Simulation: Synopsys: HSPICE, Cosmos-Scope, Cadence Spectre

Scripting / Programming: Verilog, System Verilog, Perl, tcl, C, C++, Matlab

Operating System: Linux / Unix, Windows

ACADEMIC PROJECTS Verification of Floating Point Unit (FPU) coprocessor (ongoing)

Objective: UVM based layered testbench was created to perform functional verification of the FPU coprocessor.

Techniques / concepts used: UVM methodologies, OOPS, score boarding, coverage bins, constrained random verification.

Design of 16 bit Ladner-Fischer Adder circuit on cadence virtuoso 45nm process technology node.

Techniques / concepts used: grid layout for standard cells, folding / fingering, bubble shifting, cell flipping, drain sharing by using

Euler’s path, symmetric layout.

Results: Post-layout frequency = 1.05GHz at 100 deg. C with a supply voltage of 1.1V, area = 190µm2, maximum power = 0.374mW.

ASIC chip design for finding shortest path in a graph

Objective: Design & implementing an optimized architecture which provides the shortest path in a graph.

Techniques / concepts used: Bellman-Ford algorithm, logic design using verilog, synthesis flow using tcl scripting involving multi-Vt,

clock gating, flattening & structuring for Synopsys DC, constraint random verification, ATPG test pattern generation using Synopsys

TetraMAX, floor planning, automatic place & route flow using Synopsys IC Compiler.

Systematic logic synthesis of approximate circuits

Objective: Reduce the area of the circuit by approximating the circuit according to the quality constraint.

Techniques / concepts used: Netlist parsing using Perl, logic design of quality constraint circuit, finding observability don’t cares using

BDD solver, automated synthesis flow using tcl scripting for Synopsys design compiler.

Using dead blocks as virtual victim cache (ongoing)

Objective: Improved Cache efficiency (reduce miss rate) by implementing eviction mechanism for dead blocks using burst based

counting method as virtual victim cache in L1 and using individual referencing method in last level cache (LLC).

Techniques / concepts used: Implementing in Multi2Sim tool, counting-based prediction, cache bursts, adjacent set pairs.

WORK EXPERIENCE Organization: Robert Bosch Engineering and Business Solutions, India

Position: Software Engineer from Aug 2013 to July 2015 (2 years)

Responsibilities: Developed embedded solutions on topics like Power-Train Electronics in Start-stop technology, Cruise Control and

Speed Limiter technology and implementation of ‘Injection Driver’ module for a CNG retrofit project for petrol cars. Also filed a joint

patent ‘A processor to calculate speed of an engine’ which involves calculation of engine speed without the use of conventional

sensors.