ALTIUMLIVE 2018:CLOCK STRUCTURES, TIMING ANALYSIS, AND SIGNAL REQUIREMENTS FOR SYNCHRONOUS AND ASYNCHRONOUS BUSES.Max Seeley3MLead Electrical Engineer

San DiegoOct, 2018

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Length Match High Speed Buses?

Length Match

Propagation Delay Matching

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𝜀𝜀𝑟𝑟 = 𝐷𝐷𝐷𝐷 = Dielectric Constant / Relative Permittivity

If two point charges are suspended in a material of a certain relative permittivity, the effect is to decrease the electric field between the charges relative to a vacuum.In other words, the electric field is strongest in a vacuum. Increasing the Dk increases the total shunt capacitance of the transmission line.

𝑻𝑻𝑻𝑻 =𝒙𝒙 𝜺𝜺𝒓𝒓𝒄𝒄

= 𝑳𝑳𝑻𝑻𝑪𝑪𝑻𝑻

𝐿𝐿𝑇𝑇 = total series inductance𝐶𝐶𝑇𝑇 = total shunt capacitance

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𝜀𝜀𝑟𝑟 = 𝐷𝐷𝐷𝐷IMPORTANT POINTS

• Value is frequency dependent.• Depends on test method used to measure• Varies with temperature• Varies with material thickness• Varies across material due to variations in construction of material

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Wave Propagation – Velocity Through Material (mks units or milks units)

𝒗𝒗 =𝒄𝒄𝜺𝜺𝒓𝒓

𝑣𝑣 = Propagation velocity (m/s)𝑐𝑐 = speed of light in a vacuum (3 x 108 m/s = 11.8 x 1012 mil/s)

𝜀𝜀𝑟𝑟 = 𝐷𝐷𝐷𝐷 = dielectric constant / relative permittivity

𝑷𝑷𝑻𝑻 = 𝟏𝟏𝒗𝒗

= 𝜺𝜺𝒓𝒓𝒄𝒄

𝑃𝑃𝐷𝐷 =Propagation Delay (s/m or s/mil)

𝑻𝑻𝑻𝑻 = 𝑷𝑷𝑻𝑻 × 𝒙𝒙 =𝒙𝒙 𝜺𝜺𝒓𝒓𝒄𝒄

𝑥𝑥 = length of the transmission line (m or mil)

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Reference Values

𝜀𝜀𝑟𝑟 = 𝐷𝐷𝐷𝐷 = Dielectric Constant / Relative Permittivity

Material 𝜺𝜺𝒓𝒓=DkFR4 3.8 to 4.4Isola FR 370HR 4.04GETEK 3.5Nelco 4000-13 3.6Polyimide 4.2Arlon 25N 3.38Soldermask – Taiyo 4000-BN 4.71

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Example PCB Stackup

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Propagation Delay Approximations (rules of thumb!!)

Microstrip – 150ps/inch

Stripline – 180ps/inchFR4

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What it’s all about!

Clock Rising Edge

SETUP AND HOLD

What is wrong with this picture??

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Jitter and Phase Noise

Jitter: the amount by which each edge deviates from its specified temporal position (time-domain)

Phase Noise: the frequency domain representation of jitter – random fluctuations in the phase of a waveform.

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Jitter

Total Jitter = Deterministic Jitter + Random Jitter

Deterministic Jitter**: common sources are cross-talk and power integrity issues. 1. You can control deterministic jitter.2. Peak-to-peak value of deterministic jitter is finite.

Random Jitter: common sources are process variations, thermal noise, shot noise,….1. This is what is specified by component datasheets.2. YOU CANNOT CONTROL RANDOM JITTER!!3. Follows Gaussian distribution.4. UNBOUNDED!!**Deterministic jitter is not considered in static-timing analysis

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Converting Phase Noise to a Jitter Specification

The basis of this conversion is Parseval’s Theorem – the time integral of the square of a signal is equal to the frequency integral of the square of its Fourier Transform

Most data sheets give a phase noise table:

It’s complicated, but there are tools to help

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Use Online Tools• SI Labs Calculator: https://www.silabs.com/support/Pages/phase-noise-jitter-calculator.aspx• Abracon: http://www.abracon.com/phaseNoiseCalculator.php

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Converting RMS to Peak-to-Peak Jitter Value

Jitter and Bit Error Rate (BER) are intimately related

• Jitter is a source of BER• You have to accept/tolerate BER caused by jitter • Peak-to-peak jitter is determined by the tolerable level of BER caused by jitter.• Common acceptable level of BER is 10-12

• Multiply RJRMS by value N corresponding to the acceptable BER in the table on next slide

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BER and RMS Multiplier N

Previously Calculated RJRMS : 307.11 fsPeak-to-peak Jitter: 307.11 fs x 14.069 = 4.32 ps

I will use this peak-to-peak jitter value timing calculations

Source: IDT – Understanding Jitter Units – AN815

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Bus Architectures

• Common-Clock • Source-Synchronous• Incident Clocking• Embedded Clock

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D Flip-Flop

Clock D Qnext

Rising Edge 0 0

Rising Edge 1 1

Non-Rising X Q

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Common-Clock

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Common-Clock Setup

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Common-Clock Setup

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Common-Clock Calculations - SETUP

𝑇𝑇𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆 𝑀𝑀𝑀𝑀𝑟𝑟𝑀𝑀𝑀𝑀𝑀𝑀 = )𝑇𝑇𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆 𝑀𝑀𝑀𝑀𝑟𝑟𝑀𝑀𝑀𝑀𝑀𝑀 = 𝑇𝑇𝑆𝑆𝑆𝑆𝑟𝑟𝑀𝑀𝑝𝑝𝑝𝑝−𝑐𝑐𝑐𝑐𝑐𝑐 + 𝑇𝑇𝑝𝑝𝑜𝑜𝑆𝑆−𝑐𝑐𝑐𝑐𝑐𝑐−𝑟𝑟 + 𝑇𝑇𝑆𝑆𝑝𝑝−𝑐𝑐𝑐𝑐𝑐𝑐−𝑟𝑟 − 𝑇𝑇𝑗𝑗𝑀𝑀𝑆𝑆𝑆𝑆𝑆𝑆𝑟𝑟 − 𝑇𝑇𝑝𝑝𝑜𝑜𝑆𝑆−𝑐𝑐𝑐𝑐𝑐𝑐−𝑝𝑝 − 𝑇𝑇𝑆𝑆𝑝𝑝−𝑐𝑐𝑐𝑐𝑐𝑐−𝑝𝑝 − 𝑇𝑇𝑝𝑝𝑜𝑜𝑆𝑆−𝐷𝐷𝑀𝑀𝑆𝑆𝑀𝑀 − 𝑇𝑇𝑆𝑆𝑝𝑝−𝐷𝐷𝑀𝑀𝑆𝑆𝑀𝑀

𝑇𝑇𝑐𝑐𝑐𝑐𝑐𝑐−𝑜𝑜𝑐𝑐𝑆𝑆𝑠𝑠 = 𝑇𝑇𝑝𝑝𝑜𝑜𝑆𝑆−𝑐𝑐𝑐𝑐𝑐𝑐−𝑝𝑝 − 𝑇𝑇𝑝𝑝𝑜𝑜𝑆𝑆−𝑐𝑐𝑐𝑐𝑐𝑐−𝑟𝑟𝑇𝑇𝑆𝑆𝑝𝑝−𝑐𝑐𝑐𝑐𝑐𝑐−𝑜𝑜𝑐𝑐𝑆𝑆𝑠𝑠 = 𝑇𝑇𝑆𝑆𝑝𝑝−𝑐𝑐𝑐𝑐𝑐𝑐−𝑝𝑝 − 𝑇𝑇𝑆𝑆𝑝𝑝−𝑐𝑐𝑐𝑐𝑐𝑐−𝑟𝑟

𝑇𝑇𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑀𝑀𝑀𝑀𝑟𝑟𝑀𝑀𝑀𝑀𝑀𝑀 = 𝑇𝑇𝑆𝑆𝑆𝑆𝑟𝑟𝑀𝑀𝑝𝑝𝑝𝑝−𝑐𝑐𝑐𝑐𝑐𝑐 − 𝑇𝑇𝑆𝑆𝑝𝑝−𝑐𝑐𝑐𝑐𝑐𝑐−𝑜𝑜𝑐𝑐𝑆𝑆𝑠𝑠 − 𝑇𝑇𝑐𝑐𝑐𝑐𝑐𝑐−𝑜𝑜𝑐𝑐𝑆𝑆𝑠𝑠 − 𝑇𝑇𝑗𝑗𝑀𝑀𝑆𝑆𝑆𝑆𝑆𝑆𝑟𝑟 − 𝑇𝑇𝑝𝑝𝑜𝑜𝑆𝑆−𝐷𝐷𝑀𝑀𝑆𝑆𝑀𝑀 − 𝑇𝑇𝑆𝑆𝑝𝑝−𝐷𝐷𝑀𝑀𝑆𝑆𝑀𝑀

Setup Violation Compensation:1. Shorten data trace between driver and receiver (𝑇𝑇𝑆𝑆𝑝𝑝−𝐷𝐷𝑀𝑀𝑆𝑆𝑀𝑀) – Cost: Hold Margin 2. Increase length of clock trace for receiver (𝑇𝑇𝑆𝑆𝑝𝑝−𝑐𝑐𝑐𝑐𝑐𝑐−𝑟𝑟) – Cost: Hold Margin3. Decrease length of clock trace for driver (𝑇𝑇𝑆𝑆𝑝𝑝−𝑐𝑐𝑐𝑐𝑐𝑐−𝑝𝑝) – Cost: Hold Margin

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Common-Clock HOLD

Jitter and Period Not Included

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Common-Clock - HOLD

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Common-Clock Calculations - HOLD

𝑇𝑇𝐻𝐻𝑝𝑝𝑐𝑐𝑝𝑝 𝑀𝑀𝑀𝑀𝑟𝑟𝑀𝑀𝑀𝑀𝑀𝑀 = )

𝑇𝑇𝐻𝐻𝑝𝑝𝑐𝑐𝑝𝑝 𝑀𝑀𝑀𝑀𝑟𝑟𝑀𝑀𝑀𝑀𝑀𝑀 = 𝑇𝑇𝑝𝑝𝑐𝑐𝑆𝑆−𝑐𝑐𝑐𝑐𝑐𝑐−𝑝𝑝 + 𝑇𝑇𝑆𝑆𝑝𝑝−𝑐𝑐𝑐𝑐𝑐𝑐−𝑝𝑝 + 𝑇𝑇𝑝𝑝𝑜𝑜𝑆𝑆−𝐷𝐷𝑀𝑀𝑆𝑆𝑀𝑀 + 𝑇𝑇𝑆𝑆𝑝𝑝−𝐷𝐷𝑀𝑀𝑆𝑆𝑀𝑀 − 𝑇𝑇𝑝𝑝𝑜𝑜𝑆𝑆−𝑐𝑐𝑐𝑐𝑐𝑐−𝑟𝑟 − 𝑇𝑇𝑆𝑆𝑝𝑝−𝑐𝑐𝑐𝑐𝑐𝑐−𝑟𝑟

𝑇𝑇𝑐𝑐𝑐𝑐𝑐𝑐−𝑜𝑜𝑐𝑐𝑆𝑆𝑠𝑠 = 𝑇𝑇𝑝𝑝𝑜𝑜𝑆𝑆−𝑐𝑐𝑐𝑐𝑐𝑐−𝑝𝑝 − 𝑇𝑇𝑝𝑝𝑜𝑜𝑆𝑆−𝑐𝑐𝑐𝑐𝑐𝑐−𝑟𝑟𝑇𝑇𝑆𝑆𝑝𝑝−𝑜𝑜𝑐𝑐𝑆𝑆𝑠𝑠 = 𝑇𝑇𝑆𝑆𝑝𝑝−𝑐𝑐𝑐𝑐𝑐𝑐−𝑝𝑝 − 𝑇𝑇𝑆𝑆𝑝𝑝−𝑐𝑐𝑐𝑐𝑐𝑐−𝑟𝑟

𝑇𝑇𝐻𝐻𝑝𝑝𝑐𝑐𝑝𝑝 𝑀𝑀𝑀𝑀𝑟𝑟𝑀𝑀𝑀𝑀𝑀𝑀 = 𝑇𝑇𝑝𝑝𝑜𝑜𝑆𝑆−𝐷𝐷𝑀𝑀𝑆𝑆𝑀𝑀 + 𝑇𝑇𝑆𝑆𝑝𝑝−𝐷𝐷𝑀𝑀𝑆𝑆𝑀𝑀 + 𝑇𝑇𝑐𝑐𝑐𝑐𝑐𝑐−𝑜𝑜𝑐𝑐𝑆𝑆𝑠𝑠 + 𝑇𝑇𝑆𝑆𝑝𝑝−𝑜𝑜𝑐𝑐𝑆𝑆𝑠𝑠 − 𝑇𝑇ℎ𝑝𝑝𝑐𝑐𝑝𝑝

Hold Violation Compensation:1. Lengthen data trace between driver and receiver (𝑇𝑇𝑆𝑆𝑝𝑝−𝐷𝐷𝑀𝑀𝑆𝑆𝑀𝑀) – Cost: Setup Margin2. Shorten clock trace for receiver (𝑇𝑇𝑆𝑆𝑝𝑝−𝑐𝑐𝑐𝑐𝑐𝑐−𝑟𝑟) – Cost: Setup Margin3. Lengthen clock trace for driver (𝑇𝑇𝑆𝑆𝑝𝑝−𝑐𝑐𝑐𝑐𝑐𝑐−𝑝𝑝) – Cost: Setup Margin

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Combined Timing Diagram – Common Clock

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Summary - Common-Clock

• The major constraint on clock speed is the length of the data signals – in reference to SETUP requirements.

• For example –

𝑇𝑇𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑀𝑀𝑀𝑀𝑟𝑟𝑀𝑀𝑀𝑀𝑀𝑀 = 𝑇𝑇𝑆𝑆𝑆𝑆𝑟𝑟𝑀𝑀𝑝𝑝𝑝𝑝−𝑐𝑐𝑐𝑐𝑐𝑐 − 𝑇𝑇𝑆𝑆𝑝𝑝−𝑐𝑐𝑐𝑐𝑐𝑐−𝑜𝑜𝑐𝑐𝑆𝑆𝑠𝑠 − 𝑇𝑇𝑐𝑐𝑐𝑐𝑐𝑐−𝑜𝑜𝑐𝑐𝑆𝑆𝑠𝑠 − 𝑇𝑇𝑗𝑗𝑀𝑀𝑆𝑆𝑆𝑆𝑆𝑆𝑟𝑟 − 𝑇𝑇𝑝𝑝𝑜𝑜𝑆𝑆−𝐷𝐷𝑀𝑀𝑆𝑆𝑀𝑀 − 𝑇𝑇𝑆𝑆𝑝𝑝−𝐷𝐷𝑀𝑀𝑆𝑆𝑀𝑀

5 ns = 50 ns - .018 ns - .035 ns – .005 ns – 1 ns – Ttd-dataTtd-data = 43.942 nsMax Length of Trace = 244 inches using stripeline

Or let’s say we can place and route components so the data trace is 200 mil

Ttd-data = .200 inches * (180 ps/inch) = 36 psTperiod-clk = 5 ns + .018 ns + .035 ns + .005 ns + 1 ns + .036 ns = 6.094 nsFclk-max = 164 MHz

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Crystal Oscillator: Abracon AOCJYR-20.000MHz-M5627LF

Datasheet Phase Noise:

Peak-to-peak Jitter: 307.11 fs x 14.069 = 4.32 psPeriod = 50nSUnit Interval Jitter = .000086UI or .009%

Additional contributors to variations in clock period are numerous variations in stability:Stability over first year = ± 1ppmStability over 20 years = ± 3ppmReflow Shift = ± 1ppmFree-run Accuracy = ± 4.6 ppm (all causes, 20 years life, ref. to nominal frequency)Period Variation: ± .23 ps or peak-to-peak .46 psTotal Peak-to-peak jitter: 4.78 ps

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Source Synchronous

Advantages:• No theoretical limit on bus speed – there are pragmatic limits: skew, variation in propagation

delays, JITTER, ….• Propagation delay (flight time) doesn’t constrain maximum bus speed – dissipation factor, cross-

talk, jitter, overshoot, undershoot

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Source Synchronous

Jitter and Period Not Included

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Source Synchronous Timing Equations - SETUP𝑇𝑇𝑝𝑝𝑀𝑀𝑆𝑆𝑀𝑀 = 𝑇𝑇𝑝𝑝𝑜𝑜𝑆𝑆−𝑝𝑝𝑀𝑀𝑆𝑆𝑀𝑀 + 𝑇𝑇𝑆𝑆𝑝𝑝−𝑝𝑝𝑀𝑀𝑆𝑆𝑀𝑀

𝑇𝑇𝑜𝑜𝑆𝑆𝑟𝑟𝑝𝑝𝑠𝑠𝑆𝑆 = 𝑇𝑇𝑝𝑝𝑜𝑜𝑆𝑆−𝑜𝑜𝑆𝑆𝑟𝑟𝑝𝑝𝑠𝑠𝑆𝑆 + 𝑇𝑇𝑆𝑆𝑝𝑝−𝑜𝑜𝑆𝑆𝑝𝑝𝑠𝑠𝑆𝑆 + 𝑇𝑇𝑝𝑝𝑆𝑆𝑐𝑐𝑀𝑀𝑑𝑑

𝑇𝑇𝑜𝑜𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑚𝑚𝑀𝑀𝑟𝑟𝑀𝑀𝑀𝑀𝑀𝑀 = 𝑇𝑇𝑝𝑝𝑜𝑜𝑆𝑆−𝑜𝑜𝑆𝑆𝑝𝑝𝑠𝑠𝑆𝑆 + 𝑇𝑇𝑆𝑆𝑝𝑝−𝑜𝑜𝑆𝑆𝑟𝑟𝑝𝑝𝑠𝑠𝑆𝑆 + 𝑇𝑇𝑝𝑝𝑆𝑆𝑐𝑐𝑀𝑀𝑑𝑑 − 𝑇𝑇𝑝𝑝𝑜𝑜𝑆𝑆−𝑝𝑝𝑀𝑀𝑆𝑆𝑀𝑀 − 𝑇𝑇𝑆𝑆𝑝𝑝−𝑝𝑝𝑀𝑀𝑆𝑆𝑀𝑀 − 𝑇𝑇𝑜𝑜𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑇𝑇𝑣𝑣𝑠𝑠 = 𝑇𝑇𝑝𝑝𝑜𝑜𝑆𝑆−𝑝𝑝𝑀𝑀𝑆𝑆𝑀𝑀 − (𝑇𝑇𝑝𝑝𝑜𝑜𝑆𝑆−𝑜𝑜𝑆𝑆𝑟𝑟𝑝𝑝𝑠𝑠𝑆𝑆 + 𝑇𝑇𝑝𝑝𝑆𝑆𝑐𝑐𝑀𝑀𝑑𝑑)

𝑇𝑇𝑆𝑆𝑝𝑝 𝑜𝑜𝑐𝑐𝑆𝑆𝑠𝑠 = 𝑇𝑇𝑆𝑆𝑝𝑝−𝑝𝑝𝑀𝑀𝑆𝑆𝑀𝑀 − 𝑇𝑇𝑆𝑆𝑝𝑝−𝑜𝑜𝑆𝑆𝑟𝑟𝑝𝑝𝑠𝑠𝑆𝑆

𝑇𝑇𝑜𝑜𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆−𝑚𝑚𝑀𝑀𝑟𝑟𝑀𝑀𝑀𝑀𝑀𝑀 = −𝑇𝑇𝑣𝑣𝑠𝑠 − 𝑇𝑇𝑜𝑜𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆 − 𝑇𝑇𝑆𝑆𝑝𝑝−𝑜𝑜𝑐𝑐𝑆𝑆𝑠𝑠

𝑇𝑇𝑜𝑜𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑚𝑚𝑀𝑀𝑟𝑟𝑀𝑀𝑀𝑀𝑀𝑀 = 𝑇𝑇𝑜𝑜𝑆𝑆𝑟𝑟𝑝𝑝𝑠𝑠𝑆𝑆 − 𝑇𝑇𝑝𝑝𝑀𝑀𝑆𝑆𝑀𝑀 − 𝑇𝑇𝑜𝑜𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆

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Source Synchronous Timing Equations - HOLD𝑇𝑇ℎ𝑝𝑝𝑐𝑐𝑝𝑝−𝑚𝑚𝑀𝑀𝑟𝑟𝑀𝑀𝑀𝑀𝑀𝑀 = (𝑇𝑇𝑝𝑝𝑜𝑜𝑆𝑆−𝑝𝑝𝑀𝑀𝑆𝑆𝑀𝑀+𝑇𝑇𝑆𝑆𝑝𝑝−𝑝𝑝𝑀𝑀𝑆𝑆𝑀𝑀 + 𝑇𝑇𝑝𝑝𝑆𝑆𝑐𝑐𝑀𝑀𝑑𝑑) − 𝑇𝑇𝑝𝑝𝑜𝑜𝑆𝑆−𝑜𝑜𝑆𝑆𝑟𝑟𝑝𝑝𝑠𝑠𝑆𝑆 + 𝑇𝑇𝑆𝑆𝑝𝑝−𝑜𝑜𝑆𝑆𝑟𝑟𝑝𝑝𝑠𝑠𝑆𝑆 − 𝑇𝑇ℎ𝑝𝑝𝑐𝑐𝑝𝑝

𝑇𝑇𝑜𝑜𝑆𝑆𝑟𝑟𝑝𝑝𝑠𝑠𝑆𝑆 = 𝑇𝑇𝑝𝑝𝑜𝑜𝑆𝑆−𝑜𝑜𝑆𝑆𝑟𝑟𝑝𝑝𝑠𝑠𝑆𝑆 + 𝑇𝑇𝑆𝑆𝑝𝑝−𝑜𝑜𝑆𝑆𝑝𝑝𝑠𝑠𝑆𝑆 + 𝑇𝑇𝑝𝑝𝑆𝑆𝑐𝑐𝑀𝑀𝑑𝑑

𝑇𝑇𝑜𝑜𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑚𝑚𝑀𝑀𝑟𝑟𝑀𝑀𝑀𝑀𝑀𝑀 = 𝑇𝑇𝑝𝑝𝑜𝑜𝑆𝑆−𝑜𝑜𝑆𝑆𝑟𝑟𝑝𝑝𝑠𝑠𝑆𝑆 + 𝑇𝑇𝑆𝑆𝑝𝑝−𝑜𝑜𝑆𝑆𝑟𝑟𝑝𝑝𝑠𝑠𝑆𝑆 + 𝑇𝑇𝑝𝑝𝑆𝑆𝑐𝑐𝑀𝑀𝑑𝑑 − 𝑇𝑇𝑝𝑝𝑜𝑜𝑆𝑆−𝑝𝑝𝑀𝑀𝑆𝑆𝑀𝑀 − 𝑇𝑇𝑆𝑆𝑝𝑝−𝑝𝑝𝑀𝑀𝑆𝑆𝑀𝑀 − 𝑇𝑇𝑜𝑜𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆

𝑇𝑇𝑣𝑣𝑀𝑀 = 𝑇𝑇𝑝𝑝𝑜𝑜𝑆𝑆−𝑝𝑝𝑀𝑀𝑆𝑆𝑀𝑀 − 𝑇𝑇𝑝𝑝𝑜𝑜𝑆𝑆−𝑜𝑜𝑆𝑆𝑟𝑟𝑝𝑝𝑠𝑠𝑆𝑆 + 𝑇𝑇𝑝𝑝𝑆𝑆𝑐𝑐𝑀𝑀𝑑𝑑𝑇𝑇𝑆𝑆𝑝𝑝 𝑜𝑜𝑐𝑐𝑆𝑆𝑠𝑠 = 𝑇𝑇𝑆𝑆𝑝𝑝−𝑝𝑝𝑀𝑀𝑆𝑆𝑀𝑀 − 𝑇𝑇𝑆𝑆𝑝𝑝−𝑜𝑜𝑆𝑆𝑟𝑟𝑝𝑝𝑠𝑠𝑆𝑆

𝑇𝑇ℎ𝑝𝑝𝑐𝑐𝑝𝑝−𝑚𝑚𝑀𝑀𝑟𝑟𝑀𝑀𝑀𝑀𝑀𝑀 = 𝑇𝑇𝑣𝑣𝑀𝑀 − 𝑇𝑇ℎ𝑝𝑝𝑐𝑐𝑝𝑝 − 𝑇𝑇𝑆𝑆𝑝𝑝−𝑜𝑜𝑐𝑐𝑆𝑆𝑠𝑠

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Incident Clocking

• Incident clocking is a variation of source-synchronous clocking – strobe/clock and data are transmitted simultaneously.

• Receiver has built in clock/strobe delay to restore timing requirements• Clock/strobe/data have more similar transmission experience• Can reduce component complexity on “more basic” component – DDR is example.

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Embedded Clock

• Clock is embedded into data signal – USB is an example• PLL in receiver constructs clock from data.

• Requires periodic synchronization• Example - at least 10 to 15 percent of the stated peak 60 MB/s (480 Mbit/s) of Hi-Speed USB

goes to overhead

Questions?