Amorphous silicon thin-film transistors for flexible electronics

Helena Gleskova, I-Chun Cheng, Ke Long, Sigurd Wagner, James Sturm

Department of Electrical Engineering and Princeton Institute for the Science and Technology of Materials

Princeton University

Zhigang Suo

Division of Engineering and Applied Sciences, Harvard University

The work at Princeton University is supported by the United States Display Consortium.

Berkeley, April 13, 2007

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Flexible displays

Lucent, E-Ink

Encapsulation1 μm - 1 mm

Substrate10 μm - 1 mm

Transistor layer ~ 1 μmDisplay layer (LCD, PLED..)

Schematic cross section of a display

• TFT backplane is generic for all flat panel technologies• Add display layer on top

Transistor “backplane” and display “frontplane”

Amorphous silicon thin film transistorgeneric backplane

SiNx

a-Si:HCr

Substrate: glass, steel, plastic

Source DrainGate

Passivation layer

Passivation layer

Bac

kpla

ne |

Fron

tpla

ne

Gleskova H., Wagner S., IEEE Electron Device Letters 20 (1999), pp. 473-475.

• Metal versus plastic foil substrate

• a-Si:H TFT deposition temperature

• Overlay alignment

Outline

Steel versus plasticpolymer foilsubstrate

steel foil substrate

process temperature

dimensional stability

visually clear

permeable to O2 or H2O

surface roughness

inert to chemicals

electrical conductor

up to ~1000°C

> 10 times higher

no

no

rough

yes

yes

< 280°C

low

some

yes

moderate

some

no

Kattamis A.Z., Princeton UniversityCheng I-C. et al., IEEE EDL 27 (2006) 166.

Steel versus plasticpolymer foilsubstrate

steel foil substrate

process temperature

dimensional stability

visually clear

permeable to O2 or H2O

surface roughness

inert to chemicals

electrical conductor

up to ~1000°C

> 10 times higher

no

no

rough

yes

yes

< 280°C

low

some

yes

moderate

some

no

Kattamis A.Z., Princeton UniversityCheng I-C. et al., IEEE EDL 27 (2006) 166.

Ion/Ioff > 107, μlin ~ 0.45 cm2/Vs, VT ~ 2 V

Tdep = 150ºC

10-13

10-11

10-9

10-7

10-5

10-13

10-11

10-9

10-7

10-5

-10 -5 0 5 10 15 20

Dra

in-t

o-so

urce

cur

rent

Ids

(A) G

ate-to-source current Igs (A)

Gate-to-source voltage Vgs (V)

Vds = 10 V

0.1 V

Ids

Igs

Acceptable TFT performance, but …

a-Si:H TFTs made at 150ºC on Kapton

GateSource Drain

Gleskova H. et al., J. Electrochem. Society 148 (2001), pp. G370-G374. Gleskova H. et al., J. Appl. Phys. 92 (2002), pp. 6224-6229.

-10 -5 0 5 10 15 2010-12

10-11

10-10

10-9

10-8

10-7

10-6

10-5

10-4

Dra

in C

urre

nt I D

(A)

Gate-to-Source Voltage VGS (V)

Stress time: 600 sec

Initial

After stress of Vg = 20 V

Bias-stress instability of a-Si:H TFTs

Long K. et al., IEEE Electron Device Lett. 27 (2006), pp. 111-113.

⇒ Must make a-Si:H TFTs at high process temperature

[1] Gleskova, IEEE TED, 2001

[2] Cheng, IEEE Proc. Solid-State and Integrated Circuit Tech., 1998

[3] Kanicki, APL, 1993

[4] Tsukada, JAP, 1991

[5] Long, Princeton Univ.

100.1

1

10

Thre

shol

d C

hang

e Δ

VΤ (V

)

Stress Field (*107 V/m)

Stress time: 600sec

Glass (300°C-350°C) [2]

Glass (350°C) [3]

Kapton-E (150°C) [1]

Glass (300°C-360°C) [4]

Glass (150°C) [5]

a-Si TFT stability rises with process temperature

a-Si:H TFTs made on clear plastic at 280ºC

Cherenack K., Princeton University

a-Si:H TFT stability on clear plastic substrates

10

0.1

1

10

Thre

shol

d C

hang

e Δ

VΤ (V

)

Stress Field (*107 V/m)

Clear plastic (150ºC)

Clear Plastic (250ºC)Stress time: 600sec

Glass (300°C-350°C)

Glass (350°C)

Kapton-E (150°C)

Glass (300°C-360°C)

Glass (150°C)

ΔVT depends only on process T, not on substrate material

Long K. et al., IEEE Electron Device Lett. 27 (2006), pp. 111-113.

Steel versus plasticpolymer foilsubstrate

steel foil substrate

process temperature

dimensional stability

visually clear

permeable to O2 or H2O

surface roughness

inert to chemicals

electrical conductor

up to ~1000°C

> 10 times higher

no

no

rough

yes

yes

< 280°C

low

some

yes

moderate

some

no

Kattamis A.Z., Princeton UniversityCheng I-C. et al., IEEE EDL 27 (2006) 166.

thicksubstrate (large ds)

thin film (small df)Ys⋅ds versus Yf ⋅df

OTFT / polymer substrate

Ys⋅ds >> Yf ⋅df

OLED / steel substrate

Ys⋅ds >> Yf ⋅df

compliant (small Yf)stiff (large Yf)

poly-Si TFT / steel substrate

Ys⋅ds >> Yf ⋅df

stiff (large Ys)

compliant(small Ys)

a-Si TFT / polymer substrate

Ys⋅ds ≈ Yf ⋅df

Substrate stiffness affects dimensional stability

Wu C.C. et al., IEEE EDL 18 (1997) 609

Gleskova H., Princeton University Jackson T., Penn State Univ.

Wu M. et al., APL 75 (1999) 2244

3. Cr gate metal deposition

80 nm

a-Si:H TFT process

1. Front SiNx passivation2. Back SiNx passivation

SiNx

Kapton 500 nm

4. Cr gate patterning - mask 1

80 nm

Cheng I-C. et al., J. SID 13 (2005), pp. 563-568.

Cr80 nm

(n+) a-Si:H

50 nmundopeda-Si:H 200 nm

5. PECVD TFT stack: 5 W SiNx(i) a-Si:H(n+) a-Si:H

6. Cr S/D deposition

5. PECVD TFT stack: 12 W SiNx(i) a-Si:H(n+) a-Si:H

6. Cr S/D deposition

7. S/D patterning – mask 2 7. S/D patterning – mask 2

a-Si:H TFT process – cont.

SiNx

Substrate

300 nm

Cheng I-C. et al., J. SID 13 (2005), pp. 563-568.

Location of alignment marks

roll axis

mask 1 & 2

1 2

3 4

5

52 mm

52 mm

70 mm

70 mm

40 μm

feature of mask 2: S/D layer

feature of mask 1:bottom gate metal layer

Cheng I-C. et al., J. SID 13 (2005), pp. 563-568.

3 4

40 μm 40 μm

shrinkage ~ 30 μm

shrinkage ~ 28 μm

shrink. ~ 25 μm shrink. ~ 20 μm

5W gate SiNx

40 μm

1

40 μm

5

2

40 μm

~ 52 mm

~ 52 mm

~ 52 mm ~ 52 mm

Average shrinkage ~ 500 ppmCheng I-C. et al., J. SID 13 (2005), pp. 563-568.

~ 52 mm

~ 52 mm

~ 52 mm ~ 52 mm

40 μm40 μm

5

Average change ~ 100 ppm

12W gate SiNx

stretching ~ 6 μm

stretching ~ 3 μm

shrink. ~ 10 μm shrink. ~ 1 μm

40 μm

1

40 μm

40 μm

3

40 μm 40 μm

4

40 μm

40 μm

2

40 μm

Cheng I-C. et al., J. SID 13 (2005), pp. 563-568.

Substrate at room temperature Tr

Workpiece at Trwhen held flat

εs(Tr )

εf (Tr )

Workpiece at Tdafter film growth

εs(Td )

εf (Td )

Substrate at deposition temperature Td

αs (Td –Tr ) Film grown on foil substrate at elevated temperature

Film and substrate at Trif they were separated

αf (Td –Tr )

αs > αf

( ) ( )[ ]

ffss

bidrsfrs

dYdY

TTT

+

+−⋅−=

1)(

εααε sf νν =

εbiFree-standing film at Td εbi < 0

Gleskova H. et al., Appl. Phys. Lett. 88 (2006), 011905.Gleskova H. et al., in Flexible Electronics: Materials and Applications, Eds. Wong W.S., Salleo A., Springer-Verlag – to be published.

Workpiece at Trwhen released from the substrate holder

R

Workpiece at Trwhen held flat

Film release from the substrate holder

( ) ( ) ( )[ ] ⎟⎟⎠

⎞⎜⎜⎝

⎛+

⎟⎟⎠

⎞⎜⎜⎝

⎛++

⎟⎟⎟

⎠

⎞

⎜⎜⎜

⎝

⎛−

⋅+−⋅−+

=

s

f

s

f

ss

ff

ss

ff

bidrsfss

ffs

dd

dd

dYdY

dY

dY

TTdYdY

dR1

141

16

22

2

2

εααν

40 mW/cm28Bare 19 24

SiNx

Cheng I-C. et al., J. SID 13 (2005), pp. 563-568. Suo Z. et al., Appl. Phys. Lett. 74 (1999), pp. 1177-1179.

Steel foil

A rigid substrate foil is not changed much by CTE mismatchPossible to maintain reasonable overlay accuracy

-0.1

-0.05

0

0.05

0.1

-60

-40

-20

0

20

40

60

-0.01-0.00500.0050.01

150oC200oC250oC

Steel

Td

Cur

vatu

re 1

/R (c

m-1

)Substrate strain

after film deposition

εs (Tr ) (ppm

)

tensilebuilt-in stress

compressivebuilt-in stress

SiNx built-in strain

Gleskova H. et al., in Flexible Electronics: Materials and Applications, Eds. Wong W.S., Salleo A., Springer-Verlag – to be published.

Kapton foil

Stress built into the SiNx can compensate thermal mismatchand eliminate curvature and misalignment

-1

-0.5

0

0.5

1

-1000

-500

0

500

1000

-0.01-0.00500.0050.01

150oC200oC250oC

Kapton

TdC

urva

ture

1/R

(cm

-1)

Substrate strain after film

deposition εs (T

r ) (ppm)

tensilebuilt-in stress

compressivebuilt-in stress

SiNx built-in strain

Gleskova H. et al., in Flexible Electronics: Materials and Applications, Eds. Wong W.S., Salleo A., Springer-Verlag – to be published.

Summary

• Deposition at elevated temperature changes in-plane dimensions

• Changes are small if (steel) or (Kapton) 05.0<s

fdd

~ 001.0<s

fdd

~

~ 20 ppm for a-Si:H TFTs on 100-μm steel foil~ 500 ppm for a-Si:H TFTs on 100-μm Kapton foil

• CTE mismatch change in in-plane dimensions is

• Tailor built-in stress in the film to compensate CTE mismatch⇒ possible to eliminate misalignment⇒ possible to eliminate curvature of the workpiece

• Higher deposition temperatures needed for good TFT stability