A/MS Benchmark Circuits for Comparing Fault Simulation, DFT, and Test Generation Methods

Stephen Sunter and Peter Sarson

Introduction Old way of improving quality (DPPM) too slow and costly

• Test most specs, ship ICs to customers • Diagnose customer-returned ICs • Fix test and/or re-design IC

Need to improve analog quality more systematically • Measure analog fault coverage • Diagnose undetected defects • Fix test and/or DFT

Months Affects customers

Days Automatable

Purpose Facilitate systematic DFT and practical fault simulation

• Informal group of people from a dozen companies • Now IEEE Test Coverage and Access Study Group – see paper S8.1

• Needed a way to compare systematic and ad hoc techniques

Benchmark circuits • Publicly accessible – no NDA, no fee • First, develop set of mixed-signal and digital ‘standard cells’

to facilitate design of representative larger circuits • Then add those larger circuits as benchmarks

Outline Previous benchmark circuits Creating new benchmark cells Description of the cells Limitations Next steps Conclusions

Previous benchmark circuits ISCAS’85, ’89 digital benchmarks

• Only unit delays

ITC’97 analog benchmark circuits • No specs, no test limits, no logic cells, no layouts • Each cell has different process file (without corners), VDD

NanGate 45nm Open Cell Library • Typ/slow/fast (not a real process) and layouts, but only digital

Some others include analog cells too • Must sign NDA, pay fee

Creating public benchmark process Process typ/slow/fast models

• ams donated models from their 350 nm process – Dithered and rounded values to 2 significant digits – Made ‘slow’ slightly slower, ‘fast’ slightly faster – Renamed most circuit elements to generic names

• Created typical process + 4 corners

Process files typical.process

• Typical NMOS, PMOS, PNP transistors, R, C, diodes

slowN_slowP.process fastN_fastP.process • Slow NMOS, PMOS, PNP transistors Fast … • Large resistance, capacitance Small … • Typical diodes Typical diodes

slowN_fastP.process fastN_slowP.process • Slow NMOS transistor Fast NMOS • Fast PMOS transistor Slow PMOS • Typical PNP transistor, diodes, R, C Typical …

Creating benchmark cell netlists Netlists for some common A/MS functions

• ams donated netlists for 7 functions – Changed subcircuit and circuit elements to generic names

• Enhanced ITC’97 PLL – Optimized tran. sizes, added 4-bit feedback divider, re-tuned filter

Netlists for common digital functions • Created 42 logic cells

– Transistor sizes derived from those in A/MS functions – Adjusted for near-equal rise/fall delays

Creating cell specs, models Created testbenches for all at 3.3V and 27C

• Simulated all functions for ‘typical’ and 4 corners

Created specifications with upper/lower limits • Most are slightly wider than process variation, some much wider

Created Verilog models for logic cells • Delays for fanout=2 (50 fF), not load-dependent • Typical process

10 Models Name Function

NMOS1, PMOS1 n-channel and p-channel MOS transistors, BSIM3v3, level 49, VTH0 = 0.5, -0.7V typ.

PNP1 Vertical PNP bipolar transistor, β=6 typ. DNWINSUB Diode: N-well to P substrate; 1 μA knee at 620 mV, typ.

DNINSUB Diode: N+ in P substrate; 1 μA knee at 680 mV, typ. DPINSUB Diode: P+ in N-well; 1 μA knee at 700 mV, typ.

DZF1 2V Zener diode, forward biased; 1 μA knee at 400 mV, typ. DZR1 2V Zener diode, reverse biased; 10 μA knee at 1.8V, typ.

DWELL1 Substrate diode with varactor model DWELL2 Substrate diode with varactor model

6 Primitive cells Name Function

ND DNINSUB diode, 1μm2 default area NWD DNWINSUB diode, 1μm2 default area

PD DPINSUB diode, 1μm2 default area RDIFFP Resistor in P+ diffusion (slow/typ/fast)

R=126Ω/sq @0V, (JFET model) RPOLY2 Resistor in 2nd polysilicon (slow/typ/fast)

R=66Ω/sq @0V, 151Ω/sq @1V typ. CPOLY Capacitor, poly1-to-poly2 (slow/typ/fast)

<0.1% voltage dependence, ~1 fF/μm2

(prefix: PRIMITIVE_)

Name Function INV, INVX2 INVX4,

BUF, BUFX2, BUFX4 Inverters and buffers, 1X, 2X and 4X drive

BUFZ, BUFZX2, BUFZX4 Tri-state buffers, active high enable, 1X, 2X, 4X drive PUPD Pull-up/down (weak buffer)

NAN2, NAN3, NAN4, NOR2, NOR3, NOR4

2, 3, and 4-input NAND and NOR gates, 1X drive

AND2, AND2X2, AND2X4, OR2, OR2X2, OR2X4

2-input AND and OR gates, 1X, 2X and 4X drive

MUX2, XOR2 2-input multiplexer, and Exor AOI21, AOI22, AOI32, AOI33, AOI222 3~6 input and-or-invert gates OAI21, OAI22, OAI32, OAI33, OAI222 3~6 input or-and-invert gates

LAT, LATN Transparent latch, with active high or active low enable DFF, DFFN D-type flip-flop, rising or falling edge clock

DFFR, DFFRN D-type flip-flop, rising or falling edge clock, and reset DFFS, DFFSN D-type flip-flop, rising or falling edge clock, and set

Digital cells

(prefix: LOGIC_)

A/MS functions … TRAN0 TRAN1,4

Simple transmission gate 2.1 kΩ max

110 dB min. isolation at 20 MHz

8 potential defects

‘T’ transmission gate TRAN1: 4.1 kΩ max; 114 dB isolation at 20 MHz TRAN4: 1.1 kΩ max; 98 dB isolation at 20 MHz 14 potential defects

OPAMP1

Operational amplifier ±1 mV offset 2 MHz GBW in voltage follower config. 0.7 min. gain, 45° delay at 1 MHz 36 potential defects

High-speed comparator, with enable 6 ns delay for 200 mV input swing 700 μA IDD <0.01 μA IDDQ 42 potential defects

COMP1

BANDGAP1

1.2 V bandgap reference ±15 mV 60 kΩ Rout 40 μA IDDQ 46 potential defects

Power-on reset, with enable resets when 1.4V < VDD < 3.1V 100 mV min. hysteresis 50 potential defects

POR1

OSC1

Inverters for crystal oscillator, with PD 1~20 MHz 1.8 min. gain 600 μA IDD 0.01 μA IDDQ 66 potential defects

PLL1

Phase-locked loop 80~160 MHz phase-locked loop 5-inverter ring oscillator 4-bit feedback divider 598 potential defects

DAC8B1

8-bit digital-to-analog converter, resistive ladder 30 kΩ Rout ±0.25 LSB DNL ±0.4 LSB INL 1046 potential defects

ADC8B1

8-bit analog-to-digital converter, SAR 400 kHz max. sample rate 9 clock cycles per sample 3226 potential defects

Other files Testbench for each specification of each cell

• Upper and lower limits • Pin function description • SPICE format, case-insensitive • Tested using .MEAS

List of potential defects • 2 per circuit element (e.g., short+open, or increase+decrease) • Includes defect likelihood based on sq. microns (with max. value)

To access benchmark files https://www.mentor.com/products/silicon-yield/products/defectsim

Limitations No layouts or layout-extracted netlists

• No indication of potential shorts between adjacent polygons • Can inject variations instead – if detectable, then shorts detectable

Not identical to the real process • Available under NDA and fee

• Circuit that works using benchmark cells, works better in real process

• No process parameter distributions • Welcome to donate possible distributions, else assume Normal PDF

No specs for VDD ±10%, high/low temperature • Too much effort to design, validate, support

Next steps Companies and universities can donate cells

• Should include copyright, disclaimer

New cells

• SPICE or Spectre syntax • Must use same process file • Must use same cell naming convention • Must provide specs / limits for 3.3V, 27C • Must provide testbench for each spec

Next steps Add more-complex cells

• 1149.1-compliant TAP and boundary scan, 1687 SIB, etc. • Other functions: voltage regulator, mixer, RF, etc. • Other PLLs, ADCs, DACs • I2C, SPI etc. interfaces

Add circuit blocks using the cells to compare DFT techniques • With/without scan • With/without analog test bus

Conclusions A/MS benchmark circuits 2.1 (1.0 released “20 years ago today”)

• Cell library of 51 cells: 9 mixed-signal, 42 digital • 350nm process corners, specs, testbenches for 3.3 volts, 27C

https://www.mentor.com/products/silicon-yield/products/defectsim • No registration, fees, or NDA

These can facilitate better comparison of • Analog fault simulation methods, DFT/BIST techniques, tests

Systematic improvement in quality of A/MS ICs

Thank-you