An Interleaved Secondary-Side Modulated LLC Resonant Converter for Wide Output Range ...pearl.shanghaitech.edu.cn/pdf/2020zhiqing_tie.pdf · 2019. 10. 8. · LI et al.: INTERLEAVED

1124 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 67, NO. 2, FEBRUARY 2020

An Interleaved Secondary-Side ModulatedLLC Resonant Converter for Wide Output

Range ApplicationsZhiqing Li , Bo Xue, and Haoyu Wang , Senior Member, IEEE

Abstract—In this paper, an LLC type converter with twointerleaved pulsewidth modulation (PWM) rectifiers is pro-posed. Compared with the conventional LLC converter,it achieves a wide voltage regulation range independentof load. In the proposed structure, each secondary-sidePWM rectifier can operate individually. With the interleav-ing technique and shared primary-side switching network,the circuit secondary-side current stress is halved and theprimary-side current stress is largely reduced. Besides,the filter capacitor requirement is reduced. Therefore, theproposed structure is a good option for medium/high powerwide output range applications. The symmetrical LLC reso-nant tanks always operate at the resonant frequency, whichmarks the optimal operation point of the LLC resonanttank. Therefore, the conduction loss is effectively miti-gated. In the proposed converter, zero-voltage turning-ON(ZVS) of the primary-side MOSFETs can be ensured andis independent of the load. Moreover, the turning-OFF cur-rents of the primary-side MOSFETs are small and are alsoload independent. This brings the benefits of minimizedcirculating current and negligible turning-OFF loss and noMOSFET turning-OFF voltage spike. The secondary-sideauxiliary MOSFETs turn-ON with ZVS and rectifying diodesturn-OFF with limited di/dt. Topological analysis and exper-imental results of a 1.3 kW/100 kHz prototype generating230–440 V output from 390-V input are presented. Theprototype demonstrates 97.31% peak efficiency and goodperformance over a wide output range.

Index Terms—Interleaved, LLC, pulsewidth modulated(PWM), zero-voltage turning (ZVS).

I. INTRODUCTION

NOWADAYS, in wide output range applications, such asplug-in electric vehicle (PEV) charging, LLC resonant

Manuscript received June 20, 2018; revised September 30, 2018 andDecember 3, 2018; accepted January 20, 2019. Date of publicationFebruary 25, 2019; date of current version September 30, 2019. Thiswork was supported in part by the National Natural Science Foundationof China under Grant 51607113, and in part by the Shanghai Sailing Pro-gram under Grant 16YF1407600. (Corresponding author: Haoyu Wang.)

Z. Li is with the Power Electronics and Renewable Energies Labora-tory, School of Information Science & Technology, ShanghaiTech Uni-versity, Shanghai 201210, China, and also with Analog Devices Inc.,Shanghai, 201203, China (e-mail:,[email protected]).

B. Xue and H. Wang are with the Power Electronics and Re-newable Energies Laboratory, School of Information Science & Tech-nology, ShanghaiTech University, Shanghai 201210, China (e-mail:,[email protected]; [email protected]).

Color versions of one or more of the figures in this paper are availableonline at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TIE.2019.2897507

converters are widely employed with advantages of simple struc-ture, ZVS for MOSFETs, ZCS for diodes, low electromagneticinterference (EMI), and high system efficiency [1]–[3]. How-ever, the voltage regulation of LLC converters is load dependent,and is affected by circuit parameters, like resonant inductance(Lr ), magnetizing inductance (Lm ), and resonant capacitance(Cr ) [4], [5]. Besides, the light-load poor regulation occurs dueto the transformer parasitic capacitance and the junction capaci-tance of the rectifying diodes [6], [7], [8]. This brings challengesto optimally design LLC converter with wide output voltagerange. Moreover, the system efficiency of the conventional LLCconverter degrades fast when the switching frequency (fs) devi-ates away from the resonant frequency (fr ) [4], [9]. Last, but notthe least, the lowest fs of the frequency-modulated LLC con-verter corresponds to the maximum magnetic flux swing of thetransformer, which constrains the core size and power density.

Many approaches have been suggested to overcome thesedrawbacks of the conventional LLC converter, mainly by nar-rowing down the fs range. These solutions can be roughly di-vided into three categories: 1) changing the equivalent resonantparameters [11]–[16]; 2) adopting reconfigurable primary-sideswitching network or advanced control strategies [17]–[31];and 3) modifying the rectifier with passive or active methods[32]–[37].

In [10]–[12], Lr or Lm is variable; in [13], [14], Cr areswitch controlled; in [15], an auxiliary LC resonant circuit isadded. Generally, by changing the resonant parameters includ-ing Lr , Cr , and Lm , the gain curve of the LLC converter changesand extended voltage regulation range can be obtained. How-ever, extra components increase the hardware budget and intro-duce undesirable power losses.

In [16], a hybrid scheme is proposed for wide voltage gainrange, where the primary side can be configured as a full bridge(FB) or a half bridge (HB). However, in HB configuration, thecurrent stresses of the primary-side MOSFETs are increasedremarkably. To avoid the abrupt increase of the magnetizingcurrent when HB reconfigures to FB, an auxiliary bidirectionalswitch and extra transformer are added to increase Lm in [17].In [17] and [18], the primary side is either FB or HB duringone specific switching cycle, while in [18], the output volt-age is regulated by controlling the ratio of FB and HB modesover one switching period. However, the structures in [17] and[18] require large components count. In [19] and [20], adaptivelink voltage variation schemes are proposed, where the dc-link

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LI et al.: INTERLEAVED SECONDARY-SIDE MODULATED LLC RESONANT CONVERTER FOR WIDE OUTPUT RANGE APPLICATIONS 1125

voltage linearly follows the battery pack voltage. Therefore, fs

variation of the LLC converter is remarkably narrowed down.However, the boost topology is no longer a suitable solutionwhen the PFC stage requires a wide output voltage range. Thisincreases the circuit and control complexity in the PFC stage.

In [21]–[23], burst mode control strategies are proposed to im-prove light-load regulation capacity and efficiency of the LLCconverter. However, the control circuit design becomes compli-cated especially when the burst-ON/burst-OFF time is requiredto be modulated under different load conditions. Moreover, ahigh-frequency oscillation exists during the OFF state and EMIissues are introduced. In [24], symmetrical pulsewidth mod-ulated (PWM) control strategy is proposed for LLC resonantconverters under light load conditions. However, the voltageregulation range and ZVS range are both constrained by the dutycycle, which incurs a design paradox. In [25], by using asym-metric PWM (APWM) control, a higher gain can be achieved.However, since it has a long boost interval when the transformersecondary side is open circuited, the magnetizing current con-tains a large dc bias. This leads to saturation problem and in-creased conduction loss. Besides, only half of the rectifyingdiodes conduct and transfer power. This significantly increasesthe diode current stresses. These features can also be observedin [26], where an auxiliary switch is added in the primary sideto establish the boost stage.

By merging other basic converters to the primary side, thegain characteristic can also be improved. For example, in [27],a two-phase interleaved boost circuit and an FB LLC circuitare integrated by sharing the same FB; in [28], a buck–boostconverter is merged to the primary side. However, bulky induc-tors and capacitors are required. Besides, either the boost or thebuck–boost converter is controlled by the duty cycle. Hence,the root mean square (rms) value of the FB output voltage isPWM similarly to [24]. It has a negative impact on the ZVSof MOSFETs and ZCS of diodes. In [29] and [30], three-levelLLC dc/dc converters are introduced. With auxiliary MOSFETsand capacitors, voltage stresses are reduced and more degreesof freedom are offered to achieve voltage regulation. They aremore suitable for high input voltage applications with increasedhardware cost.

Some researchers focus on modifying the secondary-sidestructure of the conventional LLC converter. In [31]–[34], therectifier structures reconfigure among half-wave rectifier, full-bridge rectifier, voltage doubler, and voltage-quadrupler recti-fier. Hence, the output voltage range is extended with squeezedfs range. However, more auxiliary switches and extra con-duction losses are introduced. Besides, during the configura-tion transition process, the output voltage changes abruptly.This causes current spikes, which increases component cur-rent stresses. In [35] and [36], the FB diode rectifier is replacedwith synchronous rectifiers. Advanced active control strategiesare used to expand the voltage regulation range with a narrowfs span. In [35], an operation mode with the short-circuitedsecondary side is introduced. However, this time duration mustbe sufficiently short to maintain good circuit stability. In [36],the secondary-side phase-shift expands the duration when thesecondary side is open circuited. This introduces a boost stage

Fig. 1. Schematic of the proposed PWM interleaved LLC converter.

and similar concepts can be observed in [25] and [26]. How-ever, component current stresses and output voltage ripple areincreased.

In this manuscript, a two-phase secondary-side interleavedPWM LLC converter is proposed. The proposed topologydemonstrates benefits that include the following:

1) optimum ZVS performance over the wide output voltageand load ranges;

2) interleaving structure facilitates reduced primary-sideMOSFET turning-OFF currents;

3) relative large Lm leads to reduced circulating power andconduction losses;

4) voltage regulation independent on load condition;5) simply PWM regulation.

Therefore, the proposed structure is a good candidate formedium/high power applications with the wide output voltageand load ranges, such as PEV charging.

II. OPERATION PRINCIPLES

Fig. 1 shows the structure of the proposed converter. Theprimary side is a square-wave generator, which is fed totwo symmetrically interleaved PWM LLC phases. Those twophases merge at the output port with a shared capacitivefilter. Two interleaved phases are featured with identi-cal resonant tanks (Lr1 = Lr2 , Cr1 = Cr2 , Lm1 = Lm2). Thesecondary side is derived from the conventional voltagedoubler rectifier (D1,2 ,D4,5 , and Co1 , Co2). Two auxiliarybridges (D3 − S5 and D6 − S6) are inserted into the voltagedoubler structures to realize voltage regulation. Co1 and Co2are large filter capacitors with small voltage ripples. fr andequivalent impedance (Zr ) of the resonant tanks are defined as

fr =1

2π√

Lr1Cr1=

12π

√Lr2Cr2

(1)

Zr =√

Lr1

Cr1=

√Lr2

Cr2. (2)

Fig. 2 shows the driving signals of S1−6 and key steady-statewaveforms. fs of S1−6 is fixed and is equal to fr . As shown, S1−4operate complementarily with certain dead time. S5 and S6 aremodulated by duty cycle (D) with 180° phase shift. The turning-ON of S1,4 and S2,3 are synchronized with the turning-ON of S6and S5 , respectively. The steady-state circuit operation can be


Fig. 2. Key steady-state waveforms.

divided into ten modes. In Fig. 3, the equivalent circuits of thefirst five modes over a half switching cycle are demonstrated,and the next five modes are symmetrical.

Mode I: [t0 , t1]. Before this mode, the output capacitance(Coss) of S1,4,6 are all discharged to zero and their body diodesconduct. At t0 , S1,4,6 are turned-ON with ZVS. On the secondaryside, is1 is positive and is2 is negative. Accordingly, D1 , S5 ,D5, and S6 construct the power transfer path. Taking the upperphase as an example, ωr is the angular resonant frequency.Define two auxiliary variables VC r1 and α1 , the expressions ofir1 , vC r1 , iLm1 can be obtained

vCr 1 (t) |t0 −t1 =−nVCo 1 +VDC + VCr 1 sin [ωr (t − t0) + α1 ]

(3)

ir1 (t) |t0 −t1 =VCr 1

Zrcos [ωr (t − t0) + α1 ] (4)

iLm 1 (t) |t0 −t1 = ir1 (t0) +nVCo 1

Lm1(t − t0) . (5)

Mode II: [t1 , t2]. Upper-phase auxiliary switch S5 is turned-OFF at t1 . Since the current flowing through Lr1 should remaincontinuous; is1 commutates from S5 to D3 . Then, Vo instead

Fig. 3. Equivalent circuits of the proposed converter over half switchingperiod. (a) Mode I, t0 ≤ t < t1 . (b) Mode II, t1 ≤ t < t2 . (c) Mode III,t2 ≤ t < t3 . (d) Mode IV, t3 ≤ t < t4 . (e) Mode V, t4 ≤ t < t5 .

of Vco1 is applied to the transformer secondary side. There-fore, the duty cycle of S5,6 can regulate the output voltage.Since Vo is much larger than VC o1 , it forces is1 to decrease.Mode II ends when is1 reaches zero. Accordingly, withtwo auxiliary variables VC r2 and α2 , ir1 , vC r1 , iLm1 can beexpressed

vCr 1 (t) |t1 −t2 = −nVo + VDC + VCr 2 sin [ωr (t − t1) + α2 ](6)


ir1 (t) |t1 −t2 =VCr 2

Zrcos [ωr (t − t1) + α2 ] (7)

iLm 1 (t) |t1 −t2 = ir1 (t2) − nVo

Lm1(t2 − t) . (8)

Mode III: [t2 , t3]. After is1 becomes zero, a discontinu-ous conduction mode (DCM) occurs. The output capacitorsof upper-phase secondary-side semiconductors resonate withthe stray inductor. This DCM resonance can be observed inis1 ir1 , ir , and vDS5 . When the resonant current is damped tozero, is1 stays zero; vDS5 keeps constant; the secondary sideof the upper phase is open circuited. The dc bias of vDS5 , afterresonance, is determined by a parasitic capacitive voltage di-vider. The operation of the lower phase keeps identical to that inModes I and II. At the end of Mode III, is2 becomeszero. Accordingly, with two auxiliary variables VC r3 andα3 , ir1 , vC r1 , iLm1 can be expressed

vCr 1 (t) |t2 −t3 = VDC

+ VCr 3 sin

[ωr (t − t3)

/√Lm1 + Lr1

Lr1+ α3

]

(9)

ir1 (t) |t2 −t3 = iLm 1 (t) |t2 −t3

=VCr 3

Zr

√Lr1

Lm1 + Lr1cos

[ωr (t− t3)

/√Lm1 + Lr1

Lr1+ α3

].

(10)

Mode IV: [t3 , t4). During this mode, the secondary sides ofboth phases are open circuited. The duration of this mode isdetermined by the duty cycle and power level. When D = 1, thisduration is zero. With the decrease of D, the duration increases.The expressions of ir1 , vC r1 , iLm1 are same as those in the lastmode.

Mode V: [t4 , t5). At t4 , S1,4 are turned-OFF and Mode V begins.In this mode, S1−5 are all OFF. ir charges and discharges Coss

of S1,4 and S2,3 , respectively. Accordingly, vab decreases, andthe voltages across the upper-phase transformer secondary sidedecrease. This forces Coss of S5 to be discharged. Finally, Coss

of S2,3 is discharged to zero; vab decreases to Vi ; and Coss of S5is discharged to zero. Then, the body diodes of S2,3,5 conduct,which ensures the ZVS turning-ON at the next mode.

III. ANALYSIS OF THE PROPOSED TOPOLOGY

As shown in Figs. 1 and 2, the two secondary-side interleavedphases are identical and operate symmetrically. It should benoted that without interleaving, each single phase can operateindividually. The single-phase structure consists of: 1) primary-side full-bridge (S1−4), 2) LLC resonant tank, and 3) secondary-side active rectifier.

Multiphase interleaving technique has been widely exploredin LLC converters. It brings the benefits of reduced currentstresses, boosted power capability, and reduced conductionlosses [13], [37], [38]. However, to achieve simply parallelinterleaving operation, the components count needs to bedoubled. In the proposed structure, the two interleaved phases

share the primary-side FB. Hence, four primary-side switchesare saved and the current stresses of the primary and secondaryside devices are largely reduced. Additionally, the primary-sidecurrent becomes smoother than that in the single-phase struc-ture, which corresponds to a lower rms current and reducedconduction losses.

Meanwhile, in the conventional LLC converters, the multi-phase operation is useless to reduce filter capacitor requirementsbecause the output ripple of different phases is unchanged. Inthe proposed structure, the interleaving technique helps to halvethe output ripple magnitude and double the ripple frequency.Hence, the filter requirements are largely reduced.

In the proposed structure, the primary-side current is symmet-rical and turn-ON/OFF currents are load independent. It providesexcellent ZVS conditions for primary switches.

A. Voltage Gain

Usually, first harmonic approximation (FHA) method is usedto analyze resonant converters with frequency modulation. How-ever, FHA loses its accuracy in the proposed converter. In thispaper, a numerical method is adopted to achieve good accuracy.The primary-side switching network operates as a square wavegenerator. This square wave is fed to both phases. Thus, there isno cross-regulation issue between the two phases. Accordingly,the monolithic voltage gain of the interleaved structure is iden-tical to that of the single-phase structure with halved equivalentload resistance. Therefore, the voltage gain of the single-phasestructure is analyzed for that of the proposed interleaved con-verter. The equivalent load resistance is defined as RL . Thenormalized voltage gain is expressed as

G =nVo

VDC. (11)

The single-phase structure operation is not symmetrical. Tak-ing the upper phase as an example, in addition to the symmet-rical five operation modes described in Section II, it has threeextra operation modes (Mode VI: t5–t7 , Mode VII: t7–t8 , andMode VIII: t8–t9). Besides, for the upper phase, the circuitoperation is the same in Modes III and IV. The dead time(Modes IV and VIII) is ignored in the gain analysis. With fourauxiliary variables VC r4 , VC r5 , α4 and α5 , ir1 , vC r1 , iLm1 inModes VI, VII can be expressed

vCr 1 (t) |t5 −t7 = nVCo 2 − VDC + VCr 4 sin [ωr (t − t5) + α4 ]

(12)

ir1 (t) |t5 −t7 =VCr 4

Zrcos [ωr (t − t5) + α4 ] (13)

iLm 1 (t) |t5 −t7 = ir1 (t5) − nVCo 2

Lm1(t − t5) (14)

vCr 1 (t) |t8 −t9

= −VDC + VCr 5 sin

[ωr (t − t8)

/√Lm1 + Lr1

Lr1+ α5

]

(15)


ir1 (t) |t8 −t9 = iLm 1 (t) |t8 −t9

=VCr 5

Zr

√Lr1

Lm1 + Lr1cos

[ωr (t− t8)

/√Lm1 + Lr1

Lr1+ α5

].

(16)

Assuming D, Lm1 , Lr1 , fs , VDC , and n are preset vari-ables, there are total 14 unknowns in (3)–(10), and (12)–(16),which include VC r1 − VC r5 , α1 − α5 , VC o1 , VC o2 , the intervalsof Modes II and VII. The equations for numerical analysis areestablished based on four features:

a) Cr voltage and Lr current should be continuous betweenany adjacent stages;

b) the initial and final values of Cr voltage, Lr current, andmagnetizing current are equal over one switching period;

c) based on charge balance of Co1 and Co2 , the integral ofis1 in Mode I and Modes VII should be equal;

d) the power (Po ) transferred to the load can be expressedusing is1 .

According to features a) and b), 12 equations can be derived.According to features c) and d), the following can be derived:

n

∫ t1

t0

[ir1 (t) − iLm 1 (t)] dt = n

∫ t9

t5

[ir1 (t) − iLm 1 (t)] dt

(17)

TsPo = GVDC

∫ t2

t0

[ir1 (t) − iLm 1 (t)] dt. (18)

Therefore, there are 14 equations for the 14 unknowns, andnumerical solutions can be obtained with the help of mathe-matical tools. Equation (18) indicates how D affects the outputpower. When D increases, t2−t0 increases. This means the in-tegral interval of (18) increases. Hence, Po increases. Also, (D− 0.5) corresponds to the interval of Mode I. It determines theduration when ir1 or ir2 stay at fr as shown in (3) and Fig. 2.When D=1, Mode I lasts for a half switching period, and thecircuit works like the conventional LLC converter at fr .

The curves of voltage gain versus equivalent RL and D areplotted in Fig. 4. As shown, the normalized voltage gain variesfrom 1 to 2. Its range (1, 2) is weakly dependent of the loadconditions. Besides, the voltage across Co2 (Vco2) is a weakfunction of both the effective load resistance and the D, which isvery close to the defined normalized voltage (Vnorm = VDC/n).The voltage across Co1 (Vco1) decreases with the decrease of D.When D = 1, Vco1 is equal to Vnorm . While, when D is close to0.5, Vco1 is close to 0. Hence, the voltage stresses of Co1 andCo2 are both defined by Vnorm .

B. ZVS Performance

The ZVS performance of LLC converter is highly relevantto the magnetizing current, especially at light load conditions.In the conventional LLC converter, the magnetizing current de-pends on Vo and fr . Hence, ZVS range of the primary-sideMOSFETs is constrained. In the proposed structure with single-phase rectifier, the ac part of the magnetizing current is almostindependent of output and can be used to extend the ZVS range.

Fig. 4. Voltage gain versus D with different equivalent RL .

Fig. 5. Simulated waveforms of iD S 2 ,4 , iD 1 ,3 , vD S 2 ,4 , and vD S 1 ,3 at20% load and Vo = 335 V.

However, the primary-side current is asymmetrical, which in-duces a small dc bias passing through Lm . Due to this asym-metry, two primary-side MOSFETs may turn-OFF with a largecurrent and this might incur large switching loss.

These two drawbacks are overcome using the secondary-sideinterleaving technique. As shown in Fig. 2, iLm1 , iLm2 com-pensate with each other. The equivalent magnetizing currentpassing through primary-side MOSFETs (iLm1 − iLm2) con-tains no dc bias. Besides, ir becomes symmetrical. This ensuresthat the turning-ON and turning-OFF currents of the four primary-side MOSFETs are equal and independent of load profile. Bydesigning Lm appropriately, their turning-ON currents are de-signed to be rightly satisfied for ZVS. Hence, the circulatingcurrent is minimized. Besides, the small MOSFET turning-OFF

currents cause negligible turning-OFF losses and no MOSFETturning-OFF voltage spike.

Fig. 5 shows the simulated waveforms of iDS1,4 ,iD2,3 , vDS1,4 , and vDS2,3 with Vo = 335 V at 20% load. Theturning-ON/OFF currents of S1−4 are equal and independent ofload. They can be expressed as

ion =VDC

Lm1

Ts

2=

VDC

Lm2

Ts

2. (19)


Fig. 6. Operation during the dead time. (a) Accurate equivalent circuitof Mode V and (b) simplified circuit.

The circuit operation during dead time has been roughly dis-cussed in Mode V. Fig. 6(a) shows a more accurate equiva-lent circuit of Mode V considering diodes’ output capacitance.Fig. 6(b) corresponds to its simplified circuits. The voltagestresses of D3,6 are different from those of D1,2,4,5 . Hence,we denote the output capacitors of D1,2,4,5 and D3,6 as Cj andC ′

j , respectively. Similarly, we denote the output capacitancesof S1−4 and S5,6 as Coss and C ′

oss , respectively. At the end ofMode IV, the two-phase secondary sides are open circuited, thevoltages across two transformer secondary sides (vtx1 and vtx2)can be expressed as

vtx1 (t4) = [VDC − VCr 1 (t4)]Lm1

n (Lm1 + Lr1)<

VDC

n(20)

vtx2 (t4) = [−VDC − VCr 2 (t4)]Lm2

n (Lm2 + Lr2)>

−VDC

n.

(21)

In Mode V, S1–5 are all OFF. ir charges and discharges Coss

of S1,4 and S2,3 , respectively. vab decreases. Accordingly, vtx1and vtx2 change, which forces Cj of D4 ,5 to be dischargedand charged, respectively. Meanwhile, C ′

oss of S5 and Cj of D2are discharged; Cj of D1 and C ′

j of D3 are charged. Finally, vab

changes from VDC to−VDC and the body diodes of S1,4 conduct.C ′

oss of S5 is discharged to zero and body diode of S5 conduct.Cj of D5 is charged to Vo , while Cj of D4 is discharged to zero.Fig. 6 (b) shows the simplified circuit of Mode V. After the deadtime, vtx1 is clamped to −VC o2 , and vtx2 is clamped to VC o1 .Practically, C ′

j + C ′oss is much larger than 2Cj , in Fig. 6 (b),

the equivalent capacitance on the secondary side of the upperphase can be approximated as 2Cj . The currents in Lr1 and Lr2charge or discharge these output capacitors. To ensure ZVS

Lr1

(VD CLm 1

Ts

4

)2= Lr2

(VD CLm 2

Ts

4

)2

≥ 2CossVDC2 + Cj

[(VD C

n + VCo 2

)2+

(VD C

n + VCo 1

)2].

(22)

Fig. 7. Waveforms of ir 1 , ir 2 , ir when D is close to 0.5.

Accordingly

Lr1Ts2

16Lm12 =

Lr2Ts2

16Lm22 ≥ 2Coss +

(3 +

2n2

)Cj . (23)

Lm1 and Lm2 are viewed as current sources, Cr1 and Cr2 areviewed as voltage sources. The dead time is designed to be aquarter of the resonant period between the resonant componentsin Fig. 6(b). In the dead time, all the energy stored in Lr1 andLr2 are transferred to these output capacitors. Accordingly

tdead ≥ π

2

√Lr1

(2Cj

n2 + 2Coss

)

=π

2

√Lr2

(2Cj

n2 + 2Coss

). (24)

It should be noted, S5,6 have nature ZVS feature. As shown inFig. 2, when S5,6 are turned-ON, their channel currents remainnegative. This means that their body diodes conduct before thegate signal is applied.

C. Low Current Stresses and Conduction Loss

Naturally, interleaved structure helps to halve the secondary-side current stresses. Indeed, the primary-side current stress isalso largely reduced.

For the proposed structure, the peak current stresses occurwhen D is close to 0.5 with peak power. Assuming iLm1 andiLm2 are ignorable; Fig. 7 shows the waveforms of is1 , is2 , irin the proposed converter when D is close to 0.5. As shown,is1 has a large positive component and nearly zero negativecomponent; is2 is exactly opposite. ir is the sum of is1 andis2 , and has the same positive and negative part. To transfer thesame power by is1 or ir individually, the average value of themshould be equal. However, the peak value of is1 should be almosttwice of ir . Also, the rms value of is1 is larger than that of ir ,which corresponds to more conduction losses. Hence, with theinterleaving technique, the current stresses of the primary-sideswitches are largely reduced compared with the single-phasestructure.

The proposed converter demonstrates low conduction loss.This is mainly due to the facts that the optimal operation of theLLC tanks at fr , large Lm and small circulating current, and


Fig. 8. Waveforms of iD 1 , iD 4 , and io .

smooth current due to the symmetrical operation. As shown inFig. 7, when the duty cycle equals 0.5, ir1 and ir2 are both mainlypositive and highly asymmetric over zero. ir is ir1 subtractsir2 and becomes symmetric. To transfer the same amount ofpower, the peak resonant current of the single-phase structure isalmost twice as that of the interleaved structure. Also, the rmsvalue of ir1 is larger than that of ir , which corresponds to moreconduction losses.

D. Small Output Voltage Ripple

Two large filter capacitors (Co1 and Co2) are used to attenuatethe switching harmonics of the output voltage. Fig. 8 shows thewaveforms of iD1 , iD4 , and io of the proposed topology. Thedc component of io passes through the load and ac componentshould be filtered. As shown, io is the sum of iD1 and iD4 .While in the single-phase structure, io is only equal to iD1or iD4 . Hence, to transfer the same power, the output voltageripple of the proposed interleaved topology is halved. Besides,the frequency of io is twice of that of singular iD1 or iD4 . Hence,considering the impedance of Co1 and Co2 , to achieve the samefiltering target, Co1 and Co2 in the proposed converter can benearly a quarter of the single-phase structure.

E. Loss Analysis

Since all the MOSFETs can achieve ZVS turning-ON andall diodes can achieve ZCS turning-OFF, the main losses includeMOSFET turn-OFF loss, conduction loss, and the magnetic com-ponent loss.

1) MOSFET Turn-OFF Loss: During the turn-OFF processof MOSFET, the turn-OFF loss occurs in two segments. Duringsegment 1, vds increases from 0 V to Vds,off and the current isIoff . During segment 2, vds is Vds,off and the current decreasesfrom Ioff to 0 A. To simplify the analysis, the voltage and currentwaveforms are linearized. Therefore, the turn-OFF loss can becalculated as

Poff =Vds,off Ioff

2toverlapfs (25)

where toverlap is the total duration of two segments, fs is theswitching frequency, and Vds,off is the reverse blocking voltage.

2) Conduction Loss: On the primary side, MOSFETsS1–4 have identical rms current. On the secondary side, S5

and S6 have identical rms current. So it is with all thesecondary-side diodes. Therefore, the conduction loss can becalculated as

Pcod =∑

Ron,iI2rms,i +

∑VD,j Irms,j (26)

where Ron,j and Irms,i are the ON resistance and the rms currentof the corresponding MOSFET, respectively. VD,j and Irms,j arethe forward voltage drop and rms current of the correspondingsecondary-side diodes, respectively.

3) Magnetic Loss: The magnetic losses include two parts:coil loss and core loss. The coil loss can be calculated as

Pcoil = ρwlwAw

I2rms (27)

where ρ, lw , Aw are the parameters of the conductors and Irms isthe rms current. It should be noted that, Litz wire and interleavedwinding help to mitigate the skin effect and proximity effect.

Steinmetz’s equation is used to estimate the core loss

Pcore = KcfsαΔBβ (28)

where Kc, α and β are provided from the datasheet, and �B isthe variation of the magnetic flux. �B can be calculated basedon the Faraday law of electromagnetic induction.

F. Performance Comparison

As reviewed in the introduction, many solutions have beenproposed to improve the circuit performance of the LLC con-verter. The proposed interleaved topology is suitable for highpower applications. Hence, its counterpart is the double-phaseLLC converter. A performance comparison among some pop-ular LLC-based structures, single-phase/double-phase conven-tional LLC converters, and the proposed topology is made. Thefeatures of those topologies are summarized in Table I. Liter-ature [39] provides a computer-aided design optimization of aconventional half-bridge LLC converter with the center-tappedrectifier. It adopts PFM control. Hence, the voltage regulationrange is medium and load independent. It demonstrates goodMOSFETs’ ZVS performance, except when fs deviates abovefr at light load. For high-power applications, [40] pro-poses a double-phase conventional HB LLC converter withcenter-tapped synchronous rectification. In [27], an interleavedboost-integrated LLC converter with center-tapped rectifier isproposed. It adopts fixed-frequency PWM control and the gainrange is extremely wide. However, the ZVS performance isrelatively poor due to the boost operation and phase shift ofthe primary-side switches. In [25], APWM for hold-up time isproposed for an LLC resonant converter. Compared with con-ventional LLC converter, no structure modification is needed.The voltage regulation range is extremely wide. However, whenadopting APWM control, a large dc current passes through mag-netizing inductance. Hence, ZVS operation for one primary-sideMOSFET easily gets lost. The topology in [18] is an integra-tion of an HB LLC circuit and an FB LLC circuit. By PWMcontrol of the auxiliary bidirectional switch, the time durationof HB or FB is variable over one switching period. The nor-malized gain range varies from 1 to 2 and is load independent.When the pulsewidth of HB increases, the magnetizing current


TABLE ICOMPARISON WITH STATE OF THE ART LLC-BASED CONVERTERS

Fig. 9. Double-phase LLC converter.

decreases. Hence, the ZVS range of this converter is medium.In [29], a three-level LLC resonant converter with pulsewidthand amplitude modulation (PWAM) control is proposed. It canachieve extremely wide voltage regulation range and mediumZVS range with the modulation of switching network’s out-put. The last column in Table I demonstrates the performanceof this paper. Comparatively, since primary-side MOSFETs’turning-ON/turning-OFF currents are independent of load, theproposed interleaved topology demonstrates best ZVS perfor-mance among all those solutions. Besides, it achieves a widevoltage regulation range independent of load. It can be seen as asuitable solution for high-power, high-output applications withdouble-phase structure.

For high power applications, two parallel phases are nec-essary. Fig. 9 presents the double-phase LLC converter.This converter and the proposed converter are more suitable

TABLE IISIMULATED PERFORMANCE VERIFICATION

for high power, high input, and high output appli-cations. To make a fair performance comparison, twoconverters are designed with identical parameters: Vi =390 V, Vo = 230–440 V, Cr = 90 nF, Lr = 28.1 μH, and fs =100 kHz. The transformer turns ratio of the double-phase LLCconverter is defined as 28:12. In the proposed converter, thetransformer turns ratio is defined as 28:16. Regarding the volt-age regulation range and ZVS requirements, in double-phaseLLC converter, magnetizing inductance is 250 μH. In theproposed converter, the interleaving technique and fixed fre-quency operation offer better ZVS and voltage regulation per-formances. Hence, the magnetizing inductance can be larger.Lm1 = Lm2 = 800 μH and the equivalent magnetizing induc-tance is 400 μH.

The two converters have the same power devices count. Thesimulation results are summarized in Table II. As shown, theturning-ON currents of S1−4 (the same as S5−8) of the double-phase LLC converter depend on the output voltage and load.Hence, S1−8 may lose ZVS when fs deviates above fr at light


TABLE IIIDESIGN PARAMETERS OF THE PROTOTYPE

load. However, the turning-ON currents of S1−4 in the proposedinterleaved topology is independent of the output voltage andload condition. This can be observed in Fig. 5 and Table II.Conclusively, the ZVS performance of the proposed topology isbetter than the double-phase LLC converter.

Ir1,rms and Is1,rms correspond to the rms values of ir1 and is1(see Figs. 1 and 9). According to the comparison of Ir,rms andIs,rms , the conduction loss of the double-phase LLC converterare usually higher than that of the proposed converter. Regard-ing the transformer design, ΔB (flux density swing) should besmaller than Bsat to avoid saturation. Moreover, ΔB should alsobe constrained to control the core loss. ΔB can be calculated as

ΔB =λ

npAe< Bsat (29)

where λ is the applied volt second, np is the primary-side turnsnumber, Ae is the cross-sectional area of the magnetic core.Thus, to constrain ΔB, either the turns number or cross-sectionalarea of the transformer should be increased. Both scenarios leadto an increased transfer size.

According to the comparison of ΔB, which constrains thetransformer size, the transformer size of the double-phase LLCconverter is larger than that of the proposed converter.

Generally, the proposed topology is more suitable for highpower, wide output voltage range applications than the conven-tional double-phase LLC converter.

IV. EXPERIMENTAL RESULTS

A 1.3 kW/100 kHz prototype generating a 230–440 V out-put from the 390-V dc link is built as a proof of concept. Ta-ble III shows the circuit design parameters. Fig. 10 shows thephoto of the experimental setup. Gate driving is implementedby ADuM4135 of analog devices. The experimental waveformsare captured in Figs. 11–14 with Vo = 230, 335, and 440 V atfull-load condition.

As shown in Figs. 11–14, S1−6 are all turned-ON with zerovoltage. The turning-ON currents of S1−4 are independent ofthe output, which agrees with (19). Besides, the turning-OFF

currents of S1−4 are small and fixed. Hence, primary-sideturning-OFF losses are negligible, and there is no voltage spikeduring the turning-OFF transients. The secondary-side currentsis1 and is2 are captured in Fig. 13. After is1 and is2 decrease

Fig. 10. Photograph of the experimental setup.

Fig. 11. Steady-state experimental waveforms with Vo = 440 V, Po =1.3 kW. (a) vD S 1 ,4 , vG S 1 ,4 , ir , ir 1 , and ir 2 . (b) vD S 2 ,3 , vG S 2 ,3 , ir , ir 1 ,and ir 2 .

Fig. 12. Steady-state waveforms with Vo = 335 V, Po = 1.3 kW.(a) vD S 1 ,4 , vG S 1 ,4 , ir , ir 1 , and ir 2 . (b) vD S 2 ,3 , vG S 2 ,3 , ir , ir 1 , and ir 2 .

Fig. 13. Steady-state waveforms with Vo = 335 V, Po = 1.3 kW.(a) vD S 5 , vG S 5 , is1, and is2. (b) vD S 6 , vG S 6 , is1, and is2 .

to zero, there is a DCM resonance, which has been described

in the mode analysis. The currents passing through D1−6 arepart of is1 , is2 . There is no steep change in is1 and is2 .Hence, the diodes turning-OFF di/dt is limited. As described inSection III-C, due to the interleaving technique, the currentstress of the primary side is largely reduced than that of the sin-gle phase of the proposed secondary-modulated structure. Thiscan be observed from Fig. 14.


Fig. 14. Steady-state waveforms with Vo = 230 V, Po = 1.3 kW.(a) vD S 1 ,4 , vG S 1 ,4 , ir , ir 1 , and ir 2 . (b) vD S 2 ,3 , vG S 2 ,3 , ir , ir 1 , and ir 2 .

Fig. 15. Transient waveforms in different Vo . (a) Vo steps from 420 to366 V. (b) Vo = 440 V, RL steps from 350 to 175 Ω.

Fig. 16. Measured efficiency versus output power at different outputvoltages.

Fig. 15 demonstrates the transient waveforms of the designedprototype in different Vo . Fig. 15(a) shows Vo steps from 420 to366 V with 390 V VDC . Fig. 15(b) shows RL steps from 350 to175 Ω with 440 V Vo .

The system efficiency is defined as the output power dividedby the input power (excluding auxiliary power supply). Theexperimental data is measured by a high-precision power ana-lyzer (PPA4530 from Newtons4th Ltd.). Efficiency data ver-sus the output power of the designed prototype is recordedin Fig. 16. As shown, the prototype demonstrates good ef-ficiency performance over the wide output range. The peakefficiency reaches 97.31% at full load. The screenshot of thepower analyzer at the peak efficiency point is captured as shown

in Fig. 17. According to the loss analysis in Section III-E andthe experimental data, the power loss breakdown at the peak

Fig. 17. Screenshot of the power analyzer at the peak efficiency point.

Fig. 18. Power loss breakdown at peak efficiency point.

Fig. 19. Thermal image of the prototype with Vo = 400 V, Po = 1.3 kW.

efficiency point is calculated and plotted in Fig 18. The thermalimage of the prototype in thermal equilibrium with 400-V out-put voltage, and 1.3-kW output power is captured in Fig. 19.As shown, with 22.4 °C ambient temperature, the highesttemperature is 65.9 °C.

V. CONCLUSION

In this paper, an interleaved secondary-side modulatedfixed-frequency LLC resonant converter was proposed. Theoperation principle and detailed analysis were presented. Theanalysis was validated experimentally with a 1.3-kW prototype.


The proposed topology with customized interleaving techniquedemonstrates benefits including optimum operation of theLLC network, full-range soft switching of all semiconductordevices, wide and fixed voltage gain range independent ofload conditions, low current stresses, small filter requirements,and high system efficiency. These attractive features makethe proposed converter a good candidate for wide voltageregulation range, medium/high power applications.

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Zhiqing Li received the B.S. degree in automa-tion from Southeast University, Nanjing, China,in 2015, and the M.S. degree in microelectron-ics and solid-state electronics from the ChineseAcademy of Sciences, Shanghai Institute of Mi-crosystem and Information Technology, Shang-hai, China, in 2018.

He worked as a Graduate Research Assis-tant with the Power Electronics and RenewableEnergies Laboratory, School of Information Sci-ence and Technology, ShanghaiTech University,

Shanghai, China, from 2015 to 2018. He is currently an Application En-gineer of interface and isolation (ISO) Team with Analog Devices Inc.,Shanghai, China, where he is involved with integrated isolated products.

Bo Xue received the B.S. degree in electrical en-gineering and automation from the Hefei Univer-sity of Technology, Xuancheng, China, in 2017.He is currently working toward the M.S. degreein electrical engineering with the School of Infor-mation Science and Technology, ShanghaiTechUniversity, Shanghai, China.

His research interests include dc–dc convert-ers, fault analysis, and fault-tolerant control ofpower electronic converters.

Haoyu Wang (S’12–M’14–SM’18) received thebachelor’s degree (Hons.) in electrical engi-neering from Zhejiang University in Hangzhou,China, and the master’s and Ph.D. degrees inelectrical engineering, from the University ofMaryland, College Park, MD, USA.

He is currently a Tenure Track Assistant Pro-fessor in electrical engineering with the School ofInformation Science and Technology at Shang-haiTech University, Shanghai, China. His re-search interests include power electronics, plug-

in electric and hybrid electric vehicles, the applications of wide bandgapsemiconductors, renewable energy harvesting, and power managementintegrated circuits.

Dr. Wang is an Associate Editor for the IEEE TRANSACTIONS ON TRANS-PORTATION ELECTRIFICATION, and an Associate Editor for CPSS Transac-tions on Power Electronics and Applications.

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