Appendix Getting Started with FPGA Mapper

A p p e n d i x EG e t t i n g S t a r t e d w i t h F P G A M a p p e r

Introduction

MINC is offering support for Actel, Altera, Lattice and Xilinx devices through FPGA Mapper, which consists of PLDSynthesis II and PLSynthesizer (PLS+).

PLDSynthesis II includes optimization and place-and-route software for a wide range of CPLDs and PLDs including the AMD MACH devices, the Atmel ATV devices, Philips XPLA devices, and Cypress 374 device.

PLS+ provides state of the art synthesis and optimization for Actel, Altera, Lattice and Xilinx CPLDs and FPGAs.

The FPGA Mapper generates a NSR file which is the input to PLS+ allowing connection between PLDSynthesis II and additional support for the above mentioned devices. PLS+ outputs an optimized design for place-and-route in the appropriate format for the place-and-route software (Actel -EDIF, Altera -EDIF or AHDL, Lattice -EDIF or LDF, Xilinx -XNF). Each vendor’s place-and-route software is required.

Appendix E - PLDSynthesis II/FPGA(Version 3.8C) E-1

Appendix E - Getting Started with FPGA Mapper

Figure 1-1 is a block diagram of the FPGA Mapper system.

Figure 1-1. PLDSynthesis II/FPGA Flow Diagram

Installation and Licensing for UNIX Workstations

Quick Installation of PLS+ V3.2.3 for the UNIX Workstation

PLS+ V3.2.3 was installed during installation of PLDSynthesis II.

Licensing for UNIX Workstations

You should receive two additional licenses along with your PLDSynthesis II license with this release. The first license is the Flex-LM license (license.dat). The second license is the pls.aut file.

PLComp

.pi file PLOpt

FPGA Mapper

PLDesigner-XL

PLSynthesis+NSR Parser

target specific synthesis and mapping

netlist (EDIF, LDF, AHDL, XNF)

PL-LINK

Design Synthesis Language EDIF/VHDL/Verilog

E-2 (Version 3.8C) Appendix E

Appendix E - Getting Started with FPGA Mapper

The FLEX-LM License

Node-Specific License

If your license is tied to a specific HOSTID, please perform the following steps to start your license.

1) Login into the workstation specified by the HOSTID listed in the license file.

rlogin <license_server_name>

2) Edit the license file and change the DAEMON path to the hard path $MINC_PATH/pls/license/mincxld_pls, i.e., /usr/asyl/license/mincxld_pls.

3) Make sure all of the FEATURE lines are unwrapped. Each feature should take only one line.

4) Start Flex-LM license. You should see the license successfully started.

$MINC_PATH/pls//license/lmgrd -c <pls_license_file> &

5) Set your LM_LICENSE_FILE environment variable to point to this license file.

The pls.aut File

1) Please place this file in $MINC_PATH/pls/hlp/pls.aut. Nothing additional is needed.


Appendix E - Using PLS+ to Synthesize NSR Files and Optimize Specific Devices

U s i n g P L S + t o S y n t h e s i z e N S R F i l e s a n d O p t i m i z e S p e c i f i c D e v i c e s

Devices Supported in PLS+ V3.2.3

q Actel ACT1, ACT2/1200XL, ACT3 and Actel_3200DXThe latest Actel Designer Series is required and supported by PLS+.

q Altera All EP devices, Flash Logic (FX8160_208, FX740_44, FX740_68, FX780_84, FX780_132), MAX5000, MAX7000, MAX9000, FLEX8000.The latest Altera MAX+Plus II is required and supported by PLS+.

q Lattice GAL devices, PLSi devices (1048, 3256, 2032, 1032, 1024, 1016)The latest Lattice place-and-route software is required and supported by PLS+.

q Xilinx XC3000, XC4000(E), XC 5200, XC8000, XC7000.The latest Xilinx XACT is required and supported by PLS+.

Using FPGA Mapper to Target Actel, Altera, Lattice, or Xilinx Devices

Device Mapping from PLDSynthesis II (UNIX Workstation)

1) Run PLDSynthesis II and open the desired design file (.src, VHDL, Verilog, or EDIF).

2) Select Device | FPGA Mapping when the compilation and pre-optimization is complete. The FPGA Mapping window will open.

3) From the FPGA Mapping window, select Command Mapping from the toolbar.

4) Select the target technology for the desired device.

Actel: ACT1, ACT2/1200XL, ACT3, or Actel_3200DXAltera: EP, Flash Logic, MAX, FLEXLattice: GAL, or PLSIXILINX: XL3000, XL4000, XL4000E, XL5200

5) Select the appropriate output format. Actel: EDIF Altera: EDIF or AHDL Lattice: EDIF or LDF XILINX: XNF

6) Select the optimization criteria (area or speed).

7) Select OK to begin synthesis and optimization.

8) Select Target Option from the execute window for device specific technology for better optimi-zation. Please refer to later chapters in this guide for more detailed information.


Appendix E - CPLD Partitioners

C P L D P a r t i t i o n e r s

1. Altera Specific Mapper

1.1. Introduction

PLS+ performs synthesis and design optimization for PLD/CPLD devices from Altera. An EDIF netlist or an AHDL file is generated when mapping on EP Classic, MAX5000/7000/9000 devices. A PLDasm file is generated when mapping on FLASHLogic device family.

1.2. Area/Speed oriented mapper

For classic EP and MAX devices, PLS+ performs minimization, factorization and mapping on a virtual standard cell library. The resulting EDIF netlist or the AHDL file is processed by Altera MAXPLUS2 tool in order to generate the final programming device file.For FLASHLogic devices, PLS+ performs minimization, factorization, partitioning and mapping on a selected device. The resulting PLDasm file is processed by Altera PLDshell tool.

1.3. PLS+ / MAXPLUS2 interface

1.3.1. From PLS+ to MAXPLUS2 The output file from PLS+ is an AHDL file or an EDIF netlist, when mapping on MAX5000/7000/9000 or EP classic devices. 1.3.1.1. EDIF netlist To enter the EDIF netlist file generated by PLS+ as a project in MAXPLUS2, choose the Project Name command from the File Menu. Then enter or select the correct file name with the extension ".edf" (Important: The design name in the netlist file must be identical to the file name of the netlist). Specify also a library mapping file. By choosing the Interfaces menu, select the EDIF Netlist Reader dialogue box and click on LMF #1 option. Write or select the name "asyl.lmf". "asyl.lmf" is the library mapping file which may be located in the current directory. Usually this file is in $ASYLDIR/lib directory. In this case, specify the path to this file. Specify in User Libraries dia-logue box from the Options menu the path to "mf" directory of MAXPLUS2 files: ".../maxplus2/max2lib/mf". Select other options for logic synthesis processing: target device, timing SNF extrac-tor, EDIF output file, etc. Finally, to compile the design, click on Start. MAXPLUS2 reads the EDIF netlist, converts it to compiler netlist format, performs minimization and optimization of the design, fits it into one or more EPLDs and, finally, generates a programmer object file (.pof), an optional jedec file (.jed), a fit file (.fit), a report file (.rpt) and others. 1.3.1.2. AHDL file The AHDL file contains the Altera primitives gates. MAXPLUS2 processes this file alone. There-fore, other files or library specifications are not needed.



1.4. Command menu

Select an Altera technology (Altera_EP, Altera_MAX5000, Altera_MAX7000, Altera_9000, Altera_FLASHLogic) from the Target Technology menu within the Target Parameters in the Synthesis Parameters window.For Altera FLASHLogic you may also select Target Option button to define or modify the specific parameters. The following window is displayed for Altera FLASHLogic :

Figure 1: Target option selection for Altera FLASHLogic

1.5. On-line mode

PLS+ can also perform synthesis on Altera families using the On-line mode.

In the main menu of the PLS+, select the On-line option. The On-line command window willappear.

For synthesis from high level description, refer to the language sections of this manual for de-tails about general options.

For synthesis on Altera EP and MAX devices the following specific parameters can be de-fined:

-t Altera-tech <max5000 | max7000 | max9000 | ep>-ofmt <Output Format>

• Output format(-ofmt)

Value: EDIF or AHDL.

Default: The default value is EDIF.

For synthesis on FLASHLogic devices the following specific parameters can be defined:

-t Intel-tech intel.lib-parttype <Device name>-fillratio <Filling Ratio>-partition <Partition >-ofmt <Output Format>

• Device (-parttype)

Value: FX740_44, FX740_68, FX780_84, FX780_132

or FX8160_208.Default: The default value is FX8160_208.



• Filling Ratio (-fillratio)

Default: The default value is 100.

• Partition (-partition)

Value: YES or NO.

Default: The default value is YES.

• Output format (-ofmt)

Value: PLDasm or DSL.

Default: The default value is PLDasm.

2 Lattice Specific Mapper

2.1. Introduction

PLS+ performs Lattice ((i)pLSI, GAL) specific mapping with optional partitioning on multiple devices. A LDF, DSL or EDIF file is created for each (i)pLSI device and a PALASM or DSL file is created for each GAL device.


PLS+ performs a unique decomposition to create a speed/area trade-off. The design is expressed using lexicographic expressions and efficient decomposition into sub functions with a limited number of inputs and product terms.Once the design has been decomposed into functions that can be mapped into the Lattice architecture, PLS+ fits it in the selected device, minimizing both the number of devices and the depth of design lev-els.

2.3. Target Specific Options

Device This parameter allows the user to select a device for design mapping. The "best_fit" option permits the automatic selection of the best device for your design.

Filling Ratio For each device, a parameter allows the control of the filling ratio of the device. This may be useful for controlling the total area used inside the device, reserving space for future extensions. It speci-fies the percentage of macrocells to be used inside the device.



Partition When selecting the YES option, the device will be partitioned, if necessary on several instances of the selected device. If PALASM output format is selected, a PALASM output file is created for each device instance. When selecting the NO option, a single PALASM output file will be generated. Warning messages indicate if the output file fits in the selected device. If LDF output format is selected, a LDF output file is created for each device instance. When selecting the NO option, a single LDF output file will be generated. Warning messages indicate if the output file fits in the selected device. If DSL output format is selected, two files are created: a DSL output file, which describes the whole design, and a .pia file which describes the design partitioning (the grouping of the signals in the device instances). When selecting the NO option, a single DSL output file is generated. Warn-ing messages indicate if the output file fits in the selected device. If EDIF format is selected, a single EDIF file, on a standard virtual cell library, is created. The netlist has been carefully optimized taking into account the structure of the device. The EDIF file can be used as input of LATTICE fitter tool for JEDEC generation or simulation.

Use Macro This parameter is valid only for EDIF output format and its value is restricted to Lattice_Macros. When selecting Lattice_Macros, the adders, substractors, comparators, decoders and multiplexers are inferred and the corresponding Lattice macro blocs are instanciated in the EDIF output netlist. These macros are recognized and processed by the Lattice fitter.

2.4. Command menu

Select the Lattice technologies (Lattice_gal or Lattice_plsi) from the Target Technology menu within the Target Parameters in the Synthesis Parameters dialog box.Select the Target Option button to define or modify the specific Lattice parameters. The following win-dow is displayed.

Figure 2 Target option selection for Lattice pLSI



2.5. On-line mode

PLS+ can also perform synthesis on Lattice family using the On-line mode. In the main menuof the PLS+, select the On-line option. The On-line command window will appear.


For synthesis on Lattice devices the following specific parameters must be defined:

-t lattice-tech <plsi.lib | gal.lib>-parttype <Device name>-fillratio <Filling ratio>-partition <Partition>-ofmt <Output format>-b_lib Lattice_Macros

• Device (-parttype)Default:The largest device from the library.

• Filling Ratio (-fillratio)Default: The default value is 100.

• Partition (-partition)Value: YES or NO.

Default: The default value is YES.

• Output Format (-ofmt)Value: LDF, DSL or EDIF when mapping on (i)pLSI devices.

PALASM or DSL when mapping on GAL devices.

Default: The default value is LDF for (i)pLSI devices and PALASM for GAL devices

• Use Macro (-b_lib)Value: lattic_m.lib, valid only for EDIF output format.



3. XILINX XEPLDs Specific Mappers

3.1. Introduction

PLS+ performs a specific mapping on Xilinx 7000 families of XEPLDs. The output is eithera single XNF file or a set of PALASM files.

3.2. Speed-Area oriented mapper

For the XC7000 series, the design optimization is obtained by dedicated minimization and fac-torization techniques tailored to the features of the XC7000 series.


3.3.1. Device

This parameter is useful when generating a XNF output file and allows the user to select a de-vice for design mapping. By default, the largest device is selected.

When generating a PALASM output files, a generic XEPLD chip name is automatically gen-erated in the top level PLUSASM interconnection file (.pld).

3.3.2. Filling Ratio

This parameter allows the user to control the filling ratio of PAL devices. It is only availablewhen generating PALASM output files. It specifies the percentage of macrocells to be usedinside the device.

3.4. Command menu

Select Xilinx_7000 in the Target Technology menu within the Target Parameters in the Syn-thesis Parameters dialog box.

Select the Target Option button define or modify the specific Xilinx parameters. The followingdisplay corresponds to the Xilinx 7000 XEPLDs:

Figure 3: Target option selection for Xilinx XC7000



3.5. On-line mode

PLS+ can also perform synthesis on Xilinx using the On-line mode. In the main menu of thePLS+, select the On-line option. The On-line command window will appear.


For synthesis or optimization of Xilinx XEPLD devices, the following specific parametersmust be defined:

-t PAL -tech <PAL.lib | 7000> -parttype <Device name>-fillratio <Filling Ratio>-ofmt <Output format>

• Technology (-tech)Value: PAL.lib when generating PALASM files,

7000 when generating a XNF file.

• Filling Ratio (-fillratio)Default: The default value is 100.

Remark: Available only for PLUSASM output format.

• Device (-parttype)Default:The largest device from the library.

Remark: Available only for XNF output format.

• Output Format (-ofmt)Value: PLUSASM or XNF.


Appendix E - FPGA Target-Specific Mappers & Netlist Optimizers

s are

t cells.

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n the

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n in iza-

F P G A T a r g e t - S p e c i f i c M a p p e r s & N e t l i s t O p t i m i z e r s

1. Technology Specific Mapper

A mapper transforms a technology independent description into a technology dependent network of cells for the target technology.

The initial specification is :

Language description : NSR (through PLDSynthesis II’s NSR generator).The first synthesis step transforms the initial description into an intermediate format where macroidentified, resource folding performed and finite state machines, logic blocks, etc., identified.The mapping phase then transforms the Boolean decomposition of the logic blocks into the targe

The mappers are technology specific since they utilize the unique architectural features of the tatechnology.

2. Netlist Optimization

2.1 Introduction

Netlist optimization options are classified into two categories:Global optimization optimizes a criterion all over the netlist; for instance, the most common optiominimizes the longest path between two flip-flops or latches all over the design thus maximizing clock frequency.Dedicated optimization optimizes the network according to a constraints file which can express foinstance specific constraints on a particular pair of nets or any region of the circuit. Many other osuch as load and capacitance constraints are available.These two types of optimizations will be discussed further. In the timing constraints window showfigure 1, the optimization mode selection button allows the user to choose between a global optimtion or a local one.



Figure 1: Optimization mode selection

2.2. Global optimization

2.2.1. Global optimization optionsFor global optimization, you can specify seven options:

a) Clock_Frequency: minimization of the delay of the longest path between two latch-es or flip-flops,

b) Inpad_to_Outpad: minimization of the longest path between a primary input pad toa primary output pad,

c) Inpad_to_Setup: minimization of the longest path between a primary input pad tothe flip-flops,

d) Clock_to_Outpad: minimization of the longest path between a flip-flop to a primaryoutput pad,

e) All_to_Setup: minimization of the longest path between a primary input pad or aflip-flop to a flip-flop; this option is a combination of the options a) and c),

f) All_to_Outpad: minimization of the longest path between a primary input pad or aflip-flop to primary output pad; this option is a combination of the options b) and d),

g) Max_Delay: minimization of the longest path among all the ones mentioned above.

The user selects one of these options in the PLS+ timing constraints window as shown infigure 2.



Figure 2: Global optimization option selection

The default option is (a) (clock frequency) for sequential designs or (b) (minimization of thelongest path between a primary input pad to a primary output pad) for combinatorial designs.

2.2.2. Critical path display controlAfter global optimization, the display on the screen of the critical paths is controlled by theuser.

Number of Paths: The user may ask as a final result the display of the k most critical paths onthe screen. For this he fixes the number k.

Minimal Delay: This option allows the user to ask for the display of all paths whose delays arelarger than the specified minimal delay value.

An example of information displayed on the screen for global optimization is given in figure 3.



Area:

before combining = 92 modules after combining = 87 modules.

Estimated worst delay before combining:

Delay from INPAD to SETUP = 32.11 ns

Delay from CLOCK to SETUP = 18.39 ns <===

Delay from CLOCK to OUTPAD = 16.75 ns

Delay from INPAD to OUTPAD = 30.46 ns

Estimated worst delay after combining:

Delay from INPAD to SETUP = 27.71 ns

Delay from CLOCK to SETUP = 13.99 ns <===

Delay from CLOCK to OUTPAD = 16.75 ns

Delay from INPAD to OUTPAD = 30.46 ns

Figure 3: Information given during netlist optimization

The arrow shows the set of paths being optimized. The expanded paths are given at the end ofthe optimization as shown in figure 3.

============================================================

FINAL LIST OF CRITICAL PATHS

============================================================

*******************INPAD TO SETUP LONGEST PATH*******************

Rise delay

WORST CASE

Instance name in pin-->out pin tr total incr cell

----------------------------------------------------------------------------------------------------------

END_OF_PATH

D.MDC_2DFM1B292P R 27.71 0.00 DF1

I_9_CM8 : D0--->Y R 27.71 0.00 CM8

I_11_CM8 : S10--->Y R 27.71 5.20 CM8

MDC_2OA4A144P : D--->Y R 22.51 4.40 OA4A

MDC_2AND2B145P : A--->Y R 18.11 4.80 AND2B

MDC_AND4C212P : A--->Y R 13.31 6.40 AND4C

MDC_INBUF223P : PAD--->Y R 6.91 6.91 INBUF

DEV_0_ R 0.00 0.00

BEGIN_OF_PATH

Figure 3: Example of information given at the end of the netlist optimization



*******************CLOCK TO SETUP LONGEST PATH******************

Rise delay

WORST CASE


----------------------------------------------------------------------------------------------------------END_OF_PATH

D.MDC_2DFM1B350P0 R 13.99 0.00 DF1A

I_6_CM8 : D2--->Y R 13.99 4.40 CM8

I_5_CM8 : S01--->Y R 9.60 4.80 CM8

MDC_2DFM1B348P : CLK--->Q R 4.80 4.80 DF1

BEGIN_OF_PATH

****************CLOCK TO OUTPAD LONGEST PATH*******************

Rise delay

WORST CASE

Instance name in pin-->out pin tr total incr cel

l----------------------------------------------------------------------------------------------------------END_OF_PATH

MDWEL_ R 16.75

OUT7 : D--->PAD R 16.75 7.55 OBHS

I_3_INVA : A--->Y R 9.20 4.40 INVA

MDC_2DFM1B325P : CLK--->Q R 4.80 4.80 DF1

BEGIN_OF_PATH

******************INPAD TO OUTPAD LONGEST PATH*****************

Rise delay

WORST CASE


----------------------------------------------------------------------------------------------------------END_OF_PATH

MDCS_0_ R 30.46

MDC_OBHS247P : D--->PAD R 30.46 7.55 OBHS

MDC_AO6A160P : C--->Y R 22.91 4.40 AO6A

MDC_INV264P : A--->Y R 18.51 5.60 INV

MDC_AND3_206P : A--->Y R 12.91 6.00 AND3

MDC_INBUF223P : PAD--->Y R 6.91 6.91 INBUF

DEV_0_ R 0.00 0.00

BEGIN_OF_PATH

Figure 3: Example of information given at the end of the netlist optimization (continued)



2.3. Dedicated optimization

This second option allows the user to define specific optimization goals through a constraintfile. The following options are available. They are not exclusive.

a) fixed value of a clock frequency,

b) fixed value of the longest path of the design,

c) clock waveform,

d) setting signal arrival time at primary input pads and signal required timing at primaryoutput pads,

e) fixed value of the longest path between two internal points,

f) fixed value of a clock skew,

g) setting the maximum fanout value of a node.

2.3.1. Syntax of the constraints fileThe constraints file consists of a set of commands in a specific format. The following con-straints are defined:

2.3.1.1. Timing constraints

set_max_path_delaySet maximum delay for path between any two nodes.

set_maxdelaySet maximum delay for longest path of design.

set_arrival_timeSet arrival time at primary input(s) or at clock input of flip-flop(s) or latch(es).

set_required_timeSet required time at primary output(s) or at data input(s) of flip-flop(s).

2.3.1.2. Load and capacitance constraints

set_output_capaSet capacitance for primary output(s).

set_output_loadSet load for primary output(s).

set_input_driveSet slope for primary input(s).

set_maxfanoutSet maximum load for gate output(s).

2.3.1.3. Setup and skew constraints

set_setupSet setup for flip-flop(s) or latch(es).

set_max_skewSet skew for flip-flop(s) or latch(es).

2.3.2. Nodes identification in a netlistAll constraints except maxfanout and maxdelay refer to nodes of the design. The following no-tations are used for specify nodes:



2.3.2.1. Simple nodes

The name of a simple node is either an Instance Name or an Instance Name followed by a ":"and a Connector Name:

<Instance Name> [":" <Connector name>]

For primary input or output nodes, the name is reduced to the connector name.

For internal nodes, the name is <Instance Name> ":" <Connector name>

2.3.2.2. Hierarchical nodes

A hierarchical node is a node within a design referencing sub-modules. The name of a hierar-chical node is composed of the hierarchy path followed by a node name. A hierarchy path is asuccession of names of hierarchically embedded instances separated by a "/".

2.3.2.3. Macros

The following macros are used to define a set of nodes globally:

INPAD : all primary inputs except clock inputs.

CLOCKED : all clock inputs of flip-flops and latches.

OUTPAD : all primary outputs.

GATED : all data inputs of flip-flops and latches.

2.3.2.4. Node list

A list of nodes is just a set of node names separated by "tabs" or "spaces" and enclosed by dou-ble quotation marks.

2.3.2.5. Example

Assume the hierarchical design shown in figure 4 on the following page. The constraint filecreated for this design should start with "begin" and end with "end". Lines beginning with the’#’ character are comments. E1, CLK, I1:A and I1/I2:E1 are valid node names referencing inputsignal pins on sub-modules. The macros used to describe these nodes are:

INPAD = {E1, E2, E3}CLOCKED = {F1:CK, F2:CK}OUTPAD = {S1, S2}

A valid node list is: "F1:CK I1:A CLK".

Figure 4: Hierarchical design example

CKCLK

E3

E2

E1

D

S1

S2

I1A

B C

I2

E1 I2D

F1

D

CK

D

F2



2.3.3. Timing constraintsAll values used in these constraints are given in nanoseconds (ns).

a) set_max_path_delay <node> <node> <rise> <fall>

The set_max_path_delay constraint imposes the maximum time for a path between any pair ofnodes such as primary inputs, primary outputs, gates inputs or outputs, flip-flops inputs or out-puts, or latches inputs or outputs. A path crossing a flip-flop or a latch cannot be considered.

To avoid conflicting constraints, a single set_max_path_delay constraint is allowed in a con-straint file.

The following constraints may be declared for the example shown in figure 5:

set_max_path_delay E2 F1:D 2.2 2.9

set_max_path_delay F1:CK S2 2.2 2.9

set_max_path_delay F1:CK AND3:Y 2.2 2.9

Figure 5: Set_max_path_delay constraint

Note that in the set_max_path_delay F1:CK AND3:Y 2.2 2.9 constraint, only the path through F1-AND2-AND3 is considered as the path F1-AND1-F2-AND3 contains a flip-flop.

b) set_maxdelay <value>

The set_maxdelay constraint defines the delay of the longest path of the design.

set_maxdelay 2.9

c) set_arrival_time <node list> <rise> <fall>

The set_arrival_time constraint defines the signal arrival times at the specified inputs. The<node list> can only contain primary or clock flip-flop inputs.

set_arrival_time "E1 E2" 2.2 2.9

set_arrival_time INPAD 2.2 2.9

set_arrival_time CLOCKED 2.2 2.9

The second constraint is equivalent to: set_arrival_time "E1 E2 E3" 2.2 2.9

d) set_required_time <node list> <rise> <fall>

Using this constraint, the user can force the specified signal to arrive before a given time at aprimary input or data input of flip-flops or latches. Note that <node list> can contain only pri-mary outputs or data flip-flop inputs.

set_required_time "S1 F1" 2.2 2.9

set_required_time OUTPAD 2.2 2.9

CLK

E3

E2

E1 S1

S2F1 F2

AND1

AND2

AND3D

E4

Y D



set_required_time GATED 2.2 2.9

The second constraint is equivalent to: set_required_time "S1 S2" 2.2 2.9

2.3.4. Load and capacitance constraintsa) set_output_capa <node list> <value>

The set_output_capa constraint specifies a value for primary output capacitance, used to cal-culate delays. It is given in units compatible with those of the library (usually pico Farad - pF).If not specified, the default value is 0.

set_output_capa "S1 S2" 2.2

set_output_capa OUTPAD 2.2

b) set_output_load <node list> <value>

The set_output_load constraint defines the value of primary output load(s). This value is usedto guarantee that a gate with a sufficient drive capability is used to drive an output. If no valueis given, default is 0.

c) set_maxfanout <value>

The set_maxfanout constraint specifies a maximal value for all output loads. In some technol-ogies, a predefined value exists. In this case, the final value is the smallest of the given valueand the predefined value. This constraint results in the same behavior as the "Global MaximumFanout" parameter.

set_maxfanout 2.2

d) set_input_drive <node list> <rise> <fall>

The set_input_drive constraint specifies the drive parameter of primary input(s). This value isused when computing critical paths. If no value is given, default is 0.

Example

set_input_drive "E1 E2 E3" 2.2 2.9

set_input_drive INPAD 2.2 2.9

2.3.5. Setup and skew constraintsa) set_setup <node list> <value>

The set_setup constraint allows the specification of the time needed by a flip-flop or a latch tostabilize its input. The value is given in nanoseconds (ns). If no value is given and if the tech-nology used gives a predefined value, the final value will be the predefined value or the default0 value.

For the example shown in figure 6, the following set_up constraint may be defined:

set_setup "H1:D A/B/C:S" 2.2



Figure 6: Set_up constraint

b) set_max_skew <clock node> <rise> <fall>

The set_max_skew constraint gives the maximum difference between the arrival time at theclock input of the flip-flops and latches connected to the specified clock.

In figure 7, the following constraint indicates that the differences between the rising arrivaltimes at FF1, FF2 and FF3 clock input must be less than 2.2 ns.

set_max_skew CLK 2.2 2.9

Figure 7: Skew constraint

2.3.6. Conflicting problemsFor all constraints except set_max_path_delay, if there is a conflict, the last constraint will beused, as illustrated in the following two examples.

Example 1:

set_arrival_time "E1 E2 E3" 2.2 2.9

set_arrival_time "E2" 2.4 3.1

Since there is a conflict on E2, these set_arrival_time constraints are interpreted as:

set_arrival_time "E1 E3" 2.2 2.9

set_arrival_time "E2" 2.4 3.1

Example 2:

set_maxdelay 2.2

set_maxdelay 3.1

Since there is a conflict on max_delay constraints, only the last is valid.

set_maxdelay 3.1

CLK H1D

S C

A B

CLK

FF1 FF2 FF3



2.3.7. Using constraintsCommands that are used in a constraint file can be classified into four groups :

2.3.7.1. Global optimization commands

These commands are: set_arrival_time, set_required_time and set_maxdelay.

Examples:

set_arrival_time INPAD 0.0 0.0set_arrival_time CLOCKED 0.0 0.0set_arrival_time "D4 D5 D6" 3.5 3.6set_maxdelay 50.5set_required_time OUTPAD 50.0 51.5set_required_time GATED 45.8 47.9

The values specified in set_arrival_time and set_required_time commands are given relativeto a clock edge.

a) Using set_arrival_time and set_required_time commands

As an example, see the pipelined design shown in figure 8 and its clocking scheme. The reg-isters are activated at the rising edge.

Figure 8: A pipelined design

To optimize the sub circuit composed of Block1 separately from the complete design, the sub cir-cuit Block1 must be described in a separate netlist. The arrival and required times have to be set for the inputs and outputs of Block1, respectively. Ei are the inputs of Block1 which are driven by the outputs Qi of register Reg1. Si are the outputs of Block1 which drive the data inputs Di of register

Reg1 Reg2 Reg3

Block1 Block2

Q1

Q2

Q3

Q4

Q0 D0

D1

D2

D3

D4

D0

D1

D2

D3

D4

CLK1

CLK2

CLK3

CLK1

CLK2

CLK3

T1 T2



paga- com-

Reg2. The rising edge of CLK1 is taken as the origin of time. For each input Ei of Block1, the arrival time has to be set for the propagation delay from CLK1 to Qi (ith output of register Reg1). For Block1, the arrival time constraints are set by the commands :

set_arrival_time E0 r0 f0set_arrival_time E1 r1 f1set_arrival_time E2 r2 f2set_arrival_time E3 r3 f3set_arrival_time E4 r4 f4

The rising and falling propagation delays through register Reg1 are ri and fi, respectively. If all delays through the flip-flops of register Reg1 are equal, then the following command can be used:

set_arrival_time INPAD r f

INPAD refer to all the primary inputs Ei of Block1. For each output Si of Block1, the value of the required time has to be set to T1 - Setup (Di), where T1 is the delay between the rising edges of CLK1 and CLK2 (see figure 8) and where Setup (Di) is the set up value of the data input Di. For Block1, the required time constraints are set by the com-mands:

set_required_time S0 T1-Setup(D0) T1-Setup(D0)set_required_time S1 T1-Setup(D1) T1-Setup(D1)set_required_time S2 T1-Setup(D2) T1-Setup(D2)set_required_time S3 T1-Setup(D3) T1-Setup(D3)set_required_time S4 T1-Setup(D4) T1-Setup(D4)

If the set up values of all inputs of register Reg2 are equal, then the following command can be used:

set_required_time OUTPAD T1-Setup T1-Setup

OUTPAD refers to all the primary outputs Si of Block1. b) Using set_maxdelay command. To optimize the sub circuit containing registers Reg1 and Reg2 and logic block Block1 separately from the complete design, as shown in figure 8, this sub circuit must be described in a separate netlist. The origin of time is the rising edge of CLK1. The following command can be used to spec-ify the maximum delay from the clock input CLK1 to the data register inputs Di of Reg2:

set_maxdelay T1

In this case, this command is equivalent to the commands:

set_arrival_time CLOCKED 0.0 0.0set_required_time GATED T1 T1

Note: When the rising and falling values are equal, only one value can be specified, as in the fol-lowing commands:

set_arrival_time CLOCKED 0.0set_required_time GATED T1

2.3.7.2. Commands for local optimization These commands are :

• set_max_path_delay for path optimization,• set_max_skew for clock network optimization.

a) Using set_max_path_delay command If the designer wants to optimize only one path or a set of paths between two nodes, the protion delay through these paths has to be set for a maximum value. The set_max_path_delay



mand allows the setting of this constraint. The rest of the circuit is not optimized. An example is given in figure 9.

Figure 9: Example of a path in a design

The desired maximum propagation delay through the path given in figure 9 can be specified by the following command: set_max_path_delay G1:A G4:Y 20.0 20.0 By setting this constraint, the path starting from input A of gate G1 to output Y of gate G4 is opti-mized to obtain a propagation delay (falling and rising) less than or equal to 20.0 ns. b) Using set_max_skew command Clock skew is the difference between the longest and shortest paths of the clock network of a cir-cuit. Above a certain value the circuit may not work correctly because the flip-flops are not acti-vated simultaneously. The maximum skew allowed by the circuit can be specified by the set_max_skew command. Figure 10 gives an example of the clock network of a circuit.

d(G1:A, G4:Y)

A B C

Y

A B C

Y A B

Y

A B C

Y

G1

G2G3

G4



Figure 10: Example of a clock network

The rising and falling delays are 0.55 ns and 0.78 ns for a buffer and 0.51 ns and 0.25 ns for an inverter. The delays shown in figure 10 are:

d1 = d(CLK, b1:CLK) = (0.0, 0.0)d2 = d(CLK, b2:CLK) = (1.1, 1.56)d3 = d(CLK, b3:CLK) = (0.51, 0.25)d4 = d(CLK, b4.CLK) = (0.76, 0.76)

Therefore, the clock skew is d2 - d1 = (1.1, 1.56). If this value is too large, a clock skew value constraint can be specified using the following com-mand:

set_max_skew CLK 0.9 1.2

In this case, the clock network is reorganized to reach this constraint. 2.3.7.3. Assigning timing features to a node These commands are: set_output_capa, set_input_drive and set_setup.

For example:

set_output_capa OUTPAD 4.8set_input_drive “D4 D7 D6 D1” 1.5 1.6set_setup “LCOUNT/U0/DFM0:B LWCOUT/U1/DFM0:A”2.0

a) Using set_output_capa command

D

CLK

Q

D

CLK

Q

D

CLK

Q

D

CLK

Q

A Y

A Y

A Y

A Y

b1

b2

b3

b4

d(CLK,b1:CLK)

d(CLK, b2:CLK)

d(CLK, b3:CLK)

d(CLK, b4:CLK)

CLK



The set_output_capa command assigns a capacitance value to a primary output or a set of primary outputs. This value may be considered the environment capacitance that is driven by this output. It is used for the critical path computation. For example, the command to specify the capacitance driven by the primary output S1 of the design described in figure 11 is:

set_output_capa S1 c1+c2+c3+c4+c5+c6

Figure 11 : Example of a design environment

b) Using set_input_drive command The set_input_drive command sets the drive values of a primary input or a set of primary inputs. These values (rising and falling) are the drives of the external gate that drives this input. These val-ues are used when computing the propagation delays through the circuit. For example, the following command sets the drives of the primary input E1 of the design shown in figure 11:

set_input_drive E1 br(G1) bf(G1)

where br(G1) and bf(G1) are, respectively, the rising and the falling drives of the external gate G1. c) Using set_setup command The data input signal of a flip-flop or a latch must be maintained during at least a specific time called set up time, before the occurrence of the active edge of the clock. The set up time is illus-trated in figure 12.

Y A

B Y

Current designEnvironment

Environment

G1G2

(c1,l1)

(c2,l2) (c3,l3)

(c4,l4)

(c5,l5)

(c6,l6)

S1

E1

A

B



Figure 12 : Set up time

The set_setup command specifies the set up time value of the data input of a flip-flop or latch. This value is usually given as a timing parameter in the library. For example, for the flip-flop "b1" in fig-ure 10, the following command may be used:

set_setup b1:D 1.5

2.3.7.4. Assigning technology features to a node These commands are: set_output_load and set_maxfanout. a) Using set_output_load command The set_output_load command assigns a load value to a primary output or a set of primary outputs. This value is the external environment load that is driven by this output. It is taken into account when limiting the fanout of the gate that drives this output. For example, the following command can be used to specify the external load to the primary output S1 of the circuit shown in figure 11:

set_output_load S1 l1+l2+l3+l4+l5+l6

b) Using set_maxfanout command The set_maxfanout command allows the specification of the maximum fanout of all the gates in a design. The maximum fanout is the maximum load that can drive each gates of the circuit. If this constraint is not verified for some gates, then the load driven by these gates is reduced by using buffer insertion or gate duplication.

setup

actived edge.



For example, suppose that figure 13(a) is part of the design for which the following constraintis given:

set_maxfanout3.0

If the load of each sink is 1.0, this constraint is violated for gate G. In this case, the network isrestructured locally to verify this constraint, as shown in the figures 13(b) and 16(c).

Figure 13: Example of fanout limitation

A Y

A Y

A Y

(a) (b)

(c)

A B C

Y

G A B C

Y

G

A B C

Y

G

A B C

Y

G1

A B C

Y

G2



2.3.7.5. Complete example of a timing constraint file

A complete example of a timing constraint file is given in figure 14. It is associated with thedesign shown in figure 15.

begin

# design : topd

# technology : tgsasyl

# time unit : ns

# capacitance unit : pF

# arrival constraints

set_arrival_time INPAD 0.0 0.0

set_arrival_time CLOCKED 0.0 0.0

# required time constraints

set_required_timeOUTPAD 50.0 51.5

set_required_timeGATED 45.8 47.9

# setup info

set_setup "LWCOUNT/U0/DFMO:B

LWCOUNT/U0/DFM0:A LWCOUNT/U1/DFM0:B" 2.0

# path constraint

set_max_path_delay DCOUNT/U0/G2:A

LWCOUNT/U0/DFM0:B 20.0 20.0

set_maxfanout 16.0

set_input_driveINPAD 0.7 0.7

set_output_load OUTPAD 3.0

set_output_capa OUTPAD 4.8

set_maxdelay 50.5

set_arrival_time "D4 D5 D6" 3.5 3.6

set_input_drive "D4 D6 D7 D1" 1.5 1.6

set_output_load "S1 S2" 2.5

set_max_skew CLK 1.6

end

Figure 14 : Example of a complete timing constraint file



Figure 15 : Example of a complete design

G1

G2

DFM0

A

B

CLK

Q

U0

G1

G2

DFM0

A

B

CLK

Q

U1

G1

G2

DFM0

A

B

CLK

Q

G3

U0

S

DCOUNT

LWCOUNT

D0

D1

D3

D4

D5

D6

D7

S1

S2

TOPD

S0

S

S

A

B Y

A

B Y

CLK



3. Actel Specific Mapper and Netlist Optimizer

3.1. Introduction

PLS+ performs mapping on ACTEL devices using the full power of ACTEL multiplexer-based cells. Two representations are used for the logic blocks namely the Binary Decision Diagrams and the factor-ized trees or DAGs. For the mapping phase, Boolean matching techniques are used. These innovative methods recognize in a very short time if a Boolean function can be implemented by any configuration of an ACTEL cell. If a library is stored, the designer can ask for restriction and use only the library cells.

3.2. Area-oriented mapper

Coming from NSR, 3 optimization efforts are available: -1: Keeps the logic sharing, uses both a ROBDD mapping and a library-based mapping on the fac-tored trees of DAGs and takes the best solution. -2: Adds to effort 1 collapsing techniques (modification on the logic sharing) and takes the best solution. -3: Adds a Boolean matching-based mapping to effort 2 and takes the best solution.

3.3. Speed-oriented mapper

3 optimization efforts are available: -1: Keeps the logic sharing and takes the best solution between a ROBDD mapping and a library-based speed mapping. -2: Same as effort 1, but uses a Boolean matching-based mapping. This usually results in better solutions at the cost of CPU increase. -3: Adds collapsing techniques (modification of the logic sharing) and several factoring options.

3.4. Area oriented netlist optimizer

The area-oriented netlist optimizer reoptimizes the logic blocks through several iterations.Three optimization efforts are available.

- 0: merges all combinational blocks, keeps the logic sharing and performs an area oriented, Bool-ean Matching-based mapping. - 1: merges all combinational blocks, applies both ROBDD mapping and Boolean Matching based mapping on factorized trees, preserves logic sharing and takes the best solution. - 2: merges all combinational blocks and adds collapsing techniques to effort 1 in order to explore different logic sharings.

3.5. Speed-oriented netlist optimizer

For speed oriented netlist optimizer, five optimization efforts are available: - 0: (LOW): does not modify the logic sharing, does a direct library based mapping on the whole netlist. - 1: detects the critical region and does not modify the logic sharing of the critical region but re-



synthesizes each logic portion of this critical region using a Boolean Matching technique. - 2: begins by optimizing the whole network for area using a Boolean Matching technique and only in a second step, detects the critical region, modifies its logic sharing, re-synthesizes and re-maps. - 3: detects the critical region, modifies its logic sharing, re-synthesizes and re-maps using a Bool-ean Matching technique. - 4 (HIGH): selects the best result out of optimization effort 2 and 3.

Do not run optimization effort 4 if you have already run effort 2 and 3.

3.6. Additional passes (A, B, C ...)

5 additional trials are available: A- implementing speed oriented netlist optimization effort 2 using library based mapping instead of Boolean matching. B- exploring alternate factorization techniques. C- canceling the sequential remapping. D- implementing speed oriented netlist optimization effort 4 using library based mapping instead of Boolean matching. E- flattening of XOR gates and multiplexors.

3.7. Target specific options

3.7.1. Use Library Cells Only This option forces the mapper to use only library cells and not CM8 cells. By default this option is set to No.

3.7.2 Add I/O Buffers This option inserts automatically I/O buffers for all ACTEL technologies.

3.7.3. Global Maximum Fanout This option sets the fanout of all gates below a given value. If the parameter is set to 999, no limita-tion of fanout is achieved. The default value is 10 for ACT1, 16 for ACT2/1200XL, ACT3 and 3200DX.

3.7.4. I/O Directive File The user can define some specific constraints using the I/O directive file. In this file, several possi-bilities are available: a) set a specific maximum fanout on an input pin, b) replace an I/O buffer by another on a pin, c) allows efficient handling of complex ACT3 I/Os.



The specification of the I/O directive file is given below in figure 16: # ... /* comment line */

BEGIN VERSION <number>

INPORTMAXFANOUT <pin_name> <maxfanout_value>

OUTPORTMINLOAD <pin_name> <minload_value>

INSERTIO <cell_name> <pin_name>

BEGINCHIPA3

CHIPA3SIG <pin_name>

CHIPA3RST <pin_name>

CHIPA3CLK <new_pin_name>

CHIPA3PCL <new_pin_name>

CHIPA3DFF <TRUE/FALSE>

CHIPA3CLR <TRUE/FALSE>

CHIPA3SLW <TRUE/FALSE>

ENDCHIPA3

END

Figure 16: I/O directive file description

All the values after the word END are not considered. See the "IO directive file" section for details.

3.8. Command menu Select an Actel technology (Actel_ACT1, Actel_ACT2/1200XL, Actel_ACT3, Actel_3200DX) from the Target Technology menu within the Target Parameters in the Synthesis Parameters window as shown in figure 17.

Figure 17: Actel target option selection



Select the Target Option button to define or modify the specific Actel parameters. The follow-ing windows are displayed for ACT1, ACT2/1200XL, ACT3 and 3200DX:

Figure 18: Target technology options available for Actel ACT1, ACT2/1200XL, ACT3 or 3200DX



3.9. On-line mode

PLS+ can also perform synthesis on Actel families using the On-line mode. In the main menu of the PLS+, select the On-line option. The On_line command window will appear. For synthesis from high level description, refer to the language parts of this manual for details about general options.For synthesis or optimization of Actel designs, the following parameters can be defined in the com-mand line :

-t Actel-tech <Actel families>-cell <Use library cells only> -iobuf <Add I/O buffers>-maxfanout <Maximum fanout for a module>-scf <I/O directive file>-b_lib <Macro file name>

• Target series (-tech)

Value:ACT1, ACT2, ACT3 or 3200DX

• Use Library Cells Only (-cell)

Value: Yes or No

Default: No.

• Add I/O buffers (-iobuf)

Value: Yes or No.

Default: Yes.

• Global Maximum Fanout (-maxfanout)

Value: integer value.

Default: 10 for ACT1, 16 for ACT2/1200XL, ACT3 and 3200DX.

• I/O Directive File (-scf)

See the next section "I/O directive file", for details.

• Use Macro (-b_lib)

Value: act3_m.lib, actgen_m.lib (for ACT3)act2_m.lib, actgen_m.lib (for ACT2/1200XL and 3200DX)act1_m.lib (for ACT1)

Default: Macro+. By default, the PLS+ macro block generators will be used.



3.10. I/O directive file.

The user can specify constraints using the I/O directive file. The specification of this file is given below:

# ... /* comment line */

BEGIN VERSION <number>

INPORTMAXFANOUT <pin_name> <maxfanout_value>

OUTPORTMINLOAD <pin_name> <minload_value>

INSERTIO <cell_name> <pin_name>

BEGINCHIPA3

CHIPA3SIG <pin_name>

CHIPA3RST <pin_name>

CHIPA3CLK <new_pin_name>

CHIPA3PCL <new_pin_name>

CHIPA3DFF <TRUE/FALSE>

CHIPA3CLR <TRUE/FALSE>

CHIPA3SLW <TRUE/FALSE>

ENDCHIPA3

END

Figure 19: I/O directive file description

All values after the word END are not considered. All the values are optional.Description of the values :- INPORTMAXFANOUT <pin_name> <maxfanout_value>When a primary input port and a maxfanout value are defined, the system adds a tree of buffers so that the fanout of the port is less than the given value.- OUTPORTMINLOAD <pin_name> <minload_value>If the user wants to optimize a hierarchical design part by part, this option can be used. The Minload value of the output port assures that this port has an equal fanout in the other part of the netlist. If the gate connected to this output port cannot drive the Minload value, a buffer is inserted.- INSERTIO <cell_name> <pin_name>This option is used to replace an I/O buffer at an input port with name "pin_name" by another I/O buffer with name "cell_name". This option is limited to single input-output I/O buffers.- BEGINCHIPA3 ... ENDCHIPA3This section is allowed only with ACT3 technology. Between these two words, the user can specify some special values to perform Complex ACT3 I/Os absorption. If the circuit already has the I/O Cells IOPCLBUF and IOCLKBUF, no absorption is done.- CHIPA3SIG<pin_name>Define the clock signal of the sequential elements to be absorbed. This port will be connected to the I/O module IOCLKBUF, unless this port is already connect to a "Dont touch" I/O cell. If not set, it uses the value given by CHIPA3RST.- CHIPA3RST <pin_name>Define the Reset or Preset signal of the sequential elements to be absorbed. The sequential elements connected to this signal will be absorbed if possible and connected to the I/O module IOPCLBUF. If neither CHIPA3SIG nor CHIPA3RST are specified and there is only one clock network, then select CHIPA3RST or no absorption will be performed.- CHIPA3CLK <new_pin_name>



- CHIPA3PCL <new_pin_name>Define the sequential elements that cannot be absorbed. They will be connected to the new names given by these parameters. If no value is given, a random name will be given to the ports.- CHIPA3DFF <TRUE/FALSE>This parameter defines the type of flip-flops to be absorbed. If it set to TRUE, select the flip-flops with no CLR or PRE (IOPCL connector of the Complex I/Os is then connected to VCC). If FALSE, use flip-flops with CLR or PRE since these two types of flip-flops cannot be in the same network.- CHIPA3CLR <TRUE/FALSE>This parameter is used when CHIPA3DFF is set to TRUE. This allows the system to use the Complex ACT3 I/Os with CLR (if TRUE) or with PRE (if FALSE).- CHIPA3SLW <TRUE/FALSE>This parameter is used to select the Slew type of the Complex ACT3 I/Os. It is available only if CHIPA3DFF is TRUE.

4. Altera Specific Mapper

4.1. Introduction

PLS+ performs Altera specific mapping with automatic partitioning on multiple devices. An AHDL file is created when mapping on FLEX8000 devices.


PLS+ performs a unique decomposition to create a speed/area trade-off. For FLEX8000 synthesis, the design is expressed using ROBDD diagrams and an efficient decomposition into sub functions with a limited number of inputs respecting the target device specification is performed.


Flex module decomposition This option allows the system to perform a direct synthesis on the structure of FLEX8000 internal cells (LCELL). The resulting AHDL file may contain the LCELL modules; and, therefore, the file may be processed by selecting the WYSIWYG option of MAXPLUS2 from the Logic Synthesis dialogue box. The AHDL file may also be generated without the LCELL modules and, in this case, MAXPLUS2 performs the complete synthesis flow.

4.4. PLS+ / MAXPLUS2 interface

4.4.1. From PLS+ to MAXPLUS2 The output file from PLS+ is an AHDL file, when mapping on Altera FLEX8000 devices. The AHDL file contains the Altera primitives gates. MAXPLUS2 processes this file alone. There-fore, other files or library specifications are not needed.



4.5. Command menu

Select the Altera_FLEX technology from the Target Technology menu within the Target Parameters in the Synthesis Parameters window.Select the Target Option button to define or modify the specific Altera FLEX8000 parameters. The fol-lowing window is displayed for FLEX8000:

Figure 20: Target option selection for Altera FLEX

5. XILINX Specific Mappers and Netlist Optimizers

5.1. Introduction

PLS+ performs a specific mapping on Xilinx 3000, 4000, 4000E and 5200 families of FPGAs and 7000 families. PLS+ infers XBLOX elements. For FPGAs, the output is either a single or a set of XNF files ready for processing by the Xilinx place and route tools. For XEPLD devices, the output is either a sin-gle XNF file or a set of PLUSASM files.

5.2. Area oriented mapper

For the XC3000 series, 2 optimization efforts are available:- effort 1: Boolean blocks are represented by factorized expressions and merged. An area oriented map-ping is then applied.- effort 2: Boolean blocks are represented successively by factorized expressions, lexicographical expressions (MINC-IST patent) and ROBDDs. The best result after mapping is selected.

For the XC4000 and XC5200 series, 2 optimization efforts are available:- effort 1: Boolean blocks are merged, represented by ROBDD and factorized expressions. An area ori-ented mapping is then applied.- effort 2: more efforts are spent on the factorized expressions by using several collapsing techniques.Notice that for the XC5200 series, the XC4000 mapping is extended by catching more specifically the multiplexor on top of the LUTs.For the XC4000E series, the mapping takes advantage of the added accessibility of the H function that can increase design density versus 4000 families.



5.3. Speed oriented mapper

For the XC3000, XC4000, XC4000E and XC5200, the speed oriented mapper minimize the depth of the logic portion in terms of CLB depth. The same processing as for the area oriented mapper is performed, but using a speed oriented mapping.

5.4. Area oriented netlist optimizer

For the XC3000, XC4000, XC4000E and XC5200, the netlist optimizer tries to minimize the number of CLBs by calling in an iterative way the area oriented mapper. Therefore, 2 optimization efforts are available.

5.5. Speed or timing constraints oriented netlist optimizer

The netlist optimizer is available only for the XC4000 and XC4000E series. The netlist is first remapped using ROBDD based techniques in order to get a minimal area CLB netlist. Then the critical region, according to the optimization requirements, is detected. This critical region is optimized using controlled collapse, specific minimization and factorization followed by a speed oriented mapping in order to satisfy user’s requirements. These steps are repeated until the optimization requirements are sat-isfied or the best solution is obtained.

For XC4000 and XC4000E series, 2 optimization efforts are available:-1: combinational blocks are minimized and factorized, these blocks are then represented by ROBDDs and factorized expressions that are partially collapsed. A speed oriented mapping on the critical region is then applied.-2: more efforts are spent on all the optimization steps to obtain better results.


5.6.1. Parttype The user specifies the part type to be used when mapping the netlist. The specification of the part type is entered following the Xilinx data sheet for the XC3000, XC4000 and XC5200, except that the temperature range is not indicated, as shown in figure 21.

Figure 21: Part type specification

XC3030-70PC44 Device Type

Toggle RateNumber of Pins

Package Type



If this parameter is not specified the following devices are chosen:- for XC3000 family the device 3090PG175-70,- for the XC4000 family the device 4010PG191-5- for the XC5200 family the device 5210PC84

5.6.2. Automatic Device Selection For XC3000, XC4000, XC4000E and XC5200, a device selection procedure is invoked. This pro-cedure will select the smallest package. If the designer has asked for device selection, the system will forget any choice and propose the smallest device according to the number of CLBs and indicate for different speed grades the critical path.

5.6.3. Add I/O Buffers For the XC3000, XC4000, XC4000E and XC5200, this parameter will insert automatically I/O buffers.

5.6.4. Use Fast Output Buffers For the XC3000, XC4000, XC4000E and XC5200 families, this parameter tells the system to use output buffers with the FAST option. The delay on speed critical outputs can be dramatically reduced by designating them as FAST out-puts. FAST option decreases the transition time of the output driver which also increases the noise in the system. However, the system can only switch all output buffers to the IOB switching characteristic guide-lines for the used device. The default value is YES.

5.6.5. Move Internal Tristates to I/O Buffers For the XC3000, XC4000, XC4000E and XC5200 families, this parameter converts three state buffers connected to outputs to OBUFTs. By default this option is Yes.

5.6.6. Buffer Insertion This option inserts automatically buffers to drive a clock or a high fanout signal. - For the XC3000 Add Generic Clock Buffer (BUFG) allows the insertion of BUFG buffers; legal values are 0 to 8; the default value is 2. Add Global Clock Buffer (GCLK) allows the insertion of GCLK buffers; legal values are 0 and 1; the default value is 0. Add Alternate Clock Buffer (ACLK) allows the insertion of ACLK buffers; legal values are 0 and 1; the default value is 0.



- For the XC4000 and XC4000E Add Generic Global Buffer (BUFG) allows the insertion of BUFG buffers; legal values are 0 to 8; the default value is 4. Add Primary Global Buffer (BUFGP) allows the insertion of BUFGP buffers; legal values are 0 to 4; the default value is 0. Add Secondary Global Buffer (BUFGS) allows the insertion of BUFGS buffers; legal values are 0 to 4; the default value is 0. - For the XC5200 Add Generic Global Buffer (BUFG) allows the insertion of BUFG buffers; legal values are 0 to 8; the default value is 4.

5.6.7. Create Startup Instance For XC4000, XC4000E and XC5200, this parameter checks if all flip-flops Reset and Set pins are driven by one signal and adds a STARTUP instance and corresponding attributes to flip-flops. This can improve routing and performance.

5.6.8. Use Internal IOB FF For XC3000, XC4000 and XC4000E, some flip-flops not sourced by an external signal may be assigned in internal CLB locations for optimization or routing congestion minimization. The maxi-mum number of internal I/O buffers is selected according to the part type. This option may increase delays and create some problems as dummy pads are design internal nodes.

5.6.9. Control Routing Complexity For the XC3000, a special synthesis method is used, minimizing the routing complexity. This option overwrites the optimization efforts.

5.6.10. Use Macro This parameter allows the user to indicate how the macro blocks will be handled. Two values are available: if Macro+ is specified then the macro blocks will be automatically generated by PLS+, if XBLOX then the XBLOX macro generators will be used. This option is available only if the input format in the source parameters is VHDL. XBLOX support is available for XC4000 and XC4000E. More details are given in the "Macro Block Handling: Macro+" part.

5.7. Command menu Select Xilinx_3000, Xilinx_4000, Xilinx_4000E or Xilinx_5200 in the Target Technology menu within the Target Parameters in the Synthesis Parameters window. Select the Target Option button to define or modify the specific Xilinx parameters. The following four displays correspond respectively to the Xilinx 3000, 4000/4000E and 5200 technologies:



Figure 22: Target option selection for Xilinx XC3000, XC4000/4000E and XC5200



5.8. On-line mode

PLS+ can also perform synthesis on Xilinx using the On-line mode. In the main menu of the PLS+, select the On-line option. The On-line command window will appear.For synthesis from high level description, refer to the language parts of this manual for details about general options.For synthesis or optimization of Xilinx FPGA series, the following specific parameters must be defined:

-t Xilinx-tech <3000/4000/4000E/5200> -parttype <package name>-xildevsel <Automatic Device Selection>-iobuf <Add I/O Buffers >-fastobuf <Add Fast Output Buffers >-tbufinio <Move Internal Three state to I/O buffers> -aclk <0/1>-gclk <0/1>-bufgs <0..4>-bufgp <0..4>-bufg <0..8>-startup <Create Startup instance>-ffinio <Use Internal IOB FF> -route <Control Routing Complexity>-b_lib <Macro File Name>

• Parttype (-parttype)

Default: Default value is 3090PG175-70 for the 3000 series, 4010PG191-5 for the 4000series and 5210PC84 for the 5200 series.

• Automatic Device Selection (-xildevsel)

Value: Yes or No

Default: Default value is Yes.

Remark: Available for XC3000, XC4000, XC4000E and XC5200 series.

• Add I/O buffers (-iobuf)

Value: Yes or No.



• Add Fast Output Buffers (-fastobuf)

Value: Yes or No.





• Move Internal Tristates to I/O Buffers(-tbufinio)

Value: Yes or No.

Default: Default value is No.


• Number of dedicated buffers (-aclk, -gclk, -bufgs, -bufgp, -bufg)


Remark: -bufg, -gclk and -aclk for XC3000,-bufg, -bufgp and -bufgs for XC4000 and XC4000E,-bufg for XC5200.

• Create STARTUP instance (-startup)

Value: Yes or No.


Remark: Available for XC4000, XC4000E and XC5200 series.

• Use Internal IOB FF (-ffinIO)


Default: Default value is 0.

Remark: Available for XC3000, XC4000 and XC4000E series.

• Control Routing Complexity (-route)

Value: Yes or No


Remark: Available for XC3000 series.

• Use Macro (-b_lib)

Value: xb_m.lib (for XC4000 and XC4000E)

Default: Macro+. By default, the PLS+ macro block generators will be used.


Documents

Appendix Getting Started with FPGA Mapper