Arch Book Solution Ch4 Sep

8/9/2019 Arch Book Solution Ch4 Sep

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Chapter 4

Sequential Logic Circuits

1


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2 Chapter 4

41 The defining characteristic of a combinational circuit is that its output depends only on the current

inputs applied to the circuit. The output of a sequential circuit, on the other hand, depends bothon the current input values as well as the past inputs. This dependence on past inputs gives the

property of memory for sequential circuits.


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Chapter 4 3

42 The sequence of past inputs is encoded into a set of state variables. The feedback circuit stores

this state information and feeds it to the input.


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Chapter 4 5

44 When S and R are 1, both outputs are forced to take 0. To see why this combination is undesirable,

consider what happens when S and R inputs are changed from S = R = 1 to S = R = 0. It is onlyin theory that we can assume that both inputs change simultaneously. In practice, there is always

some finite time difference between the two signal changes. If the S input goes low earlier than the

R signal, the sequence of input changes is SR = 11

01

00. Because of the intermediate state

SR = 01, the output will be Q = 0 and

= 1. If, on the other hand, the R signal goes low before

the S signal does, the sequence of input changes is SR = 11

10

00. Because the transition

goes through the SR = 10 intermediate state, the output will be Q = 1 and = 0. Thus, when the

input changes from 11 to 00, the output is indeterminate. This is the reason for avoiding this state.


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6 Chapter 4

45 The truth table is shown below:

Q n+1

Q n

S R

0 0

0 1

1 0

1 1

0

1

1

It can se seen from this truth table that is not exactly the same as that given for the NOR gate

version. However, it is closely related in the sense it is the dual of the other truth table.


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Chapter 4 7

46 The D-latch avoids the SR = 11 input combination by using a single inverter to provide only

complementary inputs at S and R inputs of the clocked SR latch as shown below:

Q

S

R

Q

CP

Clock


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8 Chapter 4

47 Flip-flops are edge-triggered devices whereas latches are level sensitive.


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Chapter 4 9

48 The circuit is shown below:

Reset

CCCC

S S S S

Q Q Q Q

Q 0 Q 1 Q 2 Q 3

FF0 FF1

Clock

J

K

Q

CP

J

K

Q

CP

FF2

J

K

Q

CP

FF3

J

K

Q

CP

High

High


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10 Chapter 4


Q Q

Q 0 Q 1

Q

Q 2

High J

K

Q

CP

QQ

High

High

Clock

J

K

Q

CP

J

K

Q

CP

High J

K

Q

CP

High J

K

Q

CP

Q 3 Q 4


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Chapter 4 11


Q Q QQ

High

Clock

J

K

Q

CK

D

J

K

Q

CK

C

J

K

Q

CK

A

J

K

Q

CK

B


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12 Chapter 4

411 We need four JK flip-flops to implement this four-bit counter. The design table is shown below:

Present state Next state JK flip-flop inputs

A B C D A B C D

0 0 0 0 0 0 1 0 0 d 0 d 1 d 0 d

0 0 0 1

d d d d d d d d

0 0 1 0 0 1 0 0 0 d 1 d d 1 0 d

0 0 1 1

d d d d d d d d

0 1 0 0 0 1 1 0 0 d d 0 1 d 0 d0 1 0 1

d d d d d d d d

0 1 1 0 1 0 0 0 1 d d 1 d 1 0 d

0 1 1 1

d d d d d d d d

1 0 0 0 1 0 1 0 d 0 0 d 1 d 0 d

1 0 0 1

d d d d d d d d

1 0 1 0 1 1 0 0 d 0 1 d d 1 0 d

1 0 1 1 d d d d d d d d

1 1 0 0 1 1 1 0 d 0 d 0 1 d 0 d1 1 0 1

d d d d d d d d

1 1 1 0 0 0 0 0 d 1 d 1 d 1 0 d

1 1 1 1

d d d d d d d d

Using the Karnaugh map method, we can get the simplified logical expressions for the J and K

inputs as follows:

J

B C K

B C

J

C, K

C

J

K

J

K

d

Notice that the D flip-flop is not necessary as its output is always 0. The circuit is shown below:


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Chapter 4 13

QQ Q

J

K

Q

CK

A

J

K

Q

CK

C

J

K

Q

CK

B

High

Clock

D


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14 Chapter 4

412 We need three JK flip-flops to implement this four-bit counter. The design table is shown below:

Present state Next state JK flip-flop inputs

A B C A B C

0 0 0 0 0 1 0 d 0 d 1 d

0 0 1 0 1 1 0 d 1 d d 0

0 1 0 1 1 0 1 d d 0 0 d

0 1 1 0 1 0 0 d d 0 d 1

1 0 0 0 0 0 d 1 0 d 0 d

1 0 1 1 0 0 d 0 0 d d 1

1 1 0 1 1 1 d 0 d 0 1 d

1 1 1 1 0 1 d 0 d 1 d 0


inputs as follows:

J

B

K

J

C

K

A C

J

A B

K

B

A

The circuit is shown below:

QQ Q

J

K

Q

CK

A

J

K

Q

CK

C

J

K

Q

CK

B

Clock


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Chapter 4 15

413 The state table is shown below:

Next state Output

Present state X = 0 X = 1 X = 0 X = 1

S0 S0 S1 0 1

S1 S1 S0 1 0

Simple state assignment: S0 = 0 and S1 = 1.

Present

state

Present

state

Next

state

Present

state JK flip-flop inputs

A X A Y

0 0 0 0 0 d

0 1 1 1 1 d

1 0 1 1 d 0

1 1 0 0 d 1


inputs and the output Y as follows:

J

X

K

X

Y

A

X

The circuit is shown below:

Q

J

K

Q

CKClock

X

Y


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16 Chapter 4

414 The Karnaugh map for the state assignment is shown below:

S0 S3

S2

A

BC00 01 11 10

0

1 S1

S5

S4S6

Final state assignment is shown below:

State A B C

S0 = 0 0 0

S1 = 1 0 0

S2 = 1 1 0

S3 = 0 0 1

S4 = 1 1 1

S5 = 0 1 0

S6 = 1 0 1

The design table is shown below:


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18 Chapter 4

415 We can use the same circuit; all we have to do is invert the input.


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Chapter 4 19

416 The state diagram is shown below:

You can see from this state diagram that the design remains the same as that for the pattern recog-

nition example on page 134 (see Example 2). However, we need to modify the output Y. In the Y

column in Table 4.8, the last two 1s should be zero. This gives us the following expression for the

only 1 in that column:

Y

B C

.

The implementation is as shown in Figure 4.28 (substitute the following circuit for the Y logic

circuit given in Figure 4.8 ):

C

X

Y

A

B


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20 Chapter 4


Next state Output

Present state X = 0 X = 1 X = 0 X = 1

S0 S1 S0 0 0

S1 S1 S2 0 0

S2 S0 S0 1 0

Heuristic 1 groupings: (S0, S1) (S0, S2)

Heuristic 2 groupings: (S0, S1) (S0, S2)

These groupings suggest the following state assignment:

S0 S1

A

B0 1

0

1 S2


State A B

S0 = 0 0

S1 = 0 1

S2 = 1 0



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Chapter 4 21

Present

state

Present

state

Next

state

Present


A B X A B Y

0 0 0 0 1 0 0 d 1 d

0 0 1 0 0 0 0 d 0 d

0 1 0 0 1 0 0 d d 0

0 1 1 1 0 0 1 d d 1

1 0 0 0 0 1 d 1 0 d

1 0 1 0 0 0 d 1 0 d


inputs as follows:

J

B X

K

J

K

X

The Y output logical expression is:

Y

A

The implementation is shown below:

X

Clock

B

High

A

Q

J

K

Q

CK

Q

J

K

Q

CK

Y


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22 Chapter 4


00/0

01/0 01/0 01/0 01/0 01/1

S1 S2 S3 S4 S5S0

10/0 10/0 10/0 10/1

10/1

00/0 00/0 00/0 00/0 00/0

01/0

10/0

The state table is shown below:

Next state Output Z

Present state XY = 00 XY = 01 XY = 10 XY = 00 XY = 01 XY = 10

S0 S0 S1 S2 0 0 0

S1 S1 S2 S3 0 0 0

S2 S2 S3 S4 0 0 0

S3 S3 S4 S5 0 0 0

S4 S4 S5 S5 0 1 1

S5 S5 S1 S2 0 0 0

Heuristic 1 groupings: (S0, S5)

(S3, S4)

Heuristic 2 groupings: (S1, S2) (S2, S3) (S4, S5) (S3, S4)

Heuristic 3 groupings: None



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Chapter 4 23

S0 S3

A

BC00 01 11 10

0

1 S5 S1S4

S2


State A B C

S0 = 0 0 0S1 = 1 1 1

S2 = 0 1 1

S3 = 0 0 1

S4 = 1 0 1

S5 = 1 0 0



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24 Chapter 4

Present

state

Present

state

Next

state

Present


A B C XY A B C Z

0 0 0 00 0 0 0 0 0 d 0 d 0 d

0 0 0 01 1 1 1 0 1 d 1 d 1 d

0 0 0 10 0 1 1 0 0 d 1 d 1 d

0 0 1 00 0 0 1 0 0 d 0 d d 0

0 0 1 01 1 0 1 0 1 d 0 d d 0

0 0 1 10 1 0 0 0 1 d 0 d d 1

0 1 1 00 0 1 1 0 0 d d 0 d 0

0 1 1 01 0 0 1 0 0 d d 1 d 0

0 1 1 10 1 0 1 0 1 d d 1 d 0

1 0 0 00 1 0 0 0 d 0 0 d 0 d

1 0 0 01 1 1 1 0 d 0 1 d 1 d

1 0 0 10 0 1 1 0 d 1 1 d 1 d

1 0 1 00 1 0 1 0 d 0 0 d d 0

1 0 1 01 1 0 0 1 d 0 0 d d 1

1 0 1 10 1 0 0 1 d 0 0 d d 1

1 1 1 00 1 1 1 0 d 0 d 0 d 0

1 1 1 01 0 1 1 0 d 1 d 0 d 0

1 1 1 10 0 0 1 0 d 1 d 1 d 0


inputs as follows:

J

Y

C X

K

B X

B Y

X

J

X Y K

X Y

J

X

Y

K

C X

A

C

Y

The Z output logical expression is:

Z

A

C

Y

X

It is straightforward to complete the solution using these expressions (similar to what is shown in


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Chapter 4 25

Figures 4.27 and 4.28).


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26 Chapter 4


00/00

01/00 01/00 01/00 01/00 01/01

S1 S2 S3 S4 S5S0

10/00 10/00 10/00 10/10

00/00 00/00 00/00 00/00 00/00

10/00

00/00

S6

01/0001/00

10/00

10/11

Note that the output is represented by two bits: CZ. The C bit indicates change due and the Z bit

indicates activation of the selection circuit (as in the last exercise).

The state table is shown below:

Next state Output CZ

Present state XY = 00 XY = 01 XY = 10 XY = 00 XY = 01 XY = 10

S0 S0 S1 S2 00 00 00

S1 S1 S2 S3 00 00 00

S2 S2 S3 S4 00 00 00

S3 S3 S4 S5 00 00 00

S4 S4 S5 S5 00 01 11

S5 S5 S1 S2 00 00 00

S6 S6 S1 S2 00 00 00

Heuristic 1 groupings: (S0, S5, S6) (S3, S4)

Heuristic 2 groupings: (S1, S2) (S2, S3) (S4, S5) (S3, S4)

Heuristic 3 groupings: None



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Chapter 4 27

S0 S3

A

BC00 01 11 10

0

1 S5 S1S4

S2

S6


State A B C

S0 = 0 0 0

S1 = 1 1 1

S2 = 0 1 1

S3 = 0 0 1

S4 = 1 0 1

S5 = 1 0 0

S6 = 1 1 0



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28 Chapter 4

Present

state

Present

state

Next

state

Present


A B C XY A B C CZ

0 0 0 00 0 0 0 00 0 d 0 d 0 d

0 0 0 01 1 1 1 00 1 d 1 d 1 d

0 0 0 10 0 1 1 00 0 d 1 d 1 d

0 0 1 00 0 0 1 00 0 d 0 d d 0

0 0 1 01 1 0 1 00 1 d 0 d d 0

0 0 1 10 1 0 0 00 1 d 0 d d 1

0 1 1 00 0 1 1 00 0 d d 0 d 0

0 1 1 01 0 0 1 00 0 d d 1 d 0

0 1 1 10 1 0 1 00 1 d d 1 d 0

1 0 0 00 1 0 0 00 d 0 0 d 0 d

1 0 0 01 1 1 1 00 d 0 1 d 1 d

1 0 0 10 0 1 1 00 d 1 1 d 1 d

1 0 1 00 1 0 1 00 d 0 0 d d 0

1 0 1 01 1 0 0 01 d 0 0 d d 1

1 0 1 10 1 0 0 11 d 0 0 d d 1

1 1 0 00 1 1 0 00 d 0 d 0 0 d

1 1 0 01 1 1 1 00 d 0 d 0 1 d

1 1 0 10 0 1 1 00 d 1 d 0 1 d

1 1 1 00 1 1 1 00 d 0 d 0 d 0

1 1 1 01 0 1 1 00 d 1 d 0 d 0

1 1 1 10 0 0 1 00 d 1 d 1 d 0


inputs as follows:

J

Y

C X

K

B X

B C Y

X

J

X

Y

K

X

Y


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Arch Book Solution Ch4 Sep