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SERDES Transmitter/Receiver (ALTLVDS)Megafunction User Guide

Software Version: 8.1Document Version: 4.0Document Date: November 2008

UG-MF9504-4.0

Copyright 2008 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all otherwords and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and othercountries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending ap-plications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty,but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use ofany information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version ofdevice specifications before relying on any published information and before placing orders for products or services.

UG-MF9504-4.0

November 2008 Altera Corporation

Contents

Simulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-37SERDES Transmitter/Receiver (ALTLVDS) Megafunction User Guide Chapter 1. About This MegafunctionIntroduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1Device Family Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2

Soft CDR Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3Clock Forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3Soft CDR Recovered Clock Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3Common Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4

Resource Utilization and Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4

Chapter 2. Getting StartedIntroduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1Software and System Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1MegaWizard Plug-In Manager Customization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1MegaWizard Plug-In Manager Page Options and Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

MegaWizard Plug-In Manager Pages for the LVDS Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2LVDS Transmitter Using a Dedicated SERDES Block or SERDES in LEs . . . . . . . . . . . . . . . . . . . . 2-2LVDS Transmitter Using an External PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

MegaWizard Plug-In Manager Pages for the LVDS Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9LVDS Receiver Using a Dedicated SERDES Block or SERDES in LEs . . . . . . . . . . . . . . . . . . . . . . . 2-9LVDS Receiver Using an External PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16

Common Pages for ALTLVDS Receiver and Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18Instantiating Megafunctions in HDL Code or Schematic Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18

Generating a Netlist for EDA Tool Use . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19Using the Port and Parameter Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19

Identifying a Megafunction After Compilation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20Design Example 1: LVDS-to-LVDS Bridge Using Different Clock Frequencies . . . . . . . . . . . . . . . . . . 2-22

Design Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23Generate an ALTLVDS Receiver and ALTLVDS Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23Functional ResultsSimulate the ALTLVDS Receiver/Transmitter Design in the ModelSim-Altera Simulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28

Design Example 2: Cyclone II ALTLVDS Using External PLL Option . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29Design Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29Generate an ALTLVDS Receiver and ALTLVDS Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-30

Integrating the ALTLVDS Receiver and Transmitter in the Design . . . . . . . . . . . . . . . . . . . . . . . 2-32Parameters Used by ALTPLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-33

Functional ResultsSimulate the ALTLVDS Receiver/Transmitter Design in the Quartus II Software 2-35Timing ResultsSimulate the ALTLVDS Receiver/Transmitter Design in the Quartus II Software . . 2-36Functional ResultsSimulate the ALTLVDS Receiver/Transmitter Design in the ModelSim-Altera

iv ContentsDesign Example 3: Stratix III Soft Clock Data Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-38Design Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-39Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-39Generate an ALTLVDS Receiver and ALTLVDS Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-39Functional ResultsSimulate the ALTLVDS Receiver/Transmitter Design in the ModelSim-Altera Simulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-42

Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-43

Chapter 3. SpecificationsPorts and Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

Additional InformationRevision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . About-1Referenced Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . About-2How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . About-2Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . About-2SERDES Transmitter/Receiver (ALTLVDS) Megafunction User Guide November 2008 Altera Corporation


1. About This Megafunction

Parameterizable serializer/deserializer (SERDES) factors.

Registered inpSERDES Transmitter/Receiver (ALTLVDS) Megafunction User Guide

uts and outputs.IntroductionAs design complexities increase, use of vendor-specific Intellectual Property (IP) blocks have become a common design methodology. Altera provides parameterizable megafunctions that are optimized for Altera device architectures. Using megafunctions instead of coding your own logic saves valuable design time. Additionally, the Altera-provided functions may offer more efficient logic synthesis and device implementation. You can scale the megafunctions size by setting parameters.

Device Family SupportThe SERDES transmitter/receiver (ALTLVDS) megafunction support the following target Altera device families:

Arria GX

Stratix IV

Stratix III

Stratix II

Stratix II GX

Stratix GX

Stratix

Cyclone III

Cyclone II

Cyclone

HardCopy II

HardCopy Stratix

APEX II

APEX 20KC

APEX 20KE

FeaturesThe ALTLVDS megafunction implement either an LVDS deserializer receiver or an LVDS serializer transmitter and offer many additional features:

Parameterizable data channel widths.

12 Chapter 1: About This MegafunctionGeneral Description Dynamic Phase Alignment (DPA) mode support in Stratix IV, Stratix III, Stratix II GX, Stratix II and Stratix GX receivers.

Ability to share fast phase-locked loops (PLLs) between transmitter and receivers.

PLL control signals.

Flexibility to implement in dedicated circuitry or in logic cells. This varies according to the device.

Support for separate PLL in Stratix IV, Stratix III, Stratix II, Stratix II GX, Cyclone III, Cyclone II, Cyclone, and HardCopy II devices.

Soft Clock-Data Recovery (CDR) mode support for Stratix IV and Stratix III devices.

General DescriptionThe ALTLVDS megafunction is provided in the Quartus II software, through the MegaWizard Plug-In Manager. The ALTLVDS megafunction instantiates LVDS transmitters (ALTLVDS_TX) and LVDS receivers (ALTLVDS_RX). The ALTLVDS_TX megafunction implements a serialization transmitter, and the ALTLVDS_RX megafunction implements a deserialization receiver. These megafunctions can be used to take advantage of the dedicated SERDES circuitry for high-speed differential data transfer applications in Stratix IV, Stratix III, Stratix II, Stratix II GX, Stratix GX, Stratix, HardCopy II, and HardCopy Stratix devices. The ALTLVDS megafunction can also be used to implement SERDES circuitry using logic elements (LEs) and PLLs in Cyclone III, Cyclone II and Cyclone devices. By using the LVDS megafunctions, you can customize and control the LVDS data received or transmitted to many source synchronous channels. The ALTLVDS megafunction has features that are unique to each supported device family.

To achieve high data transfer rates, the Stratix IV, Stratix III, Stratix II, Stratix II GX, Stratix GX, Stratix, HardCopy II, and HardCopy Stratix devices support True-LVDS differential I/O interfaces that have dedicated SERDES circuitry for each differential I/O pair.

f For transmitting and receiving data rates for respective devices, refer to the specific device data sheets.

On the receiver side, the high-frequency clock generated by the PLL shifts the serial data through a shift register (also called the deserializer). The parallel data is clocked out to the logic array that is synchronized with the low frequency clock.

On the transmitter side, the parallel data from the logic array is first clocked into a parallel-in, serial-out shift register that is synchronized with the low-frequency clock, and then transmitted out by the output buffers.

The dedicated phase alignment (DPA) circuitry supports multiple SERDES factors. Each channel has its own DPA circuit that provides independent data alignment for each channel; therefore, DPA can reduce channel-to-channel skew as well as clock-to-channel skew.

1 Cyclone series (Cyclone III, Cyclone II, and Cyclone) devices do not support the dedicated DPA circuitry.SERDES Transmitter/Receiver (ALTLVDS) Megafunction User Guide November 2008 Altera Corporation

Chapter 1: About This Megafunction 13General DescriptionCyclone series (Cyclone III, Cyclone II, and Cyclone) devices also allow the SERDES implementation at certain data rates for a specific device. For the LVDS transmitter and receiver, the ALTLVDS megafunction implements serialization and deserialization using LEs and PLLs.

f For supported data rates, refer to the specific device data sheets.

Soft CDR ModeThe Stratix IV and Stratix III series of devices support a new soft CDR mode. This mode supports the Serial Gigabit Media Independent Interface (SGMII) protocol. Clock-data recovery removes the clock from the clock-embedded data, a capability required for SGMII support.

The Stratix IV and Stratix III LVDS block requires the new mode to support clock forwarding to the core, described in the Clock Forwarding section. In Stratix IV and Stratix III devices, each LVDS channel can be in soft CDR mode and can drive the core. However, Stratix IV and Stratix III devices do not contain dedicated hardware for the CDR support. Instead, the CDR circuitry is implemented as part of the ALTLVDS megafunction instantiation.

Clock ForwardingThe Stratix IV and Stratix III LVDS block supports clock forwarding to the core. In soft CDR mode, the DPA clock is forwarded to the core after being divided by the deserialization factor. The divclkout output signal from the LVDS block holds the forwarded clock signal. The signal is routed to the new periphery clock (PCLK) network.

The DPA block determines the optimal DPA clock, which is forwarded to the core. In normal DPA operation, the DPA block selects an optimal phase to sample the data. The captured data is passed to the bitslip block, then to the deserializer. The deserializer divides the DPA clock and the data by the deserialization factor. The newly divided clock signal is placed on the PCLK network, which carries the clock signal to the core. In Stratix IV and Stratix III devices, each LVDS channel can be in soft CDR mode and can drive the core using the PCLK network.

f The PCLK network originates in the DPA block of a Stratix IV or a Stratix III device. For more information about PCLKs, refer to the Clock Networks and PLLs in Stratix IV Devices chapter in volume 1 of the Stratix IV Device Handbook and the Clock Networks and PLLs in Stratix III Devices chapter in volume 1 of the Stratix III Device Handbook.

Soft CDR Recovered Clock SimulationThe Quartus II software supports simulation of the forwarded clock, also called the recovered clock, based on the user-specified ppm value. The ppm value specifies the number of clock cycles drift between the transmitter and receiver after a million clock cycles. The drift is positive if the transmitter is faster than the receiver, and negative if the receiver is faster than the transmitter. November 2008 Altera Corporation SERDES Transmitter/Receiver (ALTLVDS) Megafunction User Guide

14 Chapter 1: About This MegafunctionResource Utilization and PerformanceYou can specify the ppm value using two new simulation-only parameters for the ALTLVDS megafunction. The value of NET_PPM_VARIATION is the absolute value of the drift, and the IS_NEGATIVE_PPM_DRIFT parameter specifies whether the drift is positive or negative. The Quartus II simulator simulates the ppm variation by shifting the recovered data and clock based on the user-specified ppm value.

Common ApplicationsThe SERDES interface is used to transmit and receive high-speed differential data. This enables moving data from board-to-board or box-to-box with great efficiency. This high performance consumes minimum power, is relatively immune to noise, and is cost effective. Typical applications of LVDS technology are common in PC computing (such as flat panel displays and monitor links), telecommunication and data-communication systems (such as routers, hubs, and switches) and other common consumer and commercial applications (such as set-top boxes and in-flight entertainment).

The Stratix IV and Stratix III LVDS block supports a new soft CDR mode. This mode supports the widely-used SGMII protocol. A clock-data recovery removes the clock from the clock-embedded data, a capability required for the SGMII support. This new mode is called soft CDR mode because the CDR circuitry is implemented in the LEs.

f For additional information about common applications supported, and for full details on the I/O standards and high-speed protocols supported, refer to the applicable data sheet or device handbook for each device family.

Resource Utilization and PerformanceEvery instantiation of ALTLVDS megafunction uses one fast PLL. The Quartus II software properly configures the PLL according to the settings you apply in the ALTLVDS MegaWizard Plug-In Manager. Stratix IV, Stratix III, Stratix II, Stratix II GX, Cyclone III, Cyclone II, Cyclone, HardCopy II, and HardCopy Stratix devices provide the option to use an external PLL, which requires you to enter the appropriate PLL parameters.

f For more information about the PLL parameters, refer to the ALTPLL Megafunction User Guide.

All Stratix families support the Use Shared PLL(s) for Receiver and Transmitter option to place both the LVDS transmitter and the LVDS receiver in the same device I/O bank. The Quartus II software lets the transmitter and the receiver share the same fast PLL when both use the same input clock frequency. Although you must separate the transmitter and receiver modules in your design, the Quartus II software merges the fast PLLs, when appropriate, and gives you the following message:

Info: Receiver fast PLL and transmitter fast PLL are merged together

The Quartus II software displays the following message when it cannot merge the fast PLLs for the LVDS transmitter and receiver pair in the design:

Warning: Can't merge transmitter-only fast PLL and receiver-only fast PLL SERDES Transmitter/Receiver (ALTLVDS) Megafunction User Guide November 2008 Altera Corporation

Chapter 1: About This Megafunction 15Resource Utilization and PerformanceFor Stratix device families, the side I/O banks contain dedicated SERDES circuitry, which includes the fast PLLs, serial shift registers, and parallel registers. The transmit and receive functions use varying numbers of LEs depending on the number of channels, serialization and deserialization factors. For best performance, these LEs must be placed in columns as close to the SERDES circuitry and LVDS pins as possible. This is done by the Quartus II software automatically during place-and-route.

Cyclone III, Cyclone II, and Cyclone devices use DDIO registers as part of the SERDES interface. Since data is clocked on both the rising and falling edge, the clock frequency must be half the data rate; therefore, the PLL runs at half the frequency of the data rate. The core clock frequency for the transmitter is data rate divided by the serialization factor (J). For the odd serialization factors, depending on the output clock-divide factor (B) and device family, an optional core clock frequency of data rate divided by two times the serialization factor (J) is also available.

Use Table 11 and Table 12 to determine the clock and data rate relationships.

The Quartus II software reports the number of LEs used per ALTLVDS function in the Fitter Resource Utilization by Entity section within the Resource section of the Compilation Report file.

Table 11. Cyclone III, Cyclone II, and Cyclone ALTLVDS Receiver Clock Relationships

Clock Type J = Even J = Odd

Fast Clock Data Rate / 2 Data Rate / 2

Slow Clock (outclock) Data Rate / J Data Rate / J

Table 12. Cyclone III, Cyclone II, and Cyclone ALTLVDS Transmitter Clock Relationships

Clock Type J = Even J = Odd

Fast Clock Data Rate / 2 Data Rate / 2

Slow Clock (outclock) Data Rate / 2 * B Data Rate / 2 * B

Core Clock Data Rate / J Data Rate / J November 2008 Altera Corporation SERDES Transmitter/Receiver (ALTLVDS) Megafunction User Guide

16 Chapter 1: About This MegafunctionResource Utilization and PerformanceSERDES Transmitter/Receiver (ALTLVDS) Megafunction User Guide November 2008 Altera Corporation


2. Getting StartedSERDES Transmitter/Receiver (ALTLVDS) Megafunction User GuideIntroductionThe most efficient way to customize your ALTLVDS megafunction is the MegaWizard Plug-In Manager . Stratix IV, Stratix III, Stratix II, Stratix II GX, Stratix, Stratix GX, HardCopy II, and HardCopy Stratix devices each have different features available when using the dedicated serializer/deserializer (SERDES) circuitry. Cyclone III, Cyclone II, and Cyclone devices do not have dedicated SERDES circuitry; therefore, the functions are implemented in registers using logic elements (LEs). The wizard displays only the features that are appropriate to the selected device family. Within each selected device, certain features are available, depending on the modes that you specify.

Software and System RequirementsThe instructions in this section require the Quartus II software version 8.1. For operating system support information, refer to the Operating System Support page in Altera website (www.altera.com).

MegaWizard Plug-In Manager CustomizationUse the MegaWizard Plug-In Manager to create or modify design files that contain custom ALTLVDS variations that can be instantiated in a design file. The MegaWizard Plug-In Manager provides a wizard that allows you to specify options for the custom ALTLVDS megafunction features in your design.

Start the MegaWizard Plug-In Manager in one of the following ways:

On the Tools menu, click MegaWizard Plug-In Manager.

When working in the Block Editor, from the Edit menu, click Insert Symbol as Block, or right-click in the Block Editor, point to Insert, and click Symbol as Block. In the Symbol window, click MegaWizard Plug-In Manager.

Start the stand-alone version of the MegaWizard Plug-In Manager by typing the following command at the command prompt:qmegawiz r

22 Chapter 2: Getting StartedMegaWizard Plug-In Manager Page Options and DescriptionsMegaWizard Plug-In Manager Page Options and DescriptionsThis section provides descriptions of the options available on page 1 and page 2a of the ALTLVDS MegaWizard Plug-In Manager.

The first two pages of the megafunction are the same for all supported devices. On page 1 of the MegaWizard Plug-In Manager, you can select Create a new custom megafunction variation, Edit an existing custom megafunction variation, or Copy an existing custom megafunction variation.

On page 2a of the MegaWizard Plug-In Manager, you can specify the megafunction, the family of device to use, the type of output file to create, and the name of the ouput file. The ALTLVDS megafunction appears in the I/O category. you can choose AHDL (.tdf), HVDL (.vhd), or Verilog HDL (.v) as the output file type.

The selections you make on page 3 dictate the format of the remaining pages. The device family that you select determines the ports and parameters that are available on page 3 and the following pages. For every device family, the pages for the LVDS transmitter are different than the pages for the LVDS receiver. For the receiver or the transmitter, if the device allows you to choose whether to implement the serializer/deserializer (SERDES) circuitry in logic cells or in a dedicated SERDES block, your choice affects the other parametrization choices available to you. Similarly, you can choose whether to use an external PLL. For the receiver, if you choose to enable the DPA mode, your choice affects the other parametrization choices available to you.

On page 3, you specify whether this megafunction is an LVDS transmitter or receiver, the number of channels, and the deserialization factor. The number of channels you select changes the width of the rx_in port, and the deserialization factor changes the width of the rx_out port. If the required number of channels is not available in the list, type the desired number in the What is the number of channels? box. The list for the deserialization factor is device-dependent.

Your choice of device and transmitter or receiver determines whether the remaining options on this page are available to you or are disabled.

The left pane of the MegaWizard Plug-In Manager displays a schematic representation of the custom megafunction variation that you are creating. The schematic updates automatically as the ports and parameters change.

1 For online help, click the Documentation button to view the Quartus II Help file for the LVDS transmit or receive megafunction.

MegaWizard Plug-In Manager Pages for the LVDS TransmitterOn page 3, after you select the LVDS transmitter, depending on the device you selected, you can choose to implement the SERDES circuitry in logic cells or in a dedicated SERDES block. Similarly, depending on the device, you can choose to use an external PLL.

LVDS Transmitter Using a Dedicated SERDES Block or SERDES in LEsThis section discusses the options available for configuring the LVDS transmitter megafunction if an internal PLL is used.SERDES Transmitter/Receiver (ALTLVDS) Megafunction User Guide November 2008 Altera Corporation

Chapter 2: Getting Started 23MegaWizard Plug-In Manager Page Options and DescriptionsOn page 3, several options can be customized for the transmitter settings. The options are described in Table 21.

Table 21. ALTLVDS Transmitter Settings Page Options and Descriptions (Page 3)

Option Description Comments

Implement Serializer/Deserializer circuitry in logic cells

If not enabled, the megafunction takes advantage of dedicated SERDES circuitry in the device. If enabled, SERDES circuitry is implemented in logic cells. This feature is supported by Arria GX, Stratix IV, Stratix III, Stratix II, Stratix II GX, Stratix GX, Stratix, HardCopy II, and HardCopy Stratix devices. In the Cyclone series of devices, SERDES circuitry is always implemented in logic cells.

If enabled, the transmitter starts its operation on the first fast clock edge after the PLL is locked. This option is intended for slow speeds and byte alignment may be different from the hard SERDES implementation.

What is the number of channels? Number of output channels available for the LVDS transmitter. The allowed values depend on the pins available in the device. For the allowed values for your device, refer to the relevant device handbook.

For example, if the number of channels is 44, a tx_out[43..0] port is created. Altera recommends you to use the

ALTIOBUF megafunction to connect the channels to actual FPGA pins via the I/O buffer. By using ALTIOBUF megafunction, you can control whether the buffer should be differential.

For further details, refer to the I/O Buffer (ALTIOBUF) Megafunction User Guide.

What is the deserialization factor? This value determines the number of parallel bits from the core that the transmitter serializes and sends out. For the valid deserialization factors for your device, refer to the relevant device handbook.

For example, if the deserialization factor is 10 and the number of output channels is 1, the transmitter serializes every 10 parallel bits into the single output channel. If the deserialization factor is 10 and the number of channels is 44, a tx_in[439..0]port is created.

The wizard has disabled the 50/50 duty cycle for 7, 5 and 9 mode when divide_by_factor shown in the wizard GUI is same as the deserialization factor.

Megafunction issues a warning and implements the 4:3 duty cycle.

Use External PLL This determines whether to use an external PLL to clock the SERDES transmitter. If this option is not enabled, the megafunction automatically implements an internal PLL to clock the LVDS transmitter block. If this option is enabled, a separate PLL must be used to provide the clocking source. It is your responsibility to make the necessary connections.

If not enabled, the next page displays the PLL settings. The PLL settings page is skipped if this option is enabled.

Take note when you have a deserialization factor of two, the SERDES is bypassed and its functionality is implemented in DDR registers. You need at least a deserialization factor of four to use the external PLL option. November 2008 Altera Corporation SERDES Transmitter/Receiver (ALTLVDS) Megafunction User Guide

24 Chapter 2: Getting StartedMegaWizard Plug-In Manager Page Options and DescriptionsPage 4 of the MegaWizard Plug-In Manager is the Frequency/PLL settings page. This page appears only if an internal PLL is used.

Table 22 describes the options you have on page 4 to customize the frequency and PLL settings.

Table 22. ALTLVDS Transmitter Frequency/PLL Settings Page Options and Descriptions (Page 4) (Part 1 of 2)


What is the output data rate? The value specifies the data rate for the output channel of the transmitter, in Mbps. For data rate ranges, refer to the specific DC & Switching Characteristics chapter in the appropriate device handbook.

This value determines the allowed input clock rate values.

Specify the input clock rate by The value specifies the tx_inclock frequency to the internal PLL. The allowed values depend on the output data rate selected.

What is the phase alignment of tx_in with respect to the rising edge of 'tx_inclock'? (in degrees)

This value determines the phase alignment of the data transmitted by the transmitter core with respect to tx_inclock. Available values are 0 (edge-aligned), 45, 90, 135, 180 (center-aligned), 225, 270, 315.

Use tx_pll_enable input port This port gives you control over the enable port of the fast PLL that is used with this function.

If the transmitter shares the PLL with the receiver, and the tx_pll_enable port is used, this port must be used in both megafunction instantiations and the two signals must be tied together in the design file. If the PLL-enable port is used in one megafunction instance and not the other, the PLLs are not shared, and a warning appears during compilation.

Use pll_areset input port This option gives you control over the asynchronous reset port of the fast PLL that is used with this function.

When the transmitter shares the PLL with the receiver and the pll_areset port is used, this port must be used in both megafunction instantiations and the two signals must be tied together in the design file. If the PLL-enable port is used in one megafunction instance and not the other, the PLLs are not shared, and a warning appears during compilation.

The PLL must be reset in order for the output clock phase relationships to be set correctly when the PLL loses lock or if the PLL input reference clock is not stable when the device completes the configuration processSERDES Transmitter/Receiver (ALTLVDS) Megafunction User Guide November 2008 Altera Corporation

Chapter 2: Getting Started 25MegaWizard Plug-In Manager Page Options and DescriptionsAlign clock to the center of the data window

When enabled, a phase shift of 90 is added to the clock to center the clock in the data. Use this parameter for PLL merging if the receiver has the option enabled.

This option is available only for Arria GX, Stratix II GX, Stratix II, and HardCopy II devices when SERDES is implemented in logic cells, and for Cyclone II devices. For Cyclone III, Stratix IV, and Stratix III (LE Implementation) devices, the option is always enabled.

Enable self-reset on lost lock in PLL

If enabled, the PLL resets automatically whenever it loses lock.

This option is available only for Stratix IV, Stratix III, and Cyclone III devices when SERDES is implemented in logic cells.

Use shared PLL(s) for receivers and transmitters

When this option is enabled, your LVDS receivers and transmitters can share the same PLL.

This option can be used if the LVDS receivers and transmitters use the same input clock frequency, deserialization factor, and data rates.

Register tx_in input port using If enabled, specify whether input registers are clocked by tx_inclock or by tx_coreclock. When PLLs are shared, the tx_inclock port should be connected to the same reference clock as the receiver function. For example, if tx_inclock is connected to a 500 MHz input reference clock, and the parallel data rate is not 500 MHz, then the parallel data should be registered using tx_coreclock, that runs at the output serial data rate divided by the deserialization factor. This frequency matches the parallel data rate from the FPGA core.

If you turn this parameter off, a warning message appears that directs you to pre-register the inputs in the logic that feeds the transmitter. When using Cyclone series devices with the ALTLVDS megafunction, the interface will always send the MSB of your parallel data first.

Table 22. ALTLVDS Transmitter Frequency/PLL Settings Page Options and Descriptions (Page 4) (Part 2 of 2)

Option Description Comments November 2008 Altera Corporation SERDES Transmitter/Receiver (ALTLVDS) Megafunction User Guide

26 Chapter 2: Getting StartedMegaWizard Plug-In Manager Page Options and DescriptionsPage 5 is the Transmitter settings page. It is used to specify the transmitter settings options. The options for this page are described in Table 23.

Table 23. ALTLVDS Transmitter Settings Page Options and Descriptions (Page 5) (Part 1 of 2)


Use tx_outclock output port The tx_outclock signal is associated with the serial transmit data stream.

Except for the following parameter configurations, every tx_outclock now goes through the shift register logic:

When outclock_divide_by = 1, or When outclock_divide_by = deserialization_factor (for odd factors only) and outclock_duty_cycle is 50.

What is the outclock divide factor (B)?

Specifies the frequency of the tx_outclock port as [transmitter output data rate / B]. For valid values, refer to the relevant device handbook.

The tx_outclock frequency is the transmitter output data rate divided by the outclock divide factor.

The outclock_duty_cycle of 50 is not supported when:

deserialization_factor is 5, 7 or 9 outclock_divide_by = deserialization_factor

outclock_multiply_by is 2. This is for Cyclone II and Cyclone III (always) and Stratix IV, Stratix III, and Stratix II when IMPLEMENT_IN_LES is ON.

Note that for SERDES factor of 5 and 9, outclock divide factor available are 1, 5, and 9, respectively. There is no 2.

This is for the Quartus II software version 8.1

What is the phase alignment of tx_outclock with respect to tx_out (in degrees)?

This value specifies the phase alignment of tx_outclock with respect to tx_out or tx_inclock.

This option is available only if the tx_outclock port is used.

Use tx_locked output port This port allows you to monitor the lock status of the PLL.

The status of the lock port is identical for the transmitter and receiver when shared PLLs are used.SERDES Transmitter/Receiver (ALTLVDS) Megafunction User Guide November 2008 Altera Corporation

Chapter 2: Getting Started 27MegaWizard Plug-In Manager Page Options and DescriptionsLVDS Transmitter Using an External PLLThis section discusses the options available for configuring the LVDS transmitter megafunction if an external PLL is used. To use an external PLL, select Use External PLL on page 3 of the MegaWizard Plug-In Manager. The options for this page are described in Table 21 on page 23.

If you choose to implement the LVDS transmitter using an external PLL, you must implement a PLL outside of the LVDS megafunction. You must ensure your circuit has the correct input and functionality to generate an appropriate clock frequency, and is connected to the LVDS transmitter correctly.

f For more information about external PLL options, refer to the AN 409: Design Example Using the ALTLVDS Megafunction & the External PLL Option in Stratix II Devices.

Use tx_coreclock output port This port is used to show the core clock frequency during simulation. The tx_coreclock port should be used to register all logic that feeds the LVDS transmitter function. If any other clock feeds the transmit function, your design must implement the clock domain transfer circuitry.

You need to add a false path constraint from the slow_clock to the fast_clock in the ALTLVDS_TX megafunction, whenever the faster core_clock implementation is used for odd deserialization factors.

When using the transmitter function of ALTLVDS (ALTLVDS_TX), you may get setup timing violations when using tx_inclock to register the data that feeds the SERDES blocks. The ALTLVDS_TX megafunction gives you the choice to register the tx_in data with either tx_inclock or tx_coreclock. Beginning in Quartus II version 5.1, the default setting is tx_coreclock. Using tx_coreclock to register the data before it feeds the SERDES is the better choice since it will have the optimal phase position to register the data with respect to the high speed clock that drives the SERDES.

Your setup timing violations should be eliminated when using tx_coreclock instead of tx_inclock to register the data in the ALTLVDS_TX function. Additionally, you should see better timing margins when using tx_coreclock instead of tx_inclock even if you do not have timing violations

What is the clock resource used for tx_coreclock?

This value specifies the clock resource type fed to the tx_coreclock port. Allowed values are Auto Selection (type is determined by the compiler), Global Clock, and Regional Clock. The default value is Auto Selection.

This information assists with clock management in the device.

Table 23. ALTLVDS Transmitter Settings Page Options and Descriptions (Page 5) (Part 2 of 2)

Option Description Comments November 2008 Altera Corporation SERDES Transmitter/Receiver (ALTLVDS) Megafunction User Guide

28 Chapter 2: Getting StartedMegaWizard Plug-In Manager Page Options and DescriptionsLVDS Transmitter Using External PLL and Dedicated SERDES Block

The ability to use a dedicated SERDES block in your LVDS transmitter and to clock the transmitter using an external PLL is device-dependent.

If you use a Stratix IV and a Stratix III device, clock your LVDS transmitter using an external PLL, and implement the SERDES for the transmitter using a dedicated SERDES block, a notification window pops up after you enter these settings on page 3 of the MegaWizard Plug-In Manager (Figure 21).

If you use an Arria GX, Stratix II, Stratix II GX, or HardCopy II device, clock your LVDS transmitter using an external PLL, and implement the SERDES for the transmitter using a dedicated SERDES block, a different notification window pops up after you enter these settings on page 3 of the MegaWizard Plug-In Manager (Figure 22).

For Stratix, Stratix GX, and HardCopy Stratix devices, if you implement the SERDES for your LVDS transmitter using a dedicated SERDES block, you do not have the option to use an external PLL.

The Cyclone series of devices (Cyclone III, Cyclone II, and Cyclone devices) do not have a dedicated SERDES block available for use by your LVDS transmitter. Therefore, you do not have the option to use a dedicated SERDES block in these devices.

Figure 21. MegaWizard Plug-In Manager Notification for Stratix III Device (LVDS Transmitter)

Figure 22. MegaWizard Plug-In Manager Notification for Other Devices (LVDS Transmitter)SERDES Transmitter/Receiver (ALTLVDS) Megafunction User Guide November 2008 Altera Corporation

Chapter 2: Getting Started 29MegaWizard Plug-In Manager Page Options and DescriptionsAfter you select Use External PLL and do not select Implement Serializer/Deserializer circuitry in logic cells on page 3 of the MegaWizard Plug-In Manager, and click Next, the Transmitter settings page appears. If you choose to use an external PLL, this page appears only if you choose to implement SERDES in a dedicated SERDES block.

This page is the same as the Transmitter settings page that appears when you choose to use an internal PLL, except the options to create tx_locked and tx_coreclock output ports are not available. The options that appear in the Transmitter settings page are described in Table 23 on page 26.

LVDS Transmitter Using External PLL and SERDES in LEs

If you use an Arria GX, Stratix series, Cyclone series, HardCopy II, or HardCopy Stratix device, clock your LVDS transmitter using an external PLL, and implement the SERDES for the transmitter using logic cells, a notification window pops up after you enter these settings on page 3 of the MegaWizard Plug-In Manager (Figure 22).

The Transmitter settings page does not appear.

MegaWizard Plug-In Manager Pages for the LVDS ReceiverOn page 3, after you select the LVDS receiver, depending on the device you selected, you can choose to implement the SERDES circuitry in logic cells or in a dedicated SERDES block. Similarly, depending on the device, you can choose to use an external PLL. In addition, for the LVDS receiver only, you can choose to enable DPA mode.

LVDS Receiver Using a Dedicated SERDES Block or SERDES in LEsThis section discusses the options available for configuring the LVDS receiver megafunction if an internal PLL is used.

On page 3, several options can be customized for the receiver settings. The options are described in Table 24. Except for the option to enable DPA mode, these options are the same as those described in Table 21 on page 23 for the LVDS transmitter. However, these meanings are slightly different for the LVDS receiver, because both the data flow and SERDES functionality are reversed.

Figure 23. MegaWizard Plug-In Manager Notification for SERDES in LEs (LVDS Transmitter) November 2008 Altera Corporation SERDES Transmitter/Receiver (ALTLVDS) Megafunction User Guide

210 Chapter 2: Getting StartedMegaWizard Plug-In Manager Page Options and DescriptionsPage 4 of the MegaWizard Plug-In Manager is the Frequency/PLL settings page. This page appears only if an internal PLL is used.

Table 24. ALTLVDS Receiver Settings Page Options and Descriptions (Page 3)


Implement Serializer/Deserializer circuitry in logic cells

If not enabled, the megafunction takes advantage of the dedicated SERDES circuitry in the device. If enabled, the SERDES circuitry is implemented in logic cells. This feature is supported by Arria GX, Stratix IV, Stratix III, Stratix II, Stratix II GX, Stratix GX, Stratix, HardCopy II, and HardCopy Stratix devices. In the Cyclone series devices, the SERDES circuitry is always implemented in logic cells.

If enabled, the receiver starts its operation on the first fast clock edge after the PLL is locked. This option is intended for slow speeds and byte alignment may be different from the hard SERDES implementation.

Enable Dynamic Phase Alignment mode (receiver only)

If enabled, the DPA mode helps to correct skew created by different trace lengths on the data channels routed to the device. This mode adds several ports and parameters to the megafunction instantiation. This option is available for Arria GX, Stratix III, Stratix II, Stratix II GX, Stratix GX, and HardCopy II devices only.

Enabling the DPA mode changes the appearance of the graphic representation of the megafunction in the left-hand pane. When the DPA mode is turned on, two pages are added to the MegaWizard Plug-In Manager to include the additional DPA mode ports and parameters (the DPA settings 1 and DPA settings 2 pages).

What is the number of channels? The number of input channels available for the LVDS receiver. The allowed values depend on the pins available in the device. For the allowed values for your device, refer to the relevant device handbook.

For example, if the number of channels is 44, an rx_in[43..0] port is created. Altera recommends you to use the

ALTIOBUF megafunction to connect the channels to actual FPGA pins via the I/O buffer. By using ALTIOBUF megafunction, you can control whether the buffer should be differential.

For further details, refer to the I/O Buffer (ALTIOBUF) Megafunction User Guide.

What is the deserialization factor? This value determines the number of serial input data bits that the receiver deserializes to send to the core on a single cycle. For the valid deserialization factors for your device, refer to the relevant device handbook.

For example, if the deserialization factor is 10 and the number of input channels is 1, the transmitter deserializes every 10 serial bits into 10 bits of parallel data to send to the core. If the deserialization factor is 10 and the number of channels is 44, an rx_out[439..0] port is created.

Use External PLL This determines whether to use an external PLL to clock the SERDES receiver. If this option is not enabled, the megafunction automatically implements an internal PLL to clock the LVDS receiver block. If this option is enabled, a separate PLL must be used to provide the clocking source. It is your responsibility to make the necessary connections.

If not enabled, the next page displays the PLL settings. The PLL settings page is skipped if this option is enabled.

Take note when you have a deserialization factor of two, the SERDES is bypassed and its functionality is implemented in DDR registers. You need at least a deserialization factor of four to use the external PLL option.SERDES Transmitter/Receiver (ALTLVDS) Megafunction User Guide November 2008 Altera Corporation

Chapter 2: Getting Started 211MegaWizard Plug-In Manager Page Options and DescriptionsTable 25 describes the options you have on page 4 to customize the frequency and PLL settings, depending on the device and options you selected on previous pages. These options are different than those described in Table 22 on page 24 for the LVDS transmitter.

Table 25. ALTLVDS Receiver Frequency and PLL Settings Options (Page 4) (Part 1 of 3)


What is the output data rate? This value specifies the data rate for the input channel of the receiver, in Mbps. For data rate ranges, refer to the specific DC & Switching Characteristics chapter in the appropriate device handbook.

This value determines the allowed input clock rate values.

Specify the input clock rate by The value specifies the input clock frequency to the internal PLL. The allowed values depend on the input data rate selected.

Use source-synchronous mode of the PLL

If enabled, the phase relationship between data and clock at the pin is maintained at the data capture point. Selecting this option forces the megafunction instantiation to make the required phase adjustments to guarantee a consistent relationship between the clock and data at the capture register and at the pin.

This option should always be selected, unless you have already performed all of the necessary phase adjustments manually. Altera recommends that you enable this option when using non-dedicated SERDES schemes. This option is available only if the SERDES is implemented in LEs.

Align clock to the center of the data window

When enabled, a phase shift of 90 is added to the clock to center the clock in the data.

This option is available only for Arria GX, Stratix II GX, Stratix II, and HardCopy II devices when SERDES is implemented in logic cells, and for Cyclone II devices. For Cyclone III devices, Stratix IV, and Stratix III (LE Implementation) devices, this option is not available.

Enable self-reset on lost lock in PLL

If enabled, the PLL resets automatically whenever it loses lock.

This option is available only for Stratix IV, Stratix III and Cyclone III devices when SERDES is implemented in logic cells.


When this option is enabled, your LVDS receivers and transmitters can share the same PLL.

This option can be used if the LVDS receivers and transmitters use the same input clock frequency, deserialization factor, and data rates. November 2008 Altera Corporation SERDES Transmitter/Receiver (ALTLVDS) Megafunction User Guide

212 Chapter 2: Getting StartedMegaWizard Plug-In Manager Page Options and DescriptionsUse pll_areset input port This option gives you control over the asynchronous reset port of the fast PLL that is used with this function.

When the transmitter shares the PLL with the receiver and the pll_areset port is used, this port must be used in both megafunction instantiations and the two signals must be tied together in the design file. If the pll_areset port is used in one megafunction instance and not the other, the PLLs are not shared, and a warning appears during compilation.

The PLL must be reset in order for the output clock phase relationships to be set correctly when the PLL loses lock or if the PLL input reference clock is not stable when the device completes the configuration process.

Use rx_pll_enable input port This port gives you control over the enable port of the fast PLL that is used with this function.

If the receiver shares the PLL with the transmitter, and the rx_pll_enable port is used, this port must be used in both megafunction instantiations and the two signals must be tied together in the design file. If the PLL-enable port is used in one megafunction instance and not the other, the PLLs are not shared, and a warning appears during compilation.

Use rx_locked output port This port allows you to monitor the lock status of the PLL. The status of the lock port is identical for the transmitter and the receiver when shared PLLs are used. In this case, monitor the lock output from the receiver megafunction.

What is the phase alignment of rx_in with respect to the rising edge of 'rx_inclock'? (in degrees)

This value determines the phase alignment of the data received by the receiver core with respect to rx_inclock. Available values are 0 (edge-aligned), 45, 90, 135, 180 (center-aligned), 225, 270, 315.If the DPA mode is not used, the extra two pages for DPA do not appear, but the option, What is the alignment of data with respect to the rising edge of rx_inclock? (in degrees) is added.

This option is only available if DPA mode is not enabled.


Option Description CommentsSERDES Transmitter/Receiver (ALTLVDS) Megafunction User Guide November 2008 Altera Corporation

Chapter 2: Getting Started 213MegaWizard Plug-In Manager Page Options and DescriptionsIf the DPA mode is enabled, the DPA settings 1 and DPA settings 2 pages appear. The DPA mode is supported by Arria GX, Stratix IV, Stratix III, Stratix II, Stratix II GX, Stratix GX, and HardCopy II devices only.

The options on the DPA settings 1 page are described in Table 26.

What is the clock resource used for rx_outclock?

This value specifies the clock resource type fed from the rx_outclock port. Allowed values are Auto Selection (type is determined by the compiler), Global Clock, and Regional Clock. The default value is Auto Selection.

This information assists with clock management in the device.

Enable FIFO for DPA channels The phase-compensation FIFO synchronizes parallel data to the global clock domain of the core. This option is available only in Stratix GX devices when the DPA mode is enabled.



Table 26. ALTLVDS Receiver DPA Settings 1 Page Options and Descriptions (Page 5) (Part 1 of 2)


Use rx_divfwdclk output port and bypass the DPA FIFO

If enabled, the DPA clock is divided by the deserialization factor and then forwarded to the core. The DPA clock drives the bitslip and alignment circuitry, bypassing the FIFO.

This feature is the soft CDR feature. It is available in Stratix IV and Stratix III devices only.

What is the simulated recovered clock phase drift?

The Quartus II software supports simulation of the recovered clock using the user-specified ppm value. The ppm value specifies the number of clock cycles drift between the transmitter and the receiver after a million clock cycles. The drift is positive if the transmitter is faster than the receiver, and negative if the receiver is faster than the transmitter. The Quartus II simulator simulates the ppm variation by shifting the recovered data and clock based on the user-specified ppm value.

This feature is available in Stratix IV and Stratix III devices only. It is part of the soft-CDR feature. It is available only if the Use rx_divfwdclk output port and bypass the DPA FIFO option is enabled.

Use rx_dpll_enable input port This port enables the path through the DPA circuitry. The option supports dynamic, channel-by-channel control of the DPA circuitry.

To enable the DPA circuitry for a channel, set the port for the target channel to 1. If this port is not used, the Quartus II software enables all of the channels. This option is available only if the Use rx_divfwdclk output port and bypass the DPA FIFO option is disabled. November 2008 Altera Corporation SERDES Transmitter/Receiver (ALTLVDS) Megafunction User Guide

214 Chapter 2: Getting StartedMegaWizard Plug-In Manager Page Options and DescriptionsThe options on the DPA Settings 2 page are described in Table 27.

f For more information about the DPA receiver circuit, refer to the AN 236: Using Source-Synchronous Signaling with DPA in Stratix GX Devices.

The options on the Receiver settings page are described in Table 28.

Use rx_dpll_hold input port This port prevents the DPA circuitry from switching to a new clock phase on the target channel. Each DPA block monitors the phase of the incoming data stream continuously, and selects a new clock phase when needed. When this port is held high, the selected channels hold their current phase setting.

Use rx_fifo_reset input port This port resets the FIFO between the DPA circuit and the data alignment circuit. The FIFO holds data passing between the DPA and the LVDS clock domains. When this port is held high, the FIFOs in the selected channels are reset.

This option is available only if the Use rx_divfwdclk output port and bypass the DPA FIFO option is disabled.

Table 26. ALTLVDS Receiver DPA Settings 1 Page Options and Descriptions (Page 5) (Part 2 of 2)


Table 27. ALTLVDS Receiver DPA Settings 2 Options (Page 6)

Parameter Description Comments

Use rx_reset input port This port resets all of the components of the DPA circuit.

The DPA circuit must be retrained after it is reset using this port.

Use rx_dpa_locked output port The DPA block samples the data on one of eight phase clocks with a 45 resolution between phases. This port lets you monitor the status of the DPA circuit and determine when it has locked onto the phase closest to the incoming data phase. rx_dpa_Locked will be de-asserted for at least one parallel clock cycle.

After power up or reset, the rx_dpa_locked signal is asserted after the DPA circuitry acquires an initial lock to the optimum phase. You must not use the rx_dpa_locked signal to validate the integrity of the LVDS link. Use error checkers (for example, CRC or DIP4) to validate the integrity of the LVDS link.

Use a DPA initial phase selection of This option selects the initial phase setting. Specify whether to enable this option and its value. Simulation honors this phase selection in simulating the forwarded clock.

This option is available for Stratix IV and Stratix III devices only.

Align DPA to rising edge of data only This option determines whether the DPA aligns to the rising edge of the data only or to both the rising and falling edges of the data.

This option is available for Stratix IV and Stratix III devices only.SERDES Transmitter/Receiver (ALTLVDS) Megafunction User Guide November 2008 Altera Corporation

Chapter 2: Getting Started 215MegaWizard Plug-In Manager Page Options and DescriptionsTable 28. ALTLVDS Receiver Settings Page Options and Descriptions (Page 7) (Part 1 of 2)

Parameter Description Comments

Register outputs If this option is enabled, the outputs of the receiver are registered by rx_outclock.

If you do not register the receiver outputs here, you must register them in the design logic that is fed by the receiver and specify a 'Source Multiply' assignment from the receiver to the output registers with a value equal to the deserialization factor.

Use 'rx_channel_data_align' input port This port lets you control bit insertion on a channel-by-channel basis to align the word boundaries of the incoming data. The data slips one bit for every pulse on rx_channel_data_align port. This option is available only if a dedicated SERDES block is used.

The following requirements must be met for this port:

The minimum pulse width is one period of the parallel clock in the logic array (rx_outclock).

The minimum low time between pulses is one period of the parallel clock.

There is no maximum high or low time.

Valid data is available two parallel clock cycles after the rising edge of rx_channel_data_align.

Use 'rx_cda_reset' input port This port is available only if Use 'rx_channel_data_align' input port is turned on. The port resets the data alignment circuitry, restoring the latency bit counter to zero. This option is available only if a dedicated SERDES block is used.

Use 'rx_cda_max' output port This port indicates when the rollover point has been reached in the data alignment circuit. This port is available only if Use 'rx_channel_data_align' input port is turned on. This option is available only if a dedicated SERDES block is used.

After how many pulses does the data alignment circuitry restore the serial latency back to 0?

Available values for this option range from 1 to 11. The value does not have to be the same as the deserialization factor. This option is available only if a dedicated SERDES block is used.

Altera recommends you to set this value to be equal to or greater than the deserialization factor, allowing enough depth in the alignment circuit to cycle through an entire word.

Align data to the rising edge of clock LVDS input data is aligned at the rising edge of the LVDS clock. This option is available only if a dedicated SERDES block is used.

If the selection is unchecked, the LVDS data is aligned to the falling edge of the clock. November 2008 Altera Corporation SERDES Transmitter/Receiver (ALTLVDS) Megafunction User Guide

216 Chapter 2: Getting StartedMegaWizard Plug-In Manager Page Options and DescriptionsLVDS Receiver Using an External PLLThis section discusses the options available for configuring the LVDS receiver megafunction when an external PLL is used. To use an external PLL, select Use External PLL on page 3 of the MegaWizard Plug-In Manager. The options for this page are described in Table 24 on page 210.

If you choose to implement the LVDS receiver using an external PLL, you must implement a PLL outside of the LVDS megafunction. You must ensure your circuit has the correct input and functionality to generate an appropriate clock frequency, and is connected to the LVDS receiver correctly.

f For more information about external PLL, refer to AN 409: Design Example Using the ALTLVDS Megafunction & the External PLL Option in Stratix II Devices.

LVDS Receiver Using External PLL and Dedicated SERDES Block

The ability to use a dedicated SERDES block in your LVDS receiver and to clock the transmitter using an external PLL is device-dependent, just as it is for an LVDS transmitter.

If you use a Stratix IV or a Stratix III device, clock your LVDS receiver using an external PLL, and implement the SERDES for the receiver using a dedicated SERDES block, a notification window pops up after you enter these settings on page 3 of the MegaWizard Plug-In Manager Figure 24).

Enable bitslip control This port lets you control bit insertion to align the word boundaries of the incoming data. The data slips one bit for every pulse on rx_data_align port. This option is available only if the SERDES is implemented in LEs.

The port skips a bit when it is asserted long enough to be captured by the fast clock edge. rx_data_align is slightly different from the Stratix behavior in that, each pulse has to be long enough for one slow clock cycle (instead of two in Stratix).

Enable independent bitslip controls for each channel

If enabled, it allows independent rx_data_align port for each channel so you can control each channels bit-slip capability independently.

This option is available if the SERDES is implemented in LEs

Register the bitslip control input using 'rx_outclock'

This port allows you to enable the receivers synchronization register.

If you enable this option, you can also add an extra register to register rx_data_align port using rx_outclock.

This option is available if the SERDES is implemented in LEs.

Use 'rx_data_align_reset' input port If enabled, creates the reset port for the bit-slip circuitry.

This option is available if the SERDES is implemented in LEs.

Table 28. ALTLVDS Receiver Settings Page Options and Descriptions (Page 7) (Part 2 of 2)

Parameter Description CommentsSERDES Transmitter/Receiver (ALTLVDS) Megafunction User Guide November 2008 Altera Corporation

Chapter 2: Getting Started 217MegaWizard Plug-In Manager Page Options and DescriptionsIf you use an Arria GX, Stratix II, Stratix II GX, or HardCopy II device, clock your LVDS receiver using an external PLL, and implement the SERDES for the receiver using a dedicated SERDES block, a different notification window pops up after you enter these settings on page 3 of the MegaWizard Plug-In Manager (Figure 25).

In Stratix, Stratix GX, and HardCopy Stratix devices, if you implement the SERDES for your LVDS receiver using a dedicated SERDES block, you do not have the option to use an external PLL.

The Cyclone series of devices (Cyclone III, Cyclone II, and Cyclone devices) do not have a dedicated SERDES block available for use by your LVDS receiver. Therefore, you do not have the option to use a dedicated SERDES block in these devices.

After you select Use External PLL and do not select Implement Serializer/Deserializer circuitry in logic cells on page 3 of the MegaWizard Plug-In Manager, and then click Next, the DPA settings 1 page or the Receiver settings page appears.

This page is the same as the Receiver settings page that appears when you choose to use an internal PLL, except different options are disabled. The options that appear in the Receiver settings page are described in Table 28 on page 215.

Figure 24. MegaWizard Plug-In Manager Notification for Stratix III Device (LVDS Receiver)

Figure 25. MegaWizard Plug-In Manager Notification for Other Devices (LVDS Receiver) November 2008 Altera Corporation SERDES Transmitter/Receiver (ALTLVDS) Megafunction User Guide

218 Chapter 2: Getting StartedInstantiating Megafunctions in HDL Code or Schematic DesignsLVDS Receiver Using External PLL and SERDES in LEs

If you use an Arria GX, Stratix series, Cyclone series, HardCopy II, or HardCopy Stratix device, clock your LVDS receiver using an external PLL, and implement the SERDES for the receiver using logic cells, a notification window pops up after you enter these settings on page 3 of the MegaWizard Plug-In Manager (Figure 26).

The Receiver settings page appears with only the Use rx_data_align input port option available.

Common Pages for ALTLVDS Receiver and TransmitterPage 8 lists the simulation libraries required for functional simulation by third-party tools. On this page, you can choose to generate a synthesis area and timing estimation netlist.

Page 9 of the ALTLVDS MegaWizard Plug-In Manager displays a list of the types of files to be generated. The automatically generated Variation file contains wrapper code in the language you specified on page 2a. On page 9, you can specify additional types of files to be generated. Choose from the PinPlanner ports PPF file (.ppf), AHDL Include file (.inc), VHDL component declaration file, .cmp), Quartus II symbol file (.bsf), Instantiation template file ( .v), and Verilog HDL black box file (_bb.v). If you selected Generate netlist on page 8, the file for the synthesis area and timing estimation netlist is also available. A gray checkmark indicates a file that is automatically generated, and a red checkmark indicates an optional file.

f For more information about the ports and parameters for the ALTLVDS megafunction, refer to Chapter 3, Specifications.

Instantiating Megafunctions in HDL Code or Schematic DesignsWhen you use the MegaWizard Plug-In Manager to customize and parameterize a megafunction, it creates a set of output files that allow you to instantiate the customized function in your design. Depending on the language you choose in the MegaWizard Plug-In Manager, the wizard instantiates the megafunction with the correct parameter values and generates a megafunction variation file (wrapper file) in Verilog HDL (.v), VHDL (.vhd), or AHDL (.tdf), along with other supporting files.

The MegaWizard Plug-In Manager provides options to create the following files:

Figure 26. MegaWizard Plug-In Manager Notification for SERDES in LEs (LVDS Receiver)SERDES Transmitter/Receiver (ALTLVDS) Megafunction User Guide November 2008 Altera Corporation

Chapter 2: Getting Started 219Instantiating Megafunctions in HDL Code or Schematic Designs A sample instantiation template for the language of the variation file (_inst.v, _inst.vhd, or _inst.tdf)

Component Declaration File (.cmp) that can be used in VHDL Design Files

ADHL Include File (.inc) that can be used in Text Design Files (.tdf)

Quartus II Block Symbol File (.bsf) that can be used in schematic designs

Verilog HDL module declaration file that can be used when instantiating the megafunction as a black box in a third-party synthesis tool (_bb.v)

f For more information about the wizard-generated files, refer to the Quartus II Help or to the Recommended HDL Coding Styles chapter in volume 1 of the Quartus II Handbook.

Generating a Netlist for EDA Tool UseIf you use a third-party EDA synthesis tool, you can instantiate the megafunction variation file as a black box for synthesis. Use the VHDL component declaration or Verilog module declaration black box file to define the function in your synthesis tool, and then include the megafunction variation file in your Quartus II project.

If you enable the option to generate a synthesis area and timing estimation netlist in the MegaWizard Plug-In Manager, the wizard generates an additional netlist file (_syn.v). The netlist file is a representation of the customized logic used in the Quartus II software. The file provides the connectivity of the architectural elements in the megafunction but may not represent true functionality. This information enables certain third-party synthesis tools to better report area and timing estimates. Additionally, synthesis tools can use the timing information to focus timing-driven optimizations and improve the quality of results.

f For more information about using megafunctions in your third-party synthesis tool, refer to the appropriate chapter in the Synthesis section in volume 1 of the Quartus II Handbook.

Using the Port and Parameter DefinitionsInstead of using the MegaWizard Plug-In Manager, you can instantiate the megafunction directly in your Verilog HDL, VHDL, or AHDL code by calling the megafunction and setting its parameters as you would any other module, component, or subdesign. For the ALTLVDS megafunction, many ports and parameters are available for specific device families only, and some are available only when other features have been enabled. For example, in Stratix GX devices, rx_channel_data_align[] port is available only when the DPA mode option is turned on. When DPA mode is turned off, rx_data_align port is available for use.

1 Altera strongly recommends that you use the MegaWizard Plug-In Manager for complex megafunctions. The MegaWizard Plug-In Manager ensures that you set all megafunction parameters properly.

f Refer to Chapter 3, Specifications for a list of the megafunction ports and parameters. November 2008 Altera Corporation SERDES Transmitter/Receiver (ALTLVDS) Megafunction User Guide

220 Chapter 2: Getting StartedIdentifying a Megafunction After CompilationExample 21 contains the VHDL code from a Stratix LVDS receiver. This template can be used for any VHDL ALTLVDS function. Substitute appropriate ports and parameters as needed in your design.

Identifying a Megafunction After CompilationDuring compilation with the Quartus II software, analysis and elaboration is performed to build the structure of your design. To locate your megafunction in the Project Navigator window, expand the compilation hierarchy and find the megafunction by its name. To search for node names within the megafunction (using the Node Finder), click Browse in the Look in box and select the megafunction in the Hierarchy box (Figure 27).

Example 21. VHDL Code from the Stratix LVDS Receiver

INCLUDE "altlvds_rx.inc";

SUBDESIGN stratix_rx(

rx_in[0..0] : INPUT;rx_inclock : INPUT = GND;rx_pll_enable : INPUT = VCC;rx_data_align : INPUT;pll_areset : INPUT = GND;rx_out[3..0] : OUTPUT;rx_locked : OUTPUT;rx_outclock : OUTPUT;

)

VARIABLE

ALTLVDS_rx_component : altlvds_rx WITH (INTENDED_DEVICE_FAMILY = "Stratix",NUMBER_OF_CHANNELS = 1,DESERIALIZATION_FACTOR = 4,LPM_TYPE = "altlvds_rx",COMMON_RX_TX_PLL = "ON",OUTCLOCK_RESOURCE = "AUTO",INCLOCK_PERIOD = 9523,INPUT_DATA_RATE = 840,INCLOCK_DATA_ALIGNMENT = "EDGE_ALIGNED",REGISTERED_OUTPUT = "ON",REGISTERED_DATA_ALIGN_INPUT = "ON");

BEGIN

rx_locked = altlvds_rx_component.rx_locked;rx_out[3..0] = altlvds_rx_component.rx_out[3..0];rx_outclock = altlvds_rx_component.rx_outclock;altlvds_rx_component.pll_areset = pll_areset;altlvds_rx_component.rx_inclock = rx_inclock;altlvds_rx_component.rx_in[0..0] = rx_in[0..0];altlvds_rx_component.rx_data_align = rx_data_align;altlvds_rx_component.rx_pll_enable = rx_pll_enable;

END;SERDES Transmitter/Receiver (ALTLVDS) Megafunction User Guide November 2008 Altera Corporation

Chapter 2: Getting Started 221Identifying a Megafunction After CompilationYou can use the project hierarchy to find megafunction instantiations in the Floorplan Editor. Right-click on the megafunction you want to view, and choose the Quartus II editor in which you want to view it (Figure 28).

Figure 27. Compilation Hierarchy Window

Figure 28. Compilation Hierarchy Navigation Option November 2008 Altera Corporation SERDES Transmitter/Receiver (ALTLVDS) Megafunction User Guide

222 Chapter 2: Getting StartedDesign Example 1: LVDS-to-LVDS Bridge Using Different Clock You can also locate your megafunctions in the Node Finder when making assignments in the assignment editor. Figure 29 shows an example of how the megafunction logic is shown in the Node Finder.

Design Example 1: LVDS-to-LVDS Bridge Using Different Clock Frequencies

With the inclusion of DPA circuitry, Stratix II devices offer enhanced support for source-synchronous protocols. The enhanced source-synchronous channels on Stratix II devices support 1-Gbps data transfer, while the dedicated DPA circuitry simplifies printed circuit board design by eliminating signal-alignment issues introduced by clock-to-channel and channel-to-channel skew. Stratix II devices support a wide array of high-speed protocols and can be used to bridge high-speed interfaces.

This design example uses a Stratix II device to bridge a 1-Gbps LVDS interface using a 500-MHz reference clock to a 1-Gbps LVDS interface using a 250-MHz reference clock. The ALTLVDS receiver function uses DPA circuitry. The transmitter and receiver share one fast PLL.

The focus of this design is to illustrate the features available in the MegaWizard Plug-In Manager. No user logic is shown between the receiver and transmitter blocks, and all ports are connected to input or output pins. Most designs use custom logic for many of the control ports within the FPGA. However, for this design example, all such parameters are controlled outside of the Stratix II device.

Figure 29. Node Finder View of ALTLVDS Transmitter MegafunctionSERDES Transmitter/Receiver (ALTLVDS) Megafunction User Guide November 2008 Altera Corporation

Chapter 2: Getting Started 223Design Example 1: LVDS-to-LVDS Bridge Using Different Clock FrequenciesDesign FilesThe design files are available with this user guide in the Quartus II Project section and in the User Guides section of the Altera website (www.altera.com).

In this example, you create two files using the MegaWizard Plug-In Manager: one for an ALTLVDS receiver and one for an ALTLVDS transmitter. Both files are created in Verilog HDL (.vhd) and are included in your project directory when completed.

ExampleIn this example, you will complete the following tasks:

Generate a high-speed differential receiver in DPA mode using the ALTLVDS megafunction and the MegaWizard Plug-In Manager

Generate a high-speed differential transmitter using the ALTLVDS megafunction and the MegaWizard Plug-In Manager

Implement the receiver and transmitter functions in the device by adding your custom megafunctions to the project and compiling the project

Simulate the high-speed differential interface design using the ModelSim-Altera software

Generate an ALTLVDS Receiver and ALTLVDS TransmitterTo generate the LVDS receiver, perform the following steps:

1. Open the ALTLVDS_DesignExample.zip file and extract the Quartus II archive project ALTLVDS_stratixII.qar.

2. In the Quartus II software, open ALTLVDS_stratixII.qar and restore the archive file into your working directory.

3. Open the top-level block editor file ALTLVDS_stratixII.bdf. The file ALTLVDS_stratixII.bdf is an incomplete file that you will complete in the course of this example. The ALTLVDS megafunction created in this example are added to the top-level file.

4. Double-click anywhere in the white space in the block editor file. The Symbol window appears.

5. In the Symbol window, click on MegaWizard Plug-In Manager. Page 1 of the MegaWizard Plug-In Manager appears.

6. Select Create a new custom megafunction variation.

7. Click Next. Page 2a of the MegaWizard Plug-In Manager appears.

8. In the MegaWizard Plug-In Manager pages, select or verify the configuration settings shown in Table 29. Click Next to advance from one page to the next. November 2008 Altera Corporation SERDES Transmitter/Receiver (ALTLVDS) Megafunction User Guide

224 Chapter 2: Getting StartedDesign Example 1: LVDS-to-LVDS Bridge Using Different Clock Table 29. Configuration Settings for Design Example 1 (LVDS Receiver) (Part 1 of 2)

MegaWizard Plug-In Manager Page

MegaWizard Plug-In Manager Configuration Setting Value

2a Megafunction Under I/O, select ALTLVDS

Device family Stratix II

Output file type Verilog HDL

Output file name stratixii_rx

Return to this page for another create operation

Selected

3 Currently selected device family Stratix II

Match project/default Selected

This module acts as an LVDS receiver

Implement SERDES in logic cells Not selected

Enable Dynamic Phase Alignment mode (receiver only)

Selected

What is the number of channels? 8

What is the deserialization factor? 8

Use External PLL Not selected

4 What is the input data rate? 1 Gbps (1,000 Mbps)

Specify the input clock rate by Clock frequency

Clock frequency 500 MHz

Use shared PLLs(s) for receivers and transmitters

Selected

Use pll_areset input port Selected (The PLL must be reset in order for the output clock phase relationships to be set correctly when the PLL loses lock or if the PLL input reference clock is not stable when the device completes the configuration process.)

Use rx_pll_enable input port Selected

Use rx_locked output port Not selected

What is the clock resource for rx_outclock?

Auto selection

5 Use rx_dpll_enable input port Selected

Use rx_dpll_hold input port Selected

Use rx_fifo_reset input port Selected

6 Use rx_reset input port Selected

Reset DPA circuitry Automatically reset the bit serial FIFO when rx_dpa_locked rises for the first time.

Use rx_dpa_locked output port Selected

When should the rx_dpa_locked fall low?

When there are two phase changes in same direction.SERDES Transmitter/Receiver (ALTLVDS) Megafunction User Guide November 2008 Altera Corporation

Chapter 2: Getting Started 225Design Example 1: LVDS-to-LVDS Bridge Using Different Clock Frequencies9. Click Finish. The stratixii_rx module is built.

10. Click OK. The MegaWizard Plug-In Manager resets to page 2a to allow you to create a new custom megafunction variation for the LVDS transmitter.

11. In the MegaWizard Plug-In Manager pages, select or verify the configuration settings shown in Table 210.

7 Register outputs Selected

Use rx_channel_data_align input port Selected

Use rx_cda_reset input port Selected

Use rx_cda_max output port Selected

After how many pulses does the data alignment circuitry restore the serial data latency back to 0?

8

8 Generate netlist Not selected

9 Variation file (.v) Selected

PinPlanner ports file (.PPF) Selected

AHDL Include file (.inc) Selected

VHDL component declaration file (.cmp) Selected

Quartus II symbol file (.bsf) Selected

Instantiation template file (_inst.v) Selected

Verilog HDL black box file (_bb.v) Selected

Table 29. Configuration Settings for Design Example 1 (LVDS Receiver) (Part 2 of 2)



Table 210. Configuration Settings for Design Example 1 (LVDS Transmitter) (Part 1 of 2)



2a Megafunction Under I/O, select ALTLVDS

Device family Stratix II

Output file type Verilog HDL

Output file name stratixii_tx

Return to this page for another create operation

Not selected

3 Currently selected device family Stratix II

Match project/default Selected

This module acts as an LVDS transmitter

Implement SERDES in logic cells Not selected

What is the number of channels? 8

What is the deserialization factor? 8

Use External PLL Not selected November 2008 Altera Corporation SERDES Transmitter/Receiver (ALTLVDS) Megafunction User Guide

226 Chapter 2: Getting StartedDesign Example 1: LVDS-to-LVDS Bridge Using Different Clock 12. Click Finish. The stratixii_tx module is built.

13. Click OK.

14. Place the stratixii_tx symbol in the altlvds_stratixii block editor design file under the text INSERT STRATIXII_TX HERE, aligning the input and output ports with the signals already present in the design file.

15. Double-click anywhere in the white space of the design file. The Symbol window appears.

4 What is the output data rate? 1 Gbps (1,000 Mbps)

Specify the input clock rate by Clock frequency

Clock frequency 500 MHz

What is the phase alignment of tx_in with respect to the rising edge of tx_inclock (in degrees)

0

Use tx_pll_enable input port Selected

Use pll_areset input port Selected

(The PLL must be reset in order for the output clock phase relationships to be set correctly when the PLL loses lock or if the PLL input reference clock is not stable when the device completes the configuration process.)


Selected

Register tx_in using tx_coreclock

5 Use tx_outclock output port Selected

What is the outclock divide factor (B)? 4

What is the phase alignment of tx_outclock with respect to tx_out (in degrees)

0

Use tx_locked output port Selected

Use tx_coreclock output port Selected

What is the clock resource used for tx_coreclock?

Auto selection

6 Generate netlist Not selected

7 Variation file (.v) Selected

PinPlanner ports file (.PPF) Selected

AHDL Include file (.inc) Selected

VHDL component declaration file (.cmp) Selected

Quartus II symbol file (.bsf) Selected

Instantiation template file (_inst.v) Selected

Verilog HDL black box file (_bb.v) Selected

Table 210. Configuration Settings for Design Example 1 (LVDS Transmitter) (Part 2 of 2)


MegaWizard Plug-In Manager Configuration Setting ValueSERDES Transmitter/Receiver (ALTLVDS) Megafunction User Guide November 2008 Altera Corporation

Chapter 2: Getting Started 227Design Example 1: LVDS-to-LVDS Bridge Using Different Clock Frequencies16. Choose stratixii_rx from the Project library list and click OK (Figure 210). You may have to expand the Project folder to see the megafunctions it contains.

17. Place the stratixii_rx symbol in the altlvds_stratixII block editor design file under the text INSERT STRATIXII_RX HERE and align the input and output ports with the signals already present in the design file.

The block diagram file should look similar to Figure 210.

18. On the File menu, click Save.

19. On the Processing menu, click Start Compilation.

20. When the Full Compilation was successful message box appears, click OK.

Figure 210. Design Example 1 Symbol View of stratixii_rx

Figure 211. Design Example 1 Top-Level Block Design File November 2008 Altera Corporation SERDES Transmitter/Receiver (ALTLVDS) Megafunction User Guide

228 Chapter 2: Getting StartedDesign Example 1: LVDS-to-LVDS Bridge Using Different Clock Functional ResultsSimulate the ALTLVDS Receiver/Transmitter Design in the ModelSim-Altera Simulator

Simulate the design in the ModelSim-Altera software to generate a waveform display of the device behavior.

This user guide assumes that you are familiar with using the ModelSim-Altera tool before trying out the design example. If you are unfamiliar with using the ModelSim-Altera simulator, refer to the Support page for software products on the Altera website (www.altera.com). On the Support page, there are various links to topics such as installation, usage, and troubleshooting.

Set up the ModelSim-Altera simulator by performing the following steps:

1. Unzip the altlvds_ex1_msim.zip file to any working directory on your PC.

2. Start the ModelSim-Altera software.

3. On the File menu, click Change Directory.

4. Select the folder in which you unzipped the files. Click OK.

5. On the Tools menu, point to TCL and click Execute Macro. The Execute Do File dialog box will appear.

6. Select the altlvds_ex1_msim.do file and click Open. This is a script file for the ModelSim software that automates all the necessary settings for the simulation.

7. Verify the results shown in the Waveform Viewer window.

You can rearrange signals, remove signals, add signals, and change the radix by modifying the script in altlvds_ex1_msim.do. Figure 212 shows the expected simulation results in the ModelSim simulator.

This waveform file contains only the input and output pins that are shown. You can add internal post-compilation nodes with the Node Finder to view all of the data paths in the design. You can verify that tx_outclock has a 4-ns period, which corresponds to a 250-MHz clock rate, as specified in the design.

The input serial data rx_in is edge-aligned to the reference clock clk_in_500MHz, and the output serial data tx_out is edge-aligned to tx_outclock as specified in the transmitter megafunction.

Figure 212. Design Example 1 ModelSim Simulation ResultsSERDES Transmitter/Receiver (ALTLVDS) Megafunction User Guide November 2008 Altera Corporation

Chapter 2: Getting Started 229Design Example 2: Cyclone II ALTLVDS Using External PLL OptionThis simulation output verifies that 1-Gbps data can be successfully received by and transmitted from the Stratix II device.

You can change the input vectors in the waveform editor to experiment with the other features, such as data alignment, to view the functionality and help you understand the ALTLVDS megafunction.

Design Example 2: Cyclone II ALTLVDS Using External PLL OptionThe following design example illustrates the connection scheme used in Cyclone II devices for an ALTLVDS receiver and transmitter using a common PLL. The ALTLVDS_RX and ALTLVDS_TX functions are set up using the external PLL option. This example shows step by step how to set up the ALTLVDS_RX and ALTLVDS_TX functions. Note that the ALTPLL function has already been set up in the design file.

f For PLL-specific information and for examples of PLL clock relationships, refer to the ALTPLL Megafunction Users Guide.

You can use the external PLL option in ALTLVDS to give you direct access to all of the PLL clocks that are not accessible when you allow ALTLVDS to infer the PLL for you. This option gives you the ability to use the PLL output clocks throughout your design for other functions besides the serialization and deserialization of data.

Design FilesThe design files are available with this user guide in the Quartus II Project section and in the User Guides section of the Altera website (www.altera.com).

In this example, you create two files using the MegaWizard Plug-In Manager: one for an ALTLVDS receiver and one for an ALTLVDS transmitter. Both files are created in VHDL (.vhd) and are included in your project directory when completed. The PLL block is already customized in the design.

ExampleThis example shows how to design a 600 Mbps receiver with a deserialization factor of 8 and a 600 Mbps transmitter with the same deserialization factor of 8. The input reference clock frequency is 75 MHz.

In this example, you will perform the following activities:

Generate a high-speed differential receiver using the ALTLVDS megafunction and the MegaWizard Plug-In Manager.

Generate a high-speed differential transmitter using the ALTLVDS megafunction and the MegaWizard Plug-In Manager.

View description of the external PLL settings used to clock the transmitter and receiver blocks.

Implement the receiver, transmitter, and PLL in the device by adding your custom megafunctions to the pro