Ch4 Com Bi National Functions and Circuits

8/14/2019 Ch4 Com Bi National Functions and Circuits

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Dr. I. Damaj 1

Chapter 4

Combinational Functions and Circuits

Dr. I. Damaj 2

Overview

Functions and functional blocks

Rudimentary logic functions

Decoding

Encoding

Selecting Implementing Combinational Functions Using:

Decoders and OR gates

Multiplexers (and inverter)

ROMs

PLAs

PALs

Lookup Tables


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Dr. I. Damaj 3

Functions and Functional Blocks

The functions considered are those found to be very useful in design

Corresponding to each of the functions is a combinational circuit

implementation called a functional block.

In the past, many functional blocks were implemented as SSI, MSI,

and LSI circuits.

Today, they are often simply parts within a VLSI circuits.

Dr. I. Damaj 4

Rudimentary Logic Functions

Functions of a single variable X

Can be used on the

inputs to functional

blocks to implement

other than the blocksintended function

0

1

F 5 0

F 5 1

(a)

F 5 0

F 5 1

VCC or VDD

(b)

X F 5 X

(c)

X F 5 X

(d)

TABLE 4-1Functions of One Variable

X F = 0 F = X F = F = 1

0

1

0

0

0

1

1

0

1

1

X

= = =

= ==


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Dr. I. Damaj 5

Multiple-bit Rudimentary Functions

Multi-bit Examples:

A wide line is used to represent

a buswhich is a vector signal

In (b) of the example, F = (F3, F2, F1, F0) is a bus.

The bus can be split into individual bits as shown in (b) Sets of bits can be split from the bus as shown in (c)

for bits 2 and 1 of F.

The sets of bits need not be continuous as shown in (d) for bits 3, 1, and 0

of F.

F

(d)

0

F31 F2

F1A F0

(a)

0

1

A

1

23

4F

0

(b)

4 2:1 F(2:1)2

F

(c)

4 3,1:0 F(3), F(1:0)3

A A

Dr. I. Damaj 6

Enabling Function

Enablingpermits an input signal to pass through to an output

Disablingblocks an input signal from passing through to an output,replacing it with a fixed value

The value on the output when it is disable can be Hi-Z (as for three-

state buffers), 0 , or 1

When disabled, 0 output

When disabled, 1 output

XF

EN

(a)

EN

XF

(b)


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Dr. I. Damaj 7

Decoding - the conversion of an n-bit input code to an m-bit output

code with n m 2n such that each valid code word produces aunique output code

Circuits that perform decoding are called decoders

Here, functional blocks for decoding are

called n-to-mline decoders, where m 2n, and

generate 2n

(or fewer) minterms for the ninput variables

Decoding

Dr. I. Damaj 8

1-to-2-Line Decoder

2-to-4-Line Decoder

Note that the 2-4-line

made up of 2 1-to-2-

line decoders and 4 AND gates.

Decoder Examples

A D 0 D 1

0 1 0

1 0 1

(a) (b)

D1 5 AA

D0 5 A

A1

0

0

1

1

A 0

0

1

0

1

D 0

1

0

0

0

D 1

0

1

0

0

D 2

0

0

1

0

D3

0

0

0

1

(a)

D 0 = A 1 A 0

D 1 = A 1 A 0

D 2 = A 1 A 0

D 3 = A 1 A 0

(b)

A 1

A 0

=

=


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Dr. I. Damaj 9

Decoder Expansion General procedure given in book for any decoder with ninputs and

2noutputs.

This procedure builds a decoder backward from the outputs.

The output AND gates are driven by two decoders with their

numbers of inputs either equal or differing by 1.

These decoders are then designed using the same procedure until2-to-1-line decoders are reached.

The procedure can be modified to apply to decoders with the

number of outputs 2n

Dr. I. Damaj 10

Decoder Expansion - Example 1

3-to-8-line decoder Number of output ANDs = 8

Number of inputs to decoders driving output ANDs = 3

Closest possible split to equal

2-to-4-line decoder

1-to-2-line decoder 2-to-4-line decoder

Number of output ANDs = 4

Number of inputs to decoders driving output ANDs =2

Closest possible split to equal Two 1-to-2-line decoders

See next slide for result


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Dr. I. Damaj 11

Decoder Expansion - Example 1

Result

3-to-8 Line decoder

1-to-2-Line decoders

4 2-input ANDs 8 2-input ANDs

2-to-4-Linedecoder

D0A 0

A 1

A 2

D1

D2

D3

D4

D5

D6

D7

Dr. I. Damaj 12

4.3 DecodingTruth Table for 3to8-Line Decoder

An n-bit binary code could represent up to 2n distinct elements of Coded information


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4.3 Decoding3-to-8-Line Decoder

An n-bit binary code

Could represent up to

2n distinct elements of

Coded information

Dr. I. Damaj 14

In general, attach m-enabling circuits to the outputs

See truth table below for function

Note use of Xs to denote both 0 and 1

Combination containing two Xs represent four binary

combinations

Alternatively, can be viewed as distributing value of signal EN to 1 of4 outputs

In this case, called a

demultiplexer

EN

A 1

A 0D0

D1

D2

D3

(b)

EN A 1 A 0 D 0 D 1 D 2 D 3

0

1

1

1

1

X

0

0

1

1

X

0

1

0

1

0

1

0

0

0

0

0

1

0

0

0

0

0

1

0

0

0

0

0

1

(a)

Decoder with Enable


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Dr. I. Damaj 15

Encoding

Encoding - the opposite of decoding - the conversion of an m-bit

input code to an n-bit output code with n m 2n such that eachvalid code word produces a unique output code

Circuits that perform encoding are called encoders

An encoder has 2n (or fewer) input lines and n output lines whichgenerate the binary code corresponding to the input values

Typically, an encoder converts a code containing exactly one bit that

is 1 to a binary code corresponding to the position in which the 1

appears.

Dr. I. Damaj 16

Encoder Example

A decimal-to-BCD encoder

Inputs: 10 bits corresponding to decimal digits

0 through 9, (D0, , D9)

Outputs: 4 bits with BCD codes Function: If input bit Di is a 1, then the output

(A3, A2, A1, A0) is the BCD code for i,

The truth table could be formed, but

alternatively, the equations for each of the four

outputs can be obtained directly.


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Dr. I. Damaj 17

Encoder Example (continued)

Input Di is a term in equation Aj if bit Aj is 1 in the

binary value for i.

Equations:

A3 = D8 + D9A2 = D4 + D5 + D6 + D7

A1 = D2 + D3 + D6 + D7A0 = D1 + D3 + D5 + D7 + D9

Dr. I. Damaj 18

Another Example

An encoder is a digital function that performs the inverse operation of a

decoder. It has 2n (or fewer) input lines and n output lines.


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Dr. I. Damaj 19

Another Example

For the 8-to-3-line encoder, the resultant

equations are:

A0 = D1 + D3 + D5 + D7 A1 = D2 + D3 + D6 + D7 A2 = D4 + D5 + D6 + D7

These equations can be implemented withthree 4-input OR gates.

Dr. I. Damaj 20

Priority Encoder

If more than one input value is 1, then the encoder just designed

does not work.

One encoder that can accept all possible combinations of input

values and produce a meaningful result is a priority encoder.

Among the 1s that appear,

it selects the most significant input position (or the least

significant input position) containing a 1

and responds with the corresponding binary code for that

position.


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Dr. I. Damaj 21

Priority Encoder

Input D3 has the highest priority, so regardless of the values ofthe other inputs, the output for A1A0 is 11.

The valid output (V) is set to 1 only when 1 or more of the inputsare equal to 1.

Dr. I. Damaj 22

Priority Encoder


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Dr. I. Damaj 23

Selecting of data or information is a critical function in digital

systems and computers

Circuits that perform selecting have:

A set of information inputs from which the selection is made

A single output

A set of control lines for making the selection

Logic circuits that perform selecting are called multiplexers

Selecting can also be done by three-state logic or transmission

gates

Selecting

Dr. I. Damaj 24

Multiplexers

A multiplexer selects information from an input line

and directs the information to an output line

A typical multiplexer has n control inputs (Sn 1,

S0) called selection inputs, 2n information inputs (I2

n

1, I0), and one output Y A multiplexer can be designed to have minformation

inputs with m < 2n as well as nselection inputs


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Dr. I. Damaj 25

2-to-1-Line Multiplexer Since 2 = 21, n = 1

The single selection variable S has two values:

S = 0 selects input I0 S = 1 selects input I1

The equation:

Y = SI0 + SI1

The circuit:

S

I0

I1

Decoder EnablingCircuits

Y

Dr. I. Damaj 26

2-to-1-Line Multiplexer (continued)

Note the regions of the multiplexer circuit shown:

1-to-2-line Decoder

2 Enabling circuits

2-input OR gate

To obtain a basis for multiplexer expansion, we combine the

Enabling circuits and OR gate into a 2 2 AND-OR circuit:

1-to-2-line decoder

2 2 AND-OR

In general, for an 2n-to-1-line multiplexer:

n-to-2n-line decoder

2n 2 AND-OR


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Dr. I. Damaj 27

Example: 4-to-1-line Multiplexer 2-to-22-line decoder

22 2 AND-OR

S1Decoder

S0

Y

S1Decoder

S0

Y

S1Decoder

4 3 2 AND-ORS0

Y

I2

I3

I1

I0

Dr. I. Damaj 28

Other Selection Implementations

Three-state logic in place of AND-OR

Gate input cost = 14 compared to 22 (or 18) for gate

implementation

I0

I1

I2

I3

S1

S0

(b)

Y


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Dr. I. Damaj 29

Other Selection Implementations

Transmission Gate Multiplexer

Gate input

cost = 8

compared

to 14 for

3-state logic

and 18 or 22

for gate logic

S0

S1

I0

I1

I2

I3

Y

TG(S0 5 0)

TG(S1 5 0)

TG(S1 5 1)

TG(S0 5 1)

TG(S0 5 0)

TG(S0 5 1)

Dr. I. Damaj 30

Combinational Function Implementation

Alternative implementation techniques:

Decoders and OR gates

Multiplexers (and inverter)

ROMs PLAs

PALs

Lookup Tables

Can be referred to as structured implementation methodssince a specific underlying structure is assumed in eachcase


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Dr. I. Damaj 31

Decoder and OR Gates Implement mfunctions ofnvariables with:

Sum-of-minterms expressions

One n-to-2n-line decoder

mOR gates, one for each output

Approach:

Find the truth table for the functions

Make a connection to the corresponding OR from the

corresponding decoder output wherever a 1 appears in the truthtable

Dr. I. Damaj 32

Decoder and OR Gates Example

Implement the following set of odd parity functions of (A7, A6, A5, A3)

P1 = A7 xor A5 xor A3P2 = A7 xor A6 xor A3P4 = A7 xor A6 xor A5

Finding sum of

minterms expressionsP1 = m(1,2,5,6,8,11,12,15)

P2 = m(1,3,4,6,8,10,13,15)

P4 = m(2,3,4,5,8,9,14,15)

Find circuit

Is this a good idea?

0

1

2

3

45

6

7

8

9

10

11

12

13

14

15

A7A6A5

A4

P1

P4

P2


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Dr. I. Damaj 33

Multiplexer Approach 1 Implement mfunctions ofnvariables with:

Sum-of-minterms expressions

An m-wide 2n-to-1-line multiplexer

Design: Find the truth table for the functions.

In the order they appear in the truth table:

Apply the function input variables to themultiplexer inputs Sn 1, , S0

Label the outputs of the multiplexer with the

output variables Value-fix the information inputs to the multiplexer using

the values from the truth table (for dont cares, applyeither 0 or 1)

Dr. I. Damaj 34

Example: Gray to Binary Code

Design a circuit to

convert a 3-bit Gray

code to a binary code

The formulation givesthe truth table on the

right

It is obvious from this

table that X = C and the

Y and Z are more complex

Gray

A B C

Binary

x y z

0 0 0 0 0 0

1 0 0 0 0 11 1 0 0 1 0

0 1 0 0 1 1

0 1 1 1 0 0

1 1 1 1 0 1

1 0 1 1 1 0

0 0 1 1 1 1


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Dr. I. Damaj 35

Gray to Binary (continued) Rearrange the table so

that the input combinationsare in counting order

Function x is the same as C

Functions y and z canbe implemented usinga dual 8-to-1-linemultiplexer by:

connecting A, B, and C to the multiplexer select inputs

placing y and z on the two multiplexer outputs

connecting their respective truth table values to the inputs

Gray

A B C

Binary

x y z

0 0 0 0 0 0

0 0 1 1 1 1

0 1 0 0 1 1

0 1 1 1 0 0

1 0 0 0 0 1

1 0 1 1 1 0

1 1 0 0 1 01 1 1 1 0 1

Dr. I. Damaj 36

Note that the multiplexer with fixed inputs is identical to a ROM with

3-bit addresses and 2-bit data!

Gray to Binary (continued)

D04D05D06D07

S1S0

A

B

S2

D03

D02

D01

D00

Out

C

D14D15D16D17

S1S0

AB

S2

D13

D12

D11

D10

Out

C

1

1

1

1

11

1

1

0

0

0

0

0

0

0

0

Y Z

8-to-1

MUX

8-to-1MUX


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Dr. I. Damaj 37

Multiplexer Approach 2 Implement any mfunctions ofn+ 1 variables by using:

An m-wide 2n-to-1-line multiplexer

A single inverter

Design:

Find the truth table for the functions.

Based on the values of the first nvariables, separate the truthtable rows into pairs

For each pair and output, define a rudimentary function of the

final variable (0, 1, X, X)

Using the first nvariables as the index, value-fix the informationinputs to the multiplexer with the corresponding rudimentary

functions

Use the inverter to generate the rudimentary function X

Dr. I. Damaj 38

Example: Gray to Binary Code

Design a circuit to

convert a 3-bit Gray

code to a binary code

The formulation givesthe truth table on the

right

It is obvious from this

table that X = C and the

Y and Z are more complex

Gray

A B C

Binary

x y z

0 0 0 0 0 0

1 0 0 0 0 11 1 0 0 1 0

0 1 0 0 1 1

0 1 1 1 0 0

1 1 1 1 0 1

1 0 1 1 1 0

0 0 1 1 1 1


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Dr. I. Damaj 39


Rearrange the table so that the input combinations are in counting

order, pair rows, and find rudimentary functions

1 0 11 1 1

0 1 01 1 0

1 1 01 0 1

0 0 11 0 0

1 0 00 1 1

0 1 10 1 0

1 1 10 0 1

0 0 00 0 0

Rudimentary

Functions of C

for z

Rudimentary

Functions of C

for y

Binary

x y z

Gray

A B C

F = C

F = C

F = C

F = C

F = C

F = CF = C

F = C

Dr. I. Damaj 40

Assign the variables and functions to the multiplexer inputs:

Note that this approach (Approach 2) reduces the cost by almost halfcompared to Approach 1.

This result is no longer ROM-like

Extending, a function of more than nvariables is decomposed into severalsub-functions defined on a subset of the variables. The multiplexer then

selects among these sub-functions.


S1S0

AB

D03

D02

D01

D00

Out Y

8-to-1

MUX

C

C

C

C D13

D12

D11

D10

Out Z

8-to-1

MUXS1S0

AB

C

C

C

CC C


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Dr. I. Damaj 41

Read Only Memory

Functions are implemented by storing the truth table

Other representations such as equations more convenient

Generation of programming information from equations usually

done by software

Text Example 4-10 Issue

Two outputs are generated outside of the ROM In the implementation of the system, these two functions are

hardwired and even if the ROM is reprogrammable or

removable, cannot be corrected or updated

Dr. I. Damaj 42

Using Read-Only Memories


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Dr. I. Damaj 43

Example:

Square of a 3-bit binary input

Text Example 4-10 Issue

Two outputs are generated outside of the ROM

In the implementation of the system, these two functions are hardwiredand even if the ROM is reprogrammable or removable, cannot becorrected or updated

Dr. I. Damaj 44

Programmable Array Logic

There is no sharing of AND gates as in the ROM and PLA

Design requires fitting functions within the limited number of

ANDs per OR gate

Single function optimization is the first step to fitting

Otherwise, if the number of terms in a function is greater than

the number of ANDs per OR gate, then factoring is necessary


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Dr. I. Damaj 45

Productterm

AND Inputs

OutputsA B C D W

1

2

3

W = ABC + ABC

4

5

6

F1 = X = ABC+ABC+W

7

8

9

10

11

12

F2 = Y = AB + BC +AC

1

0

0

1

0

0

1

0

1

0

1

1

1

1

1

1

1

1

1

Equations:

F1 = ABC +ABC +ABC + ABC

F2 = AB + BC + AC

F1 must be

factored

since four

terms

Factor out

last two

terms as W

Programmable Array Logic Example

Dr. I. Damaj 46

Programmable Array Logic ExampleAND gates inputs

A C WProduct

term

1

2

3

4

5

6

7

8

9

10

11

12

A

B

C

D

W

F1

F2

All fuses intact

(always 5 0)

X Fuse intact

A B B C D D W

A C WA B B C D D W

1 Fuse blown


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Dr. I. Damaj 49

Programmable Logic Array

The set of functions to be implemented must fit the available number of

product terms

The number of literals per term is less important in fitting

The best approach to fitting is multiple-output, two-level optimization (which

has not been discussed)

Since output inversion is available, terms can implement either a function or

its complement

For small circuits, K-maps can be used to visualize product term sharing and

use of complements

For larger circuits, software is used to do the optimization including use of

complemented functions

Dr. I. Damaj 50

Programmable Logic Array

1

2

F AB AC ABC

F AC BC

= + +

= +


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Dr. I. Damaj 51

Using Programmable Logic Arrays

1

2

F AB AC ABC

F AC BC

= + +

= +

Homework

Example 4 - 11

Dr. I. Damaj 52

Lookup Tables

Lookup tables are used for implementing logic in Field-Programmable

Gate Arrays (FPGAs) and Complex Logic Devices (CPLDs)

Lookup tables are typically small, often with four inputs, one output, and

16 entries

Since lookup tables store truth tables, it is possible to implement any 4-

input function

Thus, the design problem is how to optimally decompose a set of given

functions into a set of 4-input two- level functions.

We will illustrate this by a manual attempt


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Dr. I. Damaj 53

Lookup Table Example

Equations to be implemented:F1(A,B,C,D,E) = A D E + B D E + C D EF2(A,B,D,E,F) = A E D + B D E + F D E

Extract 4-input function:F3(A,B,D,E) = A D E + B D EF1(C,D,E,F3) = F3 + C D EF2(D,E,F,F3) = F3 + F D E

The cost of the solution is 3 lookup tables

Dr. I. Damaj 54

Introduction to VHDL


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Dr. I. Damaj 55

Overview

Part 1 - Basics and Constructs

VHDL basics Notation

Types & constructs

Signals

Entities and architectures

Libraries and packages

Structural VHDL Example

VHDL Operators

Concurrent VHDL Examples

Part 2 - Behavioral and Hierarchical Description Part 3 - Finite State Machines

Part 4 - Registers and Counters

Part 5 - Algorithmic State Machine Example: Binary Multiplier

Dr. I. Damaj 56

VHDL Notation - 1

VHDL is:

Case insensitive

Based on the programming language ADA

Strongly-typed language

Comments

-- [end of line]

List separator: ,

Statement terminator: ;


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VHDL Notation - 2

Types and values Determined by use of packages (discussed later) that define various types

and type conversions

IEEE 1076 predefined types: type bit has two values 0 and 1

type bit_vector is an array of bits with integers as indices

type integer has values over a specified range of integers

type boolean is (TRUE, FALSE)

IEEE 1164 predefined types: type std_ulogic has nine values: 'U', -- Uninitialized, 'X', --

Forcing Unknown, '0', -- Forcing 0, '1', -- Forcing 1, 'Z', -- High Impedance, 'W', --Weak Unknown, 'L', --Weak 0, 'H', -- Weak1, '-' -- Don't care.

type std_ulogic_vector is an array of bits with natural (non-negative)numbers as the indices

subtype std_logic is std_ulogic with definitions for multiple signalsapplied to a single wire

subtype X01Z is std_logicwith the range X, 0, 1, Z

Dr. I. Damaj 58

VHDL Notation - 3

More on types

Most frequently used type: std_logic

Provides values needed for simulation, notably X and

Z

Frequently used type: integer

Due to strong typing, essential for arithmetic

operations

Requires additional packages to be used to perform

type conversion between std_logic and integer


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VHDL Notation - 4

Constants

Binary

Single bit: '0', '1'

Multiple bit: B"110001", B"11_0001" (underline

permitted for readability)

Other bases

Octal O"61", O"6_1"

Hex X"31", X"3_1"

Decimal 49

Real 49E+1

Dr. I. Damaj 60

VHDL Notation - 5

Identifiers

Examples:A, B1, abc, run, stop, c_in

Keywords

Words reserved for special meanings

Cannot be used as identifiers

Examples: entity, architecture, and, if

Shown here in color

Shown in text in bold


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VHDL Constructs

Structural:

Describes interconnections of components (entities)

Analogous to logic diagrams or netlists

Concurrent VHDL or Dataflow:

Consists of a collection of statements and processes that

execute concurrently

Sequential VHDL: Consists of the sequences of statements within processes

Logic described may be combinational or sequential

Dr. I. Damaj 62

Signal Declaration

Signals can be viewed as "wires"

Signals are concurrent and sequential objects

A port declaration is a signal declaration with in orout added

Examples:

signal a, b: std_logic;

signal widget: std_logic_vector(0 to 7);

-- 0 is MSB and 7 is LSB

signal c: std_logic_vector(2 downto 0);

-- 2 is MSB and 0 is LSB

port (DATA: in std_logic_vector(15 downto 0));

port (NA: out std_logic);


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entity

The primary hardware abstraction in VHDL

Provides: the entity name, the inputs and outputs

Analogous to a symbol in a block diagram

architecture

Specifies the relationships between the inputs and outputs of adesign entity

May be a mixture of structural, concurrent and sequential VHDL.

A given entity may have multiple, different architectures.

Examples of entities and architectures follow.

Entities and Architectures

Dr. I. Damaj 64

Libraries and Packages

A library typically contains VHDL code or compiled VHDL code

A package consists of compiled VHDL code for multiple entities and associatedarchitectures

A package is stored in a library

Example: package func_prims is stored in library lcdf_vhdl

func_prims provides compiled code for the following delay-free gates: and2, ,and5, or2, or5, nand2, , nand5, nor2, , nor5, not, xor2, and xnor2 inwhich integers 2 through 5 specify the number of gate inputs.

Generation of the lcdf_vhdl library and the func_prims package: Generate a new library named lcdf_vhdl. Using the lcdf_vhdl library as the "work" library, compile the file

func_prims.vhd (available from the VHDL web page) that contains thecomponent, entity and architecture descriptions for the package.


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First Example to Illustrate Entities,

Architectures and Constructs

IC7283 - a 1-bit adder from a commercial IC

B0

A0

C0

C1

S0

Dr. I. Damaj 66

A Structural VHDL Example

Instantiation of two packages from two libraries.Applies only to the following entity.

Declaration of entity IC7283

Declaration of 3 inputs and 2 outputs of typestd_logic.

End of entity declaration

Declaration of architecture named structure forentity IC7283

Declarations of the gate components to be usedfrompackage func_prims in library lcdf_vhdl

library IEEE, lcdf_vhdl;

use IEEE.std_logic_1164.all,

lcdf_vhdl.func_prims.all;

entity IC7283 is

port (A0,B0,C0: in std_logic;

C1,S0: out std_logic);

end IC7283;

architecture structure of

IC7283 is

component NOT1

port(in1: in std_logic;

out1: out std_logic)

end component;

component NAND2

port(in1,in2: in std_logic;

out1: out std_logic);

end component;


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A Structural VHDL Example (continued)

component NOR2



end component;

componentAND2



end component;

component XOR2

port(in1,in2: in std_logic;out1: out std_logic);

end component;

signal N1,N2,N3,N4,N5,N6,N7:

std_logic;

Declarations of 7 signals for use ininterconnecting the gates

Dr. I. Damaj 68

A Structural VHDL Example (continued)

begin

g0: NOT1 port map (C0,N3);

g1: NOT1 port map (N2,N5);

g2: NOT1 port map (N3,N6);

g3: NAND2 port map (A0,B0,N1);

g4: NOR2 port map (A0,B0,N2);

g5: NOR2 port map (N2,N4,C1);

g6: AND2 port map (N1,N3,N4);

g7: AND2 port map (N1,N5,N7);

g8: XOR2 port map (N6,N7,S0);

end structure;

Beginning of the body of the architecture.

There is an entry for each gate:gate_identifier:

gate_name keywords port map signal list:

(input, output) or (input1, input2, output)

End of architecture and description


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VHDL Operators

Logical: and, or, nand, nor, xor, xnor, not

Relational: =, /=, =

Shift: sll, srl, sla, sra, rol, ror

Form is sdt - s is for shift, d is direction (d = l is for left, d = r is for right,and t is type (t = l is for logical, and t = r is for rotate).

Adding +, -, &

& is concatenationwhich permits one-dimensional operands to be placeend-to-end to form a combined operand.

Example: ForC_in andA(3:0), C_in & A is equivalent to a 5-bit registerwith C_in as the MSB andA(0) as the LSB.

Sign +, -

Multiplying: * (multiply), /(divide), mod (modulus), rem (remainder)

Miscellaneous: abs (absolute value), ** (exponentiation)

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Concurrent VHDL

Signal assignment

Uses signal assignment operator


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Concurrent VHDL Example Using "with select"

with Z select

CS


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library IEEE

use IEEE.std_logic_1164.all;

entity priority_encoder_we is

port (D: in std_logic_vector (4 downto 0);

A: out std_logic_vector (2 downto 0);

V: out std_logic);

end priority_encoder_we;

architecture dataflow_3 ofpriority_encoder_we is

begin

A


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Problems

4.10, 4.11, 4.12, 4.21, 4.23, 4.24, 4.25, 4.27,

4.30, 4.31, 4.32, 4.33, 4.34, 4.35.

Documents

Ch4 Com Bi National Functions and Circuits