CH5

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Basic Computer Organization & Design

BASIC COMPUTER ORGANIZATION AND DESIGN

• Instruction Codes

• Computer Registers

• Computer Instructions

• Timing and Control

• Instruction Cycle

• Memory Reference Instructions

• Input-Output and Interrupt

• Complete Computer Description

• Design of Basic Computer

• Design of Accumulator Logic

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INSTRUCTION CODES

• Program:A set of instructions that specify the operations, operands, and the sequence by which processing has to occur

• Instruction Code:A group of bits that tells the computer to perform a specific operation

Instruction codes

• Instruction Code Format:

- Operation code: • A group of bits that define the operation (add, subtract, shift)• The operation (or macrooperation) specifies a set of microoperations

- Operand (or address of operand)• Data stored in registers or in the memory, on which the operation is to be performed

Opcode Operand (or Address)

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STORED PROGRAM ORGANIZATIONInstruction codes

Instruction Format

Opcode Address15 12 11 0

Binary Operand

15 0 Operands (data)

Memory 4096 x 16

Instructions (program)

Processor register (Accumulator or AC)

15 0

4 bits 12 bits

24 = 16 operations 212 = 4096 words

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ADDRESSING MODESInstruction codes

Opcode Operand (or Address)

Instruction Format

• Direct Address Mode

Second part of instruction specifies the address of an operand

• Indirect Address Mode

Second part of instruction specifies an address of a memory word in which the address of the operand is found

• Immediate Mode

Second part of instruction specifies an operand

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INDIRECT ADDRESS

Effective Address(EFA, EA)The address of the operand in a computation-type instruction, or the target address in a branch-type instruction

Instruction codes

0 ADD 45722

Operand457

+AC

Direct Address1 ADD 30035

1350300

Operand1350

+AC

Indirect address

Effective Address

Opcode Address

Instruction Format15 14 12 0I

11 I = 0 Direct addressI = 1 Indirect address

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INSTRUCTION FORMAT - Example

Problem 5-1: A computer uses a memory unit with 256K words of 32 bits each. A binary instruction code is stored in one word of memory. The instruction has four parts: an indirect bit, an operation code, a register code part to specify one of 64 registers, and an address part.

a.How many bits are there in the operation code, the register code part, and the address part?

b.Draw the instruction word format and indicate the number of bits in each part?

c.How many bits are there in the data and address inputs of the memory?

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COMPUTER REGISTERSRegisters

Registers in the Basic Computer (BC)11 0

PC

15 0IR

15 0TR

7 0OUTR

15 0DR

15 0AC

11 0AR

INPR0 7

Memory

4096 x 16

List of BC RegistersSymbol # of bits Name Function

DR 16 Data Register Holds memory operandAR 12 Address Register Holds address for memoryAC 16 Accumulator Processor registerIR 16 Instruction Register Holds instruction codePC 12 Program Counter Holds address of instructionTR 16 Temporary Register Holds temporary dataINPR 8 Input Register Holds input characterOUTR 8 Output Register Holds output character

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COMMON BUS SYSTEMRegisters

S2S1S0

Bus

Memory unit4096 x 16

LD INR CLR

AddressReadWrite

AR

LD INR CLR

PC

LD INR CLR

DR

LD INR CLR

ACAdderandlogic

E

INPR

IRLD

LD INR CLR

TR

OUTRLD

Clock

16-bit common bus

7

1

2

3

4

5

6

S2 S1 S0selectedregister

0 0 0 none0 0 1 AR0 1 0 PC0 1 1 DR1 0 0 AC1 0 1 IR1 1 0 TR1 1 1 Memory

Bus Selection

AC extended bit flip-flop for carry-out and circulation

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COMMON BUS SYSTEM - Example

Problem 5-4: The following register transfers are to be executed in the basic computer (Figure 5-4). For each transfer, specify: (1)the binary value that must be applied to bus select inputs S2 , S1 and S0 ;(2)the register whose LD control input must be active (if any); (3)a memory read or write operation (if needed); and(4)the operation in the adder and logic circuit (if any).

a.AR ←

PC

b.IR ←

M[AR]

c.M[AR] ←

TR

d.AC ←

DR, DR ←

AC

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COMPUTER INSTRUCTIONSInstructions

Basic Computer Instruction Code Format

15 14 12 11 0I Opcode Address

Memory-Reference Instructions (Opcode = 000 ~ 110)

Register-Reference Instructions (Opcode = 111, I = 0)15 12 11 0

Register operation0 1 1 1

Input-Output Instructions (Opcode =111, I = 1)15 12 11 0

I/O operation1 1 1 1

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BASIC COMPUTER INSTRUCTIONSInstructions

Hex CodeSymbol I = 0 I = 1 DescriptionAND 0xxx 8xxx AND memory word to ACADD 1xxx 9xxx Add memory word to ACLDA 2xxx Axxx Load AC from memorySTA 3xxx Bxxx Store content of AC into memoryBUN 4xxx Cxxx Branch unconditionallyBSA 5xxx Dxxx Branch and save return addressISZ 6xxx Exxx Increment and skip if zero

CLA 7800 Clear ACCLE 7400 Clear ECMA 7200 Complement ACCME 7100 Complement ECIR 7080 Circulate right AC and ECIL 7040 Circulate left AC and EINC 7020 Increment ACSPA 7010 Skip next instruction if AC is positiveSNA 7008 Skip next instruction if AC is negativeSZA 7004 Skip next instruction if AC is zeroSZE 7002 Skip next instr. if E is zeroHLT 7001 Halt computer

INP F800 Input character to ACOUT F400 Output character from ACSKI F200 Skip on input flagSKO F100 Skip on output flagION F080 Interrupt onIOF F040 Interrupt off

15 12 11 0Register operation0 1 1 1

15 12 11 01 1 1 1 I/O operation

Memory-Reference Instructions

Register-Reference Instructions

Input-Output Instructions

15 14 12 11 0Opcode AddressI

000 - 110

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INSTRUCTION SET COMPLETENESS

Instruction Types

A computer should have a set of instructions so that the user can construct machine language programs to evaluate any function that is known to be computable.

Functional Instructions- Arithmetic, logic, and shift instructions- ADD, CMA, INC, CIR, CIL, AND, CLA

Transfer Instructions- Data transfers between the main memory

and the processor registers- LDA, STA

Control Instructions- Program sequencing and control- BUN, BSA, ISZ

Input/Output Instructions- Input and output- INP, OUT

Instructions

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TIMING AND CONTROLControl unit of basic computer

Control unit implementation- Hardwired Implementation- Micro programmed Implementation

Instruction register (IR)15 14 13 12 11 - 0

3 x 8decoder

7 6 5 4 3 2 1 0

Controllogicgates

ID0

15 14 . . . . 2 1 04 x 16

decoder

4-bitsequence

counter(SC)

Increment (INR)Clear (CLR)Clock

Other inputs

Controloutputs

D

T

T

7

15

0

Timing and control

..

..

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TIMING SIGNALS- Generated by 4-bit sequence counter and 4x16 decoder- The SC can be incremented or cleared.-Example: T0 , T1 , T2 , T3 , T4 , T0 , T1 , . . .

Assume: At time T4 , SC is cleared to 0 if decoder output D3 is active.D3 T4 : SC ← 0

Timing and control

ClockT0 T1 T2 T3 T4 T0

T0

T1

T2

T3

T4

D3

CLR SC

0 1 2 3 4 0 1COUNT

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TIMING SIGNALS

- Example: T0 : AR ← PC

Timing and control

AR

PC 2

T0

S2S1S0

Bus

Clock

1

Common bus

LD

010

ClockT0 T1

T0

T1

0 1 2COUNT

Transfer occurs here

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INSTRUCTION CYCLE

Phases of Instruction cycle

Instruction Cycle

- Fetch Instruction from memory

- Decode the instruction- Read effective address from memory if the instruction has indirect address

- Execute the instruction

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IR

LD

Memoryunit

AddressRead

INR

T1

AR

PC 2

T0

INSTRUCTION CYCLEBC Instruction cycle: [Fetch Decode [Indirect] Execute]

S2

S1

S0

Bus

Clock

1

5

Common bus

7

LD

Instruction Cycle

Fetch T0 : AR ← PCT1 : IR ← M[AR], PC ← PC + 1

T2 : D0, . . . , D7 ← Decode IR(12-14), AR ← IR(0-11), I ← IR(15)

Control Signals:– When T0 =1:

» S2S1S0 = 010» AR(LD) = 1

– When T1 = 1:» S2S1S0 = 111» Read = 1» IR(LD) = 1» PC(INC) = 1

– When T2 = 1:» S2S1S0 = 101» AR(LD) = 1

AR

PC 2

T0

T1

Decode

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DETERMINE THE TYPE OF INSTRUCTION

D7' I T3: AR ← M[AR]D7' I' T3: NothingD7 I' T3: Execute a register-reference instructionD7 I T3: Execute an input-output instruction

Instruction Cycle

StartSC ← 0

AR ← PCT0

IR ← M[AR], PC ← PC + 1T1

AR ← IR(0-11), I ← IR(15)Decode Opcode in IR(12-14),

T2

D7= 0 (Memory-reference)(Register or I/O) = 1

I

Executeregister-reference

instructionSC ← 0

Executeinput-outputinstructionSC ← 0

= 0 (register)(I/O) = 1

T3 T3

= 0 (direct)I

M[AR]←AR Nothing

(indirect) = 1

T3 T3

Executememory-reference

instructionSC ← 0

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REGISTER REFERENCE INSTRUCTIONSInstruction Cycle

r = D7 I’ T3 Bi = IR(i) , i=0,1,2,...,11r: SC ← 0 Clear SC

CLA rB11 : AC ← 0 Clear ACCLE rB10 : E ← 0 Clear ECMA rB9 : AC ← AC’ Complement ACCME rB8 : E ← E’ Complement ECIR rB7 : AC ← shr AC, AC(15) ← E, E ← AC(0) Circulate rightCIL rB6 : AC ← shl AC, AC(0) ← E, E ← AC(15) Circulate leftINC rB5 : AC ← AC + 1 Increment ACSPA rB4 : if (AC(15) = 0) then (PC ← PC+1) Skip if AC positiveSNA rB3 : if (AC(15) = 1) then (PC ← PC+1) Skip if AC negativeSZA rB2 : if (AC = 0) then (PC ← PC+1) Skip if AC zeroSZE rB1 : if (E = 0) then (PC ← PC+1) Skip if E zeroHLT rB0 : S ← 0 (S is a start-stop flip-flop) Halt computer

I Opcode Register OperationSymbol HEX B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0CLA 7800 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0CLE 7400 0 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0CMA 7200 0 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0

: : : : : :SZA 7004 0 1 1 1 0 0 0 0 0 0 0 0 0 1 0 0SZE 7002 0 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0HLT 7001 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1

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REGISTER REFERENCE INSTRUCTIONS - Example

Problem 5-9: The content of AC in the basic computer is hexadecimal A937 and the initial value of E is 1. Determine the contents of AC, E, PC, AR and IR in hexadecimal after the execution of the CLA instruction. The initial value of PC is hexadecimal 021.

CLA instruction cycle:

T0 : AR ← PC

T1 : IR ← M [AR], PC ← PC + 1

T2 : D0,…,D7 ← Decode IR(12-14), AR ← IR(0-11), I ← IR(15)

D7 I'T3 B11 : AC ← 0, SC ← 0

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MEMORY REFERENCE INSTRUCTIONS

- The effective address of the instruction is in AR and was placed there during timing signal T2 when I = 0, or during timing signal T3 when I = 1

- Memory cycle is assumed to be short enough to complete in a clock cycle

- The execution of memory reference Instruction starts with T4

MR Instructions

Symbol OperationDecoder Symbolic Description

AND D0 AC ←

AC ∧

M[AR]ADD D1 AC ←

AC + M[AR], E ← Cout

LDA D2 AC ←

M[AR]STA D3 M[AR] ←

AC

BUN D4 PC ←

ARBSA D5 M[AR] ←

PC, PC ← AR + 1

ISZ D6 M[AR] ←

M[AR] + 1, if M[AR] + 1 = 0 then PC ← PC+1

T0 : AR ← PCT1 : IR ← M [AR], PC ← PC + 1T2 : D0, . . . , D7 ← Decode IR(12-14), AR ← IR(0-11), I ← IR(15)

D'7 IT3 : AR ← M[AR]D'7 I'T3: Nothing

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AND to ACD0 T4 : DR ← M[AR] Read operandD0 T5 : AC ← AC ∧

DR, SC ← 0 AND with AC

ADD to ACD1 T4 : DR ← M[AR] Read operandD1 T5 : AC ← AC + DR, E ← Cout , SC ← 0 Add to AC and store carry in E

LDA: Load to ACD2 T4 : DR ← M[AR]D2 T5 : AC ← DR, SC ← 0

STA: Store ACD3 T4 : M[AR] ← AC, SC ← 0

MR Instructions

AND AC ←

AC ∧

M[AR]ADD AC ←

AC + M[AR], E ← Cout

STA M[AR] ←

ACLDA AC ←

M[AR]

Symbol Symbolic Description

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Memory, PC after execution

0 BUN 135

Next instruction

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PC = 135

Memory

PC ← 135

MR Instructions

BUN: Branch UnconditionallyD4 T4 : PC ← AR, SC ← 0

0 BUN 135Next Instruction

20PC = 21

AR = 135

Memory, PC, AR at time T4

Memory

Instruction

Next instruction in program sequence

Program jumps to instruction out of sequence

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0 BSA 135Next instruction

Subroutine

20PC = 21

AR = 135

136

1 BUN 135

Memory, PC, AR at time T4

Memory

Memory, PC after execution

21

0 BSA 135Next instruction

Subroutine

2021

135

PC = 136

1 BUN 135

Memory

BSA: Branch and Save Return AddressM[AR] ← PC, PC ← AR + 1

BSA: D5 T4 : M[AR] ← PC, AR ← AR + 1D5 T5 : PC ← AR, SC ← 0

M[135] ← 21, PC ← 135 + 1 = 136

MR Instructions

Subroutine call

Subroutine return

Return address

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MEMORY REFERENCE INSTRUCTIONSMR Instructions

ISZ: Increment and Skip if ZeroM[AR] ←

M[AR] + 1, if (M[AR] + 1 = 0) then (PC ← PC + 1)

ISZ:D6 T4 : DR ← M[AR]D6 T5 : DR ← DR + 1D6 T6 : M[AR] ← DR, if (DR = 0) then (PC ← PC + 1), SC ← 0

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FLOWCHART FOR MEMORY REFERENCE INSTRUCTIONSMR Instructions

Memory-reference instruction

DR ← M[AR] DR ← M[AR] DR ← M[AR] M[AR] ← ACSC ← 0

AND ADD LDA STA

AC ← AC DRSC ← 0

AC ← AC + DRE ← CoutSC ← 0

AC ← DRSC ← 0

D T0 4 D T1 4 D T2 4 D T3 4

D T0 5 D T1 5 D T2 5

PC ← ARSC ← 0

M[AR] ← PCAR ← AR + 1

DR ← M[AR]

BUN BSA ISZ

D T4 4 D T5 4 D T6 4

DR ← DR + 1

D T5 5 D T6 5

PC ← ARSC ← 0

M[AR] ← DRIf (DR = 0)then (PC ← PC + 1)SC ← 0

D T6 6

∧

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MEMORY REFERENCE INSTRUCTIONS - Example

Problem 5-11: Show the contents in hexadecimal of registers PC, AR, DR, IR, and SC of the basic computer when an ISZ indirect instruction is fetched from memory and executed. The initial content of PC is 7FF. The content of memory at address 7FF is EA9F. The content of memory at address A9F is 0C35. The content of memory at address C35 is FFFF. Give the answer in a table with five columns, one for each register and a row for each timing signal.

ISZ instruction cycle:

T0 : AR ← PCT1 : IR ← M [AR], PC ← PC + 1T2 : D0,…,D7 ← Decode IR(12-14), AR ← IR(0-11), I ← IR(15)

if (indirect) D'7 IT3 : AR ← M[AR]if (direct) D'7 I'T3 : Nothing

D6 T4 : DR ← M[AR]D6 T5 : DR ← DR + 1D6 T6 : M[AR] ← DR, if (DR = 0) then (PC ← PC + 1), SC ← 0

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MEMORY REFERENCE INSTRUCTIONS - Example

Problem 5-13: In the Basic Computer, we want to change some memory reference instructions. Give the sequence of register transfer statements needed to execute the following new instruction starting from timing T4 . EA is the effective address that resides in AR during timing T4 .

Symbol Opcode Symbolic description Description in words

XOR 000 AC ←

AC ⊕

M[EA] Exclusive-OR to AC

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INPUT-OUTPUT AND INTERRUPT

- FGO cleared to 0 by computer when information transferred from AC into OUTR

I/O and Interrupt

Input-Output Configuration

INPR Input register - 8 bitsOUTR Output register - 8 bitsFGI Input flag FF - 1 bitFGO Output flag FF - 1 bit

Input - outputterminal

Serialcommunication

interface

Computerregisters and

flip-flops

Printer

Keyboard

Receiverinterface

Transmitterinterface

FGOOUTR

AC

INPR FGI

Serial Communications PathParallel Communications Path

- FGI set to 1 by input device when information transmitted to INPR

- FGI cleared to 0 by computer when information transferred from INPR into AC

- FGO set to 1 by output device when information received from OUTR

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PROGRAMMED CONTROL DATA TRANSFER

-- CPU --

/* Initially FGI = 0 */ (i.e.; INPR empty)

loop: If FGI = 0 goto loop (i.e.; no data)

AC ← INPR, FGI ← 0

I/O and Interrupt

Start

FGI ← 0

FGI=0

AC ← INPR

MoreCharacter

END

yes

no

yes

no

Input Data Transfer

loop: If FGI = 1 goto loop (i.e.; not read)

INPR ← new data, FGI ← 1

-- I/O Device --

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PROGRAMMED CONTROL DATA TRANSFER

-- CPU --

/* Initially FGO = 1 */ (i.e.; OUTR empty)

loop: If FGO = 0 goto loop (i.e.; not read)

OUTR ← AC, FGO ← 0

I/O and Interrupt

Output Data Transfer

loop: If FGO = 1 goto loop (i.e.; no data)

consume OUTR, FGO ← 1

-- I/O Device --

Start

FGO ← 0

FGO=0

MoreCharacter

END

OUTR ← AC

AC ← Data

yes

no

yes

no

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INPUT-OUTPUT INSTRUCTIONS

D7 IT3 = p

IR(i) = Bi , i = 6, …, 11

p: SC ← 0 Clear SCINP pB11 : AC(0-7) ← INPR, FGI ← 0 Input char. to ACOUT pB10 : OUTR ← AC(0-7), FGO ← 0 Output char. from ACSKI pB9 : if (FGI = 1) then (PC ← PC + 1) Skip on input flagSKO pB8 : if (FGO = 1) then (PC ← PC + 1) Skip on output flagION pB7 : IEN ← 1 Interrupt enable onIOF pB6 : IEN ← 0 Interrupt enable off

I/O and Interrupt

Symbol HEX_INP F800OUT F400SKI F200SKO F100ION F080IOF F040

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PROGRAM-CONTROLLED INPUT/OUTPUT

• Program-controlled I/O- Continuous CPU involvement

I/O takes valuable CPU time- CPU slowed down to I/O speed- Simple- Least hardware

I/O and Interrupt

Input

LOOP, SKI /Check input flag BUN LOOP /FGI=0, branch to check againINP /FGI=1, input character

OutputLOOP, SKO /Check output flag

BUN LOOP /FGO=0, branch to check againOUT /FGO=1, output character

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INTERRUPT INITIATED INPUT/OUTPUT

- Open communication only when some data has to be passed interrupt

* IEN (Interrupt-enable flip-flop)

- can be set and cleared by instructions- when cleared, the computer cannot be interrupted

I/O and Interrupt

- The I/O interface, instead of the CPU, monitors the I/O device

- When the interface finds that the I/O device is ready for data transfer, it generates an interrupt request to the CPU

- Upon detecting an interrupt, the CPU stops momentarily the task it is doing, branches to the service routine to process the datatransfer, and then returns to the task it was performing

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FLOWCHART FOR INTERRUPT CYCLEI/O and Interrupt

Executeinstruction

FGI=0

FGO=0

=1

=1

R ← 1

Fetch and decodeinstruction

R = Interrupt FF

R =1=0 Interrupt cycleInstruction cycle

Store return addressin location 0M[0] ← PC

Branch to location 1PC ← 1

IEN ← 0R ← 0

IEN=1

=0

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DEMONESTRATION OF INTERRUPT CYCLE

0 BUN 112001

PC = 256255

1 BUN 0

Before interrupt

MainProgram

1120I/O

Program

Memory

After interrupt cycle

0 BUN 11200

PC = 1

256255

1 BUN 0

MainProgram

1120I/O

Program

256

I/O and Interrupt

SKIBUN NEXTINP

NEXT, SKOBUN EXITOUT

EXIT, ION



IEN ← 0R ← 0

Interrupt cycle

Problem 5-18: An output program resides in memory starting from address 2300. a. What instruction must be placed at address 1?b. What must be the last two instructions of the output program?

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REGISTER TRANSFER OPERATIONS IN INTERRUPT CYCLEI/O and Interrupt



IEN ← 0R ← 0

Interrupt cycle

=0IEN

FGI

FGO

R ← 1

=1

=1

=1

=0

=0

R =1=0Instruction cycle

Fetch and decodeinstruction

Executeinstruction

T0 ’T1 ’T2 ’ (IEN)(FGI + FGO): R ← 1

RT0 : AR ← 0, TR ← PC

RT1 : M[AR] ← TR, PC ← 0

RT2 : PC ← PC + 1, IEN ← 0, R ← 0, SC ← 0

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COMPLETE COMPUTER DESCRIPTION Flowchart of Operations

Description

=1 (I/O) =0 (register) =1 (indirect) =0 (direct)

startSC ← 0, IEN ← 0, R ← 0

R

AR ← PCR’T0

IR ← M[AR], PC ← PC + 1R’T1

AR ← IR(0~11), I ← IR(15)D0 ...D7 ← Decode IR(12 ~ 14)

R’T2

AR ← 0, TR ← PCRT0

M[AR] ← TR, PC ← 0RT1

PC ← PC + 1, IEN ← 0R ← 0, SC ← 0

RT2

D7

I I

ExecuteI/O

Instruction

Executereg-ref

Instruction

AR ← M[AR] NothingD7 IT3 D7 I’T3 D7 ’IT3 D7 ’I’T3

Execute mem-refInstruction

=0 (instruction cycle) =1 (interrupt cycle)

=1 (Register or I/O) =0 (Memory Ref)

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COMPLETE COMPUTER DESCRIPTION Microoperations

Description

Fetch

Decode

Indirect

Interrupt

Memory-ReferenceAND

ADD

LDA

STABUNBSA

ISZ

R’T0 : R’T1 :R’T2 :

D7 ’IT3 :

RT0 :RT1 :RT2 :

D0 T4 :D0 T5 :D1 T4 :D1 T5 :D2 T4 :D2 T5 :D3 T4 :D4 T4 :D5 T4 :D5 T5 :D6 T4 :D6 T5 :D6 T6 :

AR ← PCIR ← M[AR], PC ← PC + 1D0 , ..., D7 ← Decode IR(12 ~ 14), AR ← IR(0 ~ 11), I ← IR(15)AR ← M[AR]

R ← 1AR ← 0, TR ← PCM[AR] ← TR, PC ← 0PC ← PC + 1, IEN ← 0, R ← 0, SC ← 0

DR ← M[AR]AC ← AC ∧

DR, SC ← 0DR ← M[AR]AC ← AC + DR, E ← Cout, SC ← 0DR ← M[AR]AC ← DR, SC ← 0M[AR] ← AC, SC ← 0PC ← AR, SC ← 0M[AR] ← PC, AR ← AR + 1PC ← AR, SC ← 0DR ← M[AR]DR ← DR + 1M[AR] ← DR, if(DR=0) then (PC ← PC + 1), SC ← 0

T0 ’T1 ’T2 ’(IEN)(FGI + FGO):

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Register-Reference

CLACLECMACMECIRCILINCSPASNASZASZEHLT

Input-Output

INPOUTSKISKOIONIOF

D7 I’T3 = rIR(i) = Bi

r:rB11 :rB10 :rB9 :rB8 :rB7 :rB6 :rB5 :rB4 :rB3 :rB2 :rB1 :rB0 :

D7 IT3 = p IR(i) = Bi

p:pB11 :pB10 :pB9 :pB8 :pB7 :pB6 :

(Common to all register-reference instr)(i = 0,1,2, ..., 11)SC ← 0AC ← 0E ← 0AC ← AC’E ← E’AC ← shr AC, AC(15) ← E, E ← AC(0)AC ← shl AC, AC(0) ← E, E ← AC(15)AC ← AC + 1If(AC(15) =0) then (PC ← PC + 1)If(AC(15) =1) then (PC ← PC + 1)If(AC = 0) then (PC ← PC + 1)If(E=0) then (PC ← PC + 1)S ← 0

(Common to all input-output instructions)(i = 6,7,8,9,10,11)SC ← 0AC(0-7) ← INPR, FGI ← 0OUTR ← AC(0-7), FGO ← 0If(FGI=1) then (PC ← PC + 1)If(FGO=1) then (PC ← PC + 1)IEN ← 1IEN ← 0

Description

COMPLETE COMPUTER DESCRIPTION Microoperations

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DESIGN OF BASIC COMPUTER (BC)Hardware Components of BC

Memory unit: 4096 x 16Registers: AR, PC, DR, AC, IR, TR, OUTR, INPR, and SCFlip-Flops: I, S, E, R, IEN, FGI, and FGODecoders: 3x8 Opcode decoder, 4x16 timing decoderCommon bus: 16 bitsControl logic gatesAdder and Logic circuit connected to AC

The outputs of the Control Logic Gates are:- Signals to control the inputs of the nine registers such as LD and INC- Signals to control the read and write inputs of memory- Signals to set, clear, or complement the flip-flops- Signals for S2 , S1 , S0 to select a source register for the bus- Signals to control the AC Adder and Logic circuit

Design of Basic Computer

42


CONTROL OF REGISTERS AND MEMORY

Scan all of the register transfer statements that change the content of AR:Address Register; AR

LD(AR) = R'T0 + R'T2 + D'7 IT3CLR(AR) = RT0INR(AR) = D5 T4

R’T0 : AR ← PC LD(AR)R’T2 : AR ← IR(0-11) LD(AR)D’7 IT3 : AR ← M[AR] LD(AR)RT0 : AR ← 0 CLR(AR)D5 T4 : AR ← AR + 1 INR(AR)


AR

LDINR

CLR

Clock

To bus12From bus 12

D'I

TT

RTD5T

7

32

0

4

R’T0 : R’T1 :R’T2 :

D7 ’IT3 :

RT0 :RT1 :RT2 :



AR ← 0, TR ← PCM[AR] ← TR, PC ← 0PC ← PC + 1, IEN ← 0, R ← 0, SC ← 0



Problem 5-21:Derive the control gates associated with PC.

43


CONTROL OF REGISTERS AND MEMORY

Scan all of the register transfer statements that specify a read operation:Memory (Read Input)

Read = R′T1 + D7 ′IT3 + (D0 + D1 + D2 + D6 )T4

R′T1 : IR ← M[AR]D7 ′IT3 : AR ← M[AR]D0 T4 : DR ← M[AR]D1 T4 : DR ← M[AR]D2 T4 : DR ← M[AR]D6 T4 : DR ← M[AR]


Memory

Read

To bus16From bus

16

D'I

TTR

TD1

7

31

4

D0

D2

D6

R’T0 : R’T1 :R’T2 :

D7 ’IT3 :

RT0 :RT1 :RT2 :



AR ← 0, TR ← PCM[AR] ← TR, PC ← 0PC ← PC + 1, IEN ← 0, R ← 0, SC ← 0



Problem 5-22:Derive the control gates for write input of memory.

44


CONTROL OF FLIP-FLOPS

pB7: IEN ← 1 (I/O Instruction)pB6: IEN ← 0 (I/O Instruction)RT2 : IEN ← 0 (Interrupt)

p = D7 IT3 (Input/Output Instruction)

IEN: Interrupt Enable Flag


D

IT3

7J

K

Q IENpB7

B6

T2R

Problem 5-23:Show the complete logic of interrupt flip-flop R.

45


CONTROL OF COMMON BUS

For AR D4 T4 : PC ← ARD5 T5 : PC ← AR

x1 = D4 T4 + D5 T5


x1x2x3x4x5x6x7

Encoder

S2

S1

S0

Multiplexerbus select

inputs

S2 S1 S0

selectedregister

0 0 0 none0 0 1 AR0 1 0 PC0 1 1 DR1 0 0 AC1 0 1 IR1 1 0 TR1 1 1 Memory

x1 x2 x3 x4 x5 x6 x7

0 0 0 0 0 0 01 0 0 0 0 0 00 1 0 0 0 0 00 0 1 0 0 0 00 0 0 1 0 0 00 0 0 0 1 0 00 0 0 0 0 1 00 0 0 0 0 0 1

Problem 5-24:Derive the Boolean logic expression for x2 .

46


DESIGN OF ACCUMULATOR LOGICDesign of AC Logic

Circuits associated with AC16

16

8

Adder andlogic circuit

16 ACFrom DR

From INPR

Controlgates

LD INR CLR

16

To bus

Clock

All the statements that change the content of AC

D0 T5 : AC ← AC ∧

DR AND with DRD1 T5 : AC ← AC + DR Add with DRD2 T5 : AC ← DR Transfer from DRpB11 : AC(0-7) ← INPR Transfer from INPRrB9 : AC ← AC’ ComplementrB7 : AC ← shr AC, AC(15) ← E Shift rightrB6 : AC ← shl AC, AC(0) ← E Shift leftrB11 : AC ← 0 ClearrB5 : AC ← AC + 1 Increment

ClearIncrement

Load

47


CONTROL OF AC REGISTERDesign of AC Logic

AC

LDINR

CLR

Clock

To bus16From Adderand Logic

16

D0

D1

D2

B11

B9

B7

B6

B5

B11

r

p

T 5

T 5

r = D7 I’T3

p = D7 IT3

D0 T5

D1 T5

D2 T5

pB11

rB9

rB7

rB6

rB5

rB11

D0 T5 : AC ← AC ∧

DRD1 T5 : AC ← AC + DRD2 T5 : AC ← DRpB11 : AC(0-7) ← INPRrB9 : AC ← AC’rB7 : AC ← shr AC, AC(15) ← ErB6 : AC ← shl AC, AC(0) ← ErB11 : AC ← 0rB5 : AC ← AC + 1

48


ADDER AND LOGIC CIRCUITDesign of AC Logic

D0 T5

D1 T5

D2 T5

pB11

rB9

rB7

rB6

FA

C

C

INPR(i)

DR(i)AC(i)

AC(i+1)

AC(i-1)

i

i+1

Fi

Select Output

D0 T5 AC ← AC ∧

DRD1 T5 AC ← AC + DRD2 T5 AC ← DRpB11 AC(0-7) ← INPRrB9 AC ← AC’rB7 AC ← shr ACrB6 AC ← shl AC

S’1 S’0 I0S’1 S0 I1S1 S’0 I2S1 S0 I3

Select Output I0

FI1

I2

I3

S0

S1S’1 S’0

S’1 S0

S1 S’0

S1 S0

4X1 MUX

FI0I1I2I3

4 X 1MUX

S1S0

49


ADDER AND LOGIC CIRCUIT

One stage of Adder and Logic circuit

Design of AC Logic

J

K

QAC(i)

LD

iI

One stage of AC register

D0 T5

D1 T5

D2 T5

pB11

rB9

rB7

rB6

FA

C

C

INPR(i)

DR(i) AC(i)

AC(i+1)

AC(i-1)

i

i+1

Documents

CH5