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Chapter 1: High-efficiency power amplifier design
Grebennikov, A., Thian, M., & Narendra Kumar (2019). Chapter 1: High-efficiency power amplifier design. In A.Grebennikov (Ed.), Radio Frequency and Microwave Power Amplifiers. Volume 2: Efficiency and LinearityEnhancement Techniques IET. https://digital-library.theiet.org/content/books/cs/pbcs071g
Published in:Radio Frequency and Microwave Power Amplifiers. Volume 2: Efficiency and Linearity EnhancementTechniques
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Download date:06. Aug. 2021
7. High-efficiency power amplifier design
Andrei Grebennikov, Mury Thian and Narendra Kumar
High efficiency of the power amplifier can be obtained by using overdriven Class-B,
Class-F, or Class-E operation modes and their subclasses, depending on the technical require-
ments. In all cases, an efficiency improvement in practical implementation is achieved by
providing the nonlinear operation conditions when an active device can simultaneously operate
in pinch-off, active, and saturation regions, resulting in the nonsinusoidal collector current and
voltage waveforms, symmetrical for Class-F and asymmetrical for Class-E operation modes. In
Class-F power amplifiers analyzed in frequency domain, the fundamental-frequency and har-
monic load impedances are optimized by short-circuit termination and open-circuit peaking to
control the voltage and current waveforms at the device output to obtain maximum efficiency.
In Class-E power amplifiers analyzed in time domain, an efficiency improvement is achieved
by realizing the on/off active device switching operation (saturation and pinch-off modes) with
special current and voltage waveforms so that high voltage and high current do not concur at
the same time.
7.1. Class-F circuit design
The possibility to maximize efficiency in a vacuum-tube amplifier was firstly demon-
strated in the late 1910s by a suitable choice of grid voltage with the corresponding anode ar-
rangement to produce an anode current or voltage waveform which is composed principally of
the fundamental frequency and third harmonic and has a “Meander”-like form [1]. It was pro-
posed to use the load network with a third- or higher-harmonic trap in series to the anode in
practical implementation, as shown in Fig. 7.1(a) [2, 3]. However, effect of the inclusion of a
third-harmonic resonator was described and analyzed in detail only 1.5 decades later [4, 5]. It
was shown that the symmetrical anode voltage waveform and level of its depression can be
provided with opposite phase conditions at the waveform midpoints between the fundamental
and third harmonic and optimum value of the ratio between their voltage amplitudes. In addi-
tion, it was noted that high operation efficiency can be achieved even when impedance of the
third-harmonic resonator is equal or slightly greater than that of the fundamental tank. To max-
imize efficiency of the vacuum-tube amplifier with better approximating a square voltage anode
waveform, it was also suggested to use an additional resonator tuned to the fifth harmonic, as
shown in Fig. 7.1(b) [6].
7-2
RL
3f0
f0
a).
b).
RL
3f0
f0
5f0
Fig. 7.1. Biharmonic and polyharmonic Class-F power amplifiers.
2 t
i n = 1, 2
I0
0
2 t
v n = 1, 3
Vcc
0
a).
b). Fig. 7.2. Fourier voltage and current waveforms with third and second harmonics, respectively.
Figure 7.2 shows that the shapes of the voltage and current waveforms can be significantly
changed with increasing fundamental voltage amplitude by adding even one additional har-
monic component being properly phased. For example, the combination of the fundamental-
frequency and third-harmonic components being 180 out-of-phase at center points results in a
flattened voltage waveform with depression in its center. It is clearly seen from Fig. 7.2(a) that
the proper ratio between the amplitudes of the fundamental and third-harmonic components can
provide the flattened voltage waveform with minimum depression and maximum difference
7-3
between its peak amplitude and amplitude of the fundamental component. Similarly, the
combination of the fundamental-frequency and second-harmonic components, being in phase
at the center points, flattens the current waveform corresponding to the maximum values of the
voltage waveform and sharpens the current waveform corresponding to the minimum values of
the voltage waveform, as shown in Fig. 7.2(b). The optimum ratio between the amplitudes of
the current fundamental-frequency and second-harmonic components can maximize a peak
value of the current waveform, with its minimized value determined by the device saturation
resistance in a practical circuit. Thus, power loss due to the active device can be minimized
because the results of the integration over period when the minimum voltage corresponds to the
maximum current will give a small value compared with the power delivered to the load.
7.1.1. Idealized Class-F mode
Generally, an infinite number of the odd-harmonic tank resonators can maintain a square
collector voltage waveform, also providing a half-sinusoidal current waveform. Figure 7.3(a)
shows such a Class-F power amplifier with a multiple-resonator output filter to control the har-
monic content of its collector (anode or drain) voltage and current waveforms, thereby shaping
them to reduce dissipation and to increase efficiency [7].
iR
i I0
v Vcc
a).
b).
RL
3f0
f0
5f0 (2n + 1)f0
RL
3f0
f0
5f0 (2n + 1)f0
ieven
Vcc
vodd
Fig. 7.3. Basic circuits of Class-F power amplifier with parallel resonant circuits.
To simplify an analysis of a Class-F power amplifier, whose simplified equivalent circuit
is shown in Fig. 7.3(b), the following several assumptions are introduced:
Transistor has zero saturation voltage, zero saturation resistance, and infinite off-re-
sistance, and its switching action is instantaneous and lossless.
RF choke allows only a dc current and has no resistance.
Quality factors of all parallel resonant circuits have infinite impedance at the corre-
sponding harmonic and zero impedance at other harmonics.
7-4
There are no losses in the circuit except only into the load RL.
Operation mode with a 50% duty ratio.
To determine the idealized collector voltage and current waveforms, let us consider the
distribution of voltages and currents in the load network, assuming the sinusoidal fundamental
current flowing into the load as iR(t) = IRsin(t), where IR is its amplitude. The voltage v(t)
across the switch can be represented as a sum of the dc voltage Vcc, the fundamental voltage vR
= iRRL across the load resistor, and the voltage vodd across the odd-harmonic resonators,
v(t) = Vcc + vodd[(2n + 1)t] + vR(t). (7.1)
Because the time moment t was chosen arbitrarily, by introducing a phase shift of , Eq.
(7.1) can be rewritten for periodical sinusoidal functions as
v(t + ) = Vcc vodd[(2n + 1)t] vR(t). (7.2)
Then, the summation of Eq. (7.1) and Eq. (7.2) yields
v(t) = 2Vcc v(t + ). (7.3)
From Eq. (7.3), it follows that the maximum value of the collector voltage cannot exceed
a value of 2Vcc and the time duration with a maximum voltage of v = 2Vcc coincides with the
time duration with a minimum voltage of v = 0. Because the collector voltage is zero when the
switch is turned on, the only possible waveform for the collector voltage is a square wave,
composing of only dc, fundamental-frequency, and odd-harmonic components.
During the interval 0 < t when the switch is turned on, the current i(t) flowing
through the switch can be written as
i(t) = I0 + ieven(2nt) + iR(t) (7.4)
whereas during the interval < t 2 when the switch is turned off, the current i(t + ) is
equal to zero, resulting in
0 = I0 + ieven(2nt) iR(t). (7.5)
Then, by substituting Eq. (7.5) into Eq. (7.4), we can rewrite Eq. (7.4) as
i(t) = 2iR(t) = 2IR sin(t) (7.6)
from which it follows that the amplitude of the current flowing through the switch during the
interval 0 < t is two times greater than the amplitude of the fundamental current. Thus, in
a general case of entire interval, Eq. (7.4) can be rewritten as
i(t) = IR (sint + sint) (7.7)
which means that the switch current represents half-sinusoidal pulses with the amplitude equal
to double load current amplitude.
7-5
Consequently, for a purely sinusoidal current flowing into the load, which is shown in
Fig. 7.4(a), the ideal collector voltage and current waveforms can be represented by the appro-
priate normalized waveforms shown in Fig. 7.4(b) and 7.4(c), respectively. Here, a sum of the
fundamental and odd harmonics approximates a square voltage waveform and a sum of the
fundamental and even harmonics approximates a half-sinusoidal collector current waveform.
As a result, the shapes of the collector current and voltage waveforms provide a condition when
the current and voltage do not overlap simultaneously. Such a condition, with symmetrical col-
lector voltage and current waveforms, corresponds to an idealized Class-F operation mode with
100% collector efficiency.
i/I0
3.0
2.0
1.0
0 t, 300 240 180 120 60 0
c).
v/Vcc
1.5
1.0
0.5
0 t, 300 240 180 120 60 0
b).
iR/I0
1.5
1.0
0.5
0 t,
300 240 120 60
a).
-0.5
-1.0
-1.5
180
2.0
Fig. 7.4. Ideal waveforms of Class-F power amplifier.
A Fourier analysis of the current and voltage waveforms allows us to obtain the following
equations for the dc current and the fundamental voltage and current components in the collec-
tor voltage and current waveforms:
The dc current I0 can be calculated from Eq. (7.7) as
R
0
R0
2 sin2
2
1
ItdtII . (7.8)
The fundamental current component can be calculated from Eq. (7.7) as
R
0
2R1 sin2
1 ItdtII
. (7.9)
7-6
The fundamental voltage component can be calculated using Eq. (7.3) as
cc2
ccR1
4 sin2
1
VtdtVVV (7.10)
where VR = IRRL is the fundamental voltage amplitude across the load resistor RL.
Then, the dc power and output power at the fundamental frequency are calculated by
Rcc
0cc0
2
IVIVP (7.11)
Rcc11
1
2
2
IVIVP (7.12)
respectively, resulting in a theoretical collector efficiency with maximum value of
100% 0
1 P
P . (7.13)
In this case, the impedance conditions seen by the device collector for an idealized Class-
F mode must be equal to
0
cc211
8
I
VRZ
(7.14)
Z2n = 0 for even harmonics (7.15)
Z2n+1 = for odd harmonics. (7.16)
7.1.2. Class F with maximally flat waveforms
Although it is impossible to realize the ideal harmonic impedance conditions in practical
implementation, the peaking of at least several current and voltage harmonic components can
be provided to achieve a high operation efficiency of the power amplifier. The more the voltage
waveform provided by higher-order harmonic components can be flattened, the less power dis-
sipation due to flowing of the output current (when the output voltage is extremely small) oc-
curs. To understand the basic design principles and to numerically calculate the power amplifier
efficiency according to the contribution of an appropriate number of the harmonic components
of voltage and current waveforms, it is convenient to use a design technique based on a Class-
F approximation with maximally flat waveforms [8]. In this case, the load network is assumed
ideal to deliver only the fundamental-frequency power to the load without loss. The active de-
vice represents an ideal multiharmonic current source with zero saturation voltage and output
capacitance for providing instant switching between saturation and pinch-off operation regions.
Flattening of the voltage and current waveforms to realize a Class-F operation can be accom-
plished by using odd-harmonic components to approximate a rectangular voltage waveform
and even-harmonic components to approximate a half-sinusoidal current waveform given by
7-7
,...7,5,3
n 1cc sin sin n
tnVtVVtv (7.17)
,...6,4,2
n10 cos sin n
tnItIIti . (7.18)
For the symmetrical flattened voltage waveforms shown in Fig. 7.5, the medium points
where the voltage waveform reaches its maximum and minimum values are at t = /2 and t
= 3/2, respectively. Maximum flatness at minimum voltage requires the even-order derivatives
to be zero at t = 3/2. As the odd-order derivatives are equal to zero because cos(n/2) = 0 for
odd n, it is necessary to define the even-order derivatives of the voltage waveform given by Eq.
(7.17).
v/Vcc
2.0
1.5
1.0
0.5
0 /2 3/2 t
n = 1, 3
v/Vcc
2.0
1.5
1.0
0.5
0 /2 3/2 t
n = 1, 3, 5
a).
b).
v/Vcc
2.0
1.5
1.0
0.5
0 /2 3/2 t
n = 1, 3, 5, 7
c). Fig. 7.5. Voltage waveforms for nth-harmonic peaking
For the third-harmonic peaking when only the third-harmonic component together with
the fundamental one is present, their optimum amplitudes are defined as
7-8
cc1 8
9 VV cc3
8
1 VV . (7.19)
The voltage waveforms for the third-harmonic peaking (n = 1, 3), fifth-harmonic peaking
(n = 1, 3, 5), and seventh-harmonic peaking (n = 1, 3, 5, 7) are shown in Fig. 7.5.
2.5
i/I0
2.0
1.5
1.0
0.5
0 /2 3/2 t
n = 1, 2
a).
b).
2.5
i/I0
2.0
1.5
1.0
0.5
0 /2 3/2 t
n = 1, 2, 4, 6
c).
2.5
i/I0
2.0
1.5
1.0
0.5
0 /2 3/2 t
n = 1, 2, 4
Fig. 7.6. Current waveforms for nth-harmonic peaking.
For the symmetrical current waveforms shown in Fig. 7.6, the medium points where the
current waveform reaches its minimum and maximum values are at t = /2 and t = 3/2,
respectively. As the odd-order derivatives are equal to zero because cos(/2) = 0 and sin(n/2)
= 0 for even n, it is sufficient to determine the even-order derivatives of the current waveform
given by Eq. (7.18). Maximum flatness at minimum current requires the even-order derivatives
to be zero at t = /2.
For the second-harmonic peaking when only the second-harmonic component together
with the fundamental one is present, their optimum amplitudes are defined by
7-9
01 3
4 II 02
3
1 II . (7.20)
The current waveforms for the second-harmonic peaking (n = 1, 2), fourth-harmonic
peaking (n = 1, 2, 4), and sixth-harmonic peaking (n = 1, 2, 4, 6) are shown in Fig. 7.6.
The effectiveness of the operations modes with different voltage and current harmonic
peaking can be compared by calculating the collector (drain) efficiency of each operation
mode according to
0
1
cc
1
0
1 2
1
I
I
V
V
P
P . (7.21)
The resultant efficiencies for various combinations of the voltage and current harmonic
components are given in Table 7.1, which shows that the efficiency increases with an increase
in the number of voltage and current harmonic components. To increase efficiency, it is more
desirable to provide harmonic peaking in consecutive numerical order (both for voltage and
current harmonic components) than to increase the number of the harmonic components into
only voltage or current waveforms. Class-F operation becomes mostly effective in comparison
with Class-B operation if at least third-voltage harmonic peaking and fourth-current harmonic
peaking are realized. An inclusion of fifth-voltage harmonic component increases the efficiency
to 83.3%. An additional inclusion of sixth-current harmonic component into the current wave-
form and a seventh-voltage harmonic component into the voltage waveform leads to efficien-
cies up to 94%.
Table 7.1. Resultant efficiencies for various combinations of voltage and current harmonic components.
Current har-monic compo-
nents
Voltage harmonic components
1 1, 3 1, 3, 5 1, 3, 5, 7 1, 3, 5, …,
1 1/2 =0.500 9/16 = 0.563 75/128 = 0.586 1225/2048 = 0.598 2/ = 0.637
1, 2 2/3 = 0.667 3/4 = 0.750 25/32 = 0.781 1225/1536 = 0.798 8/3 = 0.849
1, 2, 4 32/45 = 0.711 4/5 = 0.800 5/6 = 0.833 245/288 = 0.851 128/45 = 0.905
1, 2, 4, 6 128/175 = 0.731 144/175 = 0.823 6/7 = 0.857 7/8 = 0.875 512/175 = 0.931
1, 2, 4,…, /4 = 0.785 9/32 = 0.884 75/256 = 0.920 1225/4096 = 0.940 1 = 1.000
7.1.3. Class F with quarterwave transmission line
Ideally, a control of an infinite number of the harmonics maintaining a square voltage
waveform and a half-sinusoidal current waveform at the device output can be provided by using
a serious quarterwave transmission line and a parallel-tuned resonant circuit, as shown in Fig.
7-10
7.7. This type of a Class-F power amplifier was initially proposed to be used at higher
frequencies, where implementation of the load networks with only lumped elements is difficult
and the parasitic device output (lead or package) inductor is sufficiently small [9]. In this case,
the quarterwave transmission line transforms the load impedance according to
L
20
R
ZR (7.22)
where Z0 is the characteristic impedance of a transmission line. For even harmonics, the short
circuit on the load side of the transmission line is repeated, thus producing a short circuit at the
drain. However, the short circuit at the load produces an open circuit at the drain for odd har-
monics with resistive load at the fundamental.
Vdd
Z0, /4
vin RL C0 L0
Cb
R
Fig. 7.7. Class-F power amplifier with series quarterwave transmission line.
Generally, at low drive level, the active device acts as a current source (voltage-controlled
in the case of the MOSFETs or MESFETs and current-controlled in the case of bipolar transis-
tors). As input drive increases, the active device enters saturation resulting in a harmonic-gen-
eration process. Because the quarterwave transmission line presents the high impedance condi-
tions to all odd harmonics, all odd harmonics provide a proper contribution to the output voltage
waveform. As a result, at high drive level, the output voltage waveform approximates a square
wave, and the transistor is saturated for a full half-cycle. In this case, the transistor acts as a
switch rather than a saturating current source.
An alternative configuration of the Class-F power amplifier with a shunt transmission line
located in between the dc power supply and the device collector is shown in Fig. 7.8(a). In this
case, there is no need to use an RF choke and a series blocking capacitor because a series fun-
damentally tuned resonant L0C0 circuit is used instead of a parallel fundamentally tuned reso-
nant circuit. However, unlike the case with a series quarterwave transmission line, such a Class-
F load-network configuration with a shunt quarterwave transmission line does not provide an
impedance transformation. Therefore, the load resistance R, which is equal to the equivalent
active device output resistance at the fundamental frequency, must then be transformed to the
7-11
standard load resistance RL. Let us now derive analytically fundamental properties of a
quarterwave transmission line. The transmission line in time domain can be represented as an
element with finite delay time depending on its electrical length. Consider a simplified load
network of the Class-F power amplifier shown in Fig. 7.8(b), which consists of a parallel quar-
terwave transmission line grounded at the end through the dc power supply, a series fundamen-
tally tuned L0C0 circuit, and a load resistance R. In an idealized case, the intrinsic device output
capacitance is assumed to be negligible to affect the power amplifier performance. The loaded
quality factor QL of the series resonant L0C0 circuit is high enough to provide the sinusoidal
output current iR flowing into the load R.
Cb
Vcc
/4
R
C0 L0
i
Vcc
/4
R
C0 L0 iR x
l 0
iT
v
a).
vinc, iinc
vrefl, irefl
b). Fig. 7.8. Class-F power amplifier with shunt quarterwave transmission line.
To define the collector voltage and current waveforms, consider the electrical behavior
of a homogeneous lossless quarterwave transmission line connected to the dc voltage supply
with RF grounding [10, 11]. In this case, the voltage v(t, x) in any cross section of such a trans-
mission line can be represented as a sum of the incident voltage vinc(t 2x/) and the reflected
voltage vrefl(t +2x/), generally with an arbitrary waveform. When x = 0, the voltage v(t, x)
is equal to the collector voltage,
v(t) = v(t, 0) = vinc(t) + vrefl(t). (7.23)
At the same time, at another end of the transmission line when x = /4, the voltage is
constant and equal to
Vcc = v(t, /2) = vinc(t /2) + vrefl(t + /2). (7.24)
7-12
Because the time moment t was chosen arbitrarily, let us rewrite Eq. (7.24) using a
phase shift of /2 for each voltage by
vinc(t) = Vcc vrefl(t + ). (7.25)
Substituting Eq. (7.25) into Eq. (7.23) yields
v(t) = vrefl(t) vrefl(t + ) + Vcc. (7.26)
Consequently, for the phase shift of , the collector voltage can be obtained by
v(t + ) = vrefl (t + ) vrefl (t + 2) + Vcc. (7.27)
For an idealized operation condition with a 50% duty ratio when during half a period the
transistor is turned on and during another half a period the transistor is turned off with overall
period of 2, the voltage vrefl(t) can be considered the periodical function with a period of 2,
vrefl (t) = vrefl (t + 2). (7.28)
As a result, the summation of Eqs. (7.26) and (7.27) results in the basic expression for
collector voltage in the form
v(t) = 2Vcc v(t + ). (7.29)
From Eq. (7.29), which is similar to Eq. (7.3), it follows that the maximum value of the
collector voltage cannot exceed a value of 2Vcc and the time duration with maximum voltage of
v = 2Vcc coincides with the time duration with minimum voltage of v = 0.
Similarly, the equation for the current iT flowing into the quarterwave transmission line
can be obtained by
iT(t) = iT(t + ) (7.30)
which means that the period of a signal flowing into the quarterwave transmission line is equal
to because it contains only even harmonics, because a shorted quarterwave transmission line
has an infinite impedance at odd harmonics at its input.
Let the transistor operate as an ideal switch when it is turned on during the interval 0 <
t ≤ where v = 0 and turned off during the interval < t ≤ 2 where v = 2Vcc, according to
Eq. (7.29). During the interval < t ≤ 2 when the switch is turned off, the load is directly
connected to the transmission line and iT = iR = IR sint. Consequently, during the interval 0
< t ≤ when the switch is turned on, iT = IR sint according to Eq. (7.30). Hence, the current
flowing into the quarterwave transmission line at any t can be represented by
iT(t) = IRsint (7.31)
where IR is the amplitude of current flowing into the load.
Because the collector current is defined as i = iT + iR, then
i(t) = IR (sint + sint) (7.32)
7-13
which means that the collector current represents half-sinusoidal pulses with the amplitude
equal to double load current amplitude.
iT/I0
1.5
1.0
0.5
0 t, 300 240 180 120 60 0
Fig. 7.9. Ideal current waveform in quarterwave transmission line.
Consequently, for a purely sinusoidal current flowing into the load due to the infinite
loaded quality factor of the series fundamentally tuned L0C0 circuit shown in Fig. 7.4(a), the
ideal collector voltage and current waveforms can be represented by the corresponding normal-
ized square and half-sinusoidal waveforms shown in Figs. 7.4(b) and 7.4(c), respectively, where
I0 is the dc current. Here, a sum of odd harmonics approximates a square voltage waveform,
and a sum of the fundamental and even harmonics approximates a half-sinusoidal collector
current waveform. The waveform corresponding to the normalized current flowing into the
quarterwave transmission line shown in Fig. 7.9 represents a sum of even harmonics. As a re-
sult, the shapes of the collector current and voltage waveforms provide a condition where the
current and voltage do not overlap simultaneously.
7.1.4. Effect of saturation resistance
It is useful to analytically estimate the effect of a saturation (or on-resistance) rsat that is
not equal to zero in a real transistor, and transistor therefore dissipates some amount of power
due to the collector current flowing through this resistance when the transistor is turned on. The
simplified equivalent circuit of a Class-F power amplifier with a quarterwave transmission line
where the transistor is represented by a nonideal switch with the saturation resistance rsat and
parasitic output capacitance Cout is shown in Fig. 7.10. During the interval 0 < t when the
switch is turned on, the saturation voltage vsat due to the current i(t) flowing through the switch
can be written as
vsat(t) = Vsat sint = 2IR rsat sint (7.33)
where, by using Eq. (7.10), the saturation voltage amplitude Vsat can be obtained by
R
rV
R
rVV satccsat
Rsat 8
2
. (7.34)
7-14
i
Vcc
/4
R
C0 L0
rsat
Cout
iC
iR iT
vR
Fig. 7.10. Effect of parasitic on-resistance and shunt capacitance.
The corresponding collector current and voltage waveforms are shown in Fig. 7.11, where
the half-sinusoidal current flowing through the saturation resistance rsat causes the deviation of
the voltage waveform from the ideal square waveform. In this case, the bottom part of the volt-
age waveform becomes sinusoidal with the amplitude Vsat during the interval 0 < t . From
Eq. (7.29), it follows that the same sinusoidal behavior will correspond to the top part of the
voltage waveform during the interval < t 2.
i/I0
3.0
2.0
1.0
0 t, 300 240 180 120 60 0
a).
v/Vcc
1.5
1.0
0.5
0 t, 300 240 180 120 60 0
2.0
8 rsat
R
b). Fig. 7.11. Idealized collector current and voltage waveforms with nonzero on-resistance.
The power losses and collector efficiency due to presence of the saturation resistance rsat
can be evaluated using Eqs. (7.6), (7.8), and (7.10) as
sin2 2
2
1
2
0
22R
cc 0
sat2
0 cc 0
sat2
0
sat tdtIVI
rtd
VI
rti
P
P
R
r
V
V
I
I
R
r
I
I
V
Ir sat
cc
R
0
Rsat
0
R
cc
Rsat 2 . (7.35)
Hence, the collector efficiency can be calculated from
R
r
P
P sat
0
sat 2 1 1 . (7.36)
7-15
In practice, the idealized collector voltage and current waveforms can be realized at
low frequencies when effect of the device output capacitance is negligible. At higher frequen-
cies, effect of the output capacitance contributes to a nonzero switching time, resulting in time
periods when the collector voltage and collector current exist at the same time when simultane-
ously v > 0 and i > 0. Consequently, such a load network with shunt capacitance cannot provide
the switching-mode operation with an instantaneous transition from the device pinch-off to sat-
uration mode and vice versa. Therefore, during a nonzero time interval, the device operates in
the active region as a nonlinear current source.
7.1.5. Load networks with lumped and distributed parameters
Theoretical results show that the proper control of only second and third harmonics can
significantly increase the collector efficiency of the power amplifier by flattening the output
voltage waveform. Because practical realization of a multielement high-order LC resonant cir-
cuit can cause a serious implementation problem, especially at higher frequencies, it is suffi-
cient to be confined to a three- or four-element resonant circuit composing the load network of
the power amplifier. In addition, it is necessary to take into account that, in practice, the com-
bined extrinsic and intrinsic transistor output capacitance has a substantial effect on the effi-
ciency. The device output capacitance Cout can represent the collector capacitance Cc in the case
of the bipolar transistor or the sum of the drain-source capacitance and gate-drain capacitance,
Cds + Cgd, in the case of the FET device.
For a lumped-circuit power amplifier, a special three-element load network can be used
to approximate the ideal Class-F mode by providing both high impedance at the fundamental
and third harmonics and zero impedance at the second harmonic at the collector (or drain) by
compensating for the influence of Cout. Examples of such load networks with additional parallel
and series resonant circuits located between the dc power supply and device output are shown
in Fig. 7.12 [12, 13]. Here, the output circuit of the transistor is represented by a multiharmonic
current source, and Rout is the equivalent output resistance at the fundamental frequency defined
as a ratio of the fundamental voltage at the device output to the fundamental current flowing
into the device.
The reactive part of the output admittance (or susceptance) Bnet = Im(Ynet) of the load
network with a parallel resonant tank shown in Fig. 7.12(b), including the device output capac-
itance Cout, can be written as
2222
1
222
outnet 1
1
LCLL
CLCB
. (7.37)
7-16
L1
Cbypass
C2
Rout
Cout
Vcc
L2
To output matching
circuit
L1
Cbypass
C2
Cout
L2
To output matching
circuit
Vcc
b). c).
From device output
Impedance- peaking circuit
To output matching circuit
and load
a).
Ynet
Fig. 7.12. Load networks with parallel and series resonant circuits.
By applying three-harmonic impedance conditions at the device collector (or drain),
open-circuited for the fundamental and third harmonic when Bnet(0) = Bnet(30) = 0 and short-
circuited for the second harmonic when Bnet(20) = , the parameters of this impedance-peak-
ing load network can be derived as
out212out
2o
1 5
12
3
5
6
1CCLL
CL
(7.38)
where the sum of the reactance of the parallel resonant tank, consisting of an inductor L2 and a
capacitor C2, and an inductor L1 create resonances at the fundamental and third-harmonics,
whereas the series capacitive reactance of the tank circuit in series with the inductance L1 cre-
ates a short-circuited series resonance condition at the second harmonic [12, 13].
Applying the same conditions for the load network with a series resonant circuit L2C2
shown in Fig. 7.12(c) results in the ratios between elements given by
out212out
20
1 16
15
15
9
9
4CCLL
CL
(7.39)
where an inductance L2 and a capacitance C2 create a short-circuited condition at the second
harmonic, and all elements create the parallel-resonant tanks at the fundamental and third har-
monics [14].
As a first approximation for comparison between different operation modes, the output
device resistance Rout at the fundamental frequency required to realize a Class-F operation mode
7-17
with third-harmonic peaking can be estimated as the equivalent resistance determined at
the fundamental frequency for an ideal Class-F operation and written as Rout = (F)1R = V1/I1,
where V1 and I1 are the fundamental-frequency voltage and current amplitudes at the device
output, respectively. For the same supply voltage Vcc and output power P1 at the fundamental,
assuming zero saturation voltage and using Eq. (7.14) yield
(B)1
2
1
2cc
20
cc2
)F(1
4
8
8 R
P
V
I
VR
(7.40)
where (B)1R = 2
ccV /2P1 is the output resistance at the fundamental in an ideal Class-B mode.
The ideal Class-F power amplifier with all even-harmonic short-circuit termination and
third-harmonic peaking achieves a maximum drain efficiency of 88.4% [8]. Such an operation
mode can be very conveniently realized by using the transmission lines in the load network.
The impedance-peaking load-network topology of such a transmission-line power amplifier is
shown in Fig. 7.13 [12, 13].
1
Cbypass
Cout
Vdd
To output matching
circuit
Z0, 2
3
Rout
TL1
TL2
TL3
Fig. 7.13. Transmission-line impedance-peaking circuit for Class F.
In this case, a quarterwave transmission line TL1 located between the dc power supply
and the drain terminal provides short-circuit termination for even harmonics. The electrical
length 3 of an open-circuit stub TL3 is chosen to have a quarter wavelength at the third-har-
monic component to realize a short-circuited condition at the right end of the series transmission
line TL2, whose electrical length 2 should provide an inductive reactance to resonate with the
device output capacitance Cout at the third harmonic. As a result, the electrical lengths of the
transmission lines at the fundamental frequency can be obtained as
6
3
1tan
3
1
2 3out0 0
121
CZ (7.41)
where Z0 is the characteristic impedance of the series transmission line TL2 and 0 is the fun-
damental angular frequency.
7-18
7.1.6. Design examples of Class-F power amplifiers
The effectiveness of the Class-F load-network design technique is demonstrated based on
the example of high-power 1.25-m LDMOSFET amplifiers. The circuit schematic of the sim-
ulated 500-MHz single-stage lumped LDMOSFET power amplifier is shown in Fig. 7.14,
where its load network corresponds to that shown in Fig. 7.12(b) and their parameters are cal-
culated from Eq. (7.38). In this case, the total gate width of a high-voltage LDMOSFET device
is 71.44 mm to achieve 8 W of output power. The drain efficiency and power gain of the
power amplifier versus input power Pin for the case of ideal inductors are given in Fig. 7.15(a).
The drain efficiency over 75% is obtained due to a short-circuited condition at the second-
harmonic and open-circuited condition at the third harmonic. Generally, it is important to pro-
vide high-impedance conditions at higher-order harmonics that can be readily done by using an
output matching circuit with the series inductor as a first element. This shortens the switching
time from pinch-off region to voltage-saturation region by better approximating the idealized
drain voltage square waveform, as shown in Fig. 7.15(c).
500
24 V
300
1.5 k
100 pF
3.5 pF
Pout
1.1 pF 6 pF
10 pF
25 nH 2 pF 15 nH
3.6 nH
4.5 nH
Pin
Fig. 7.14. Simulated lumped LDMOSFET Class-F power amplifier.
As follows from Eq. (7.17) for a symmetrical voltage waveform, the initial phases for the
fundamental-frequency and higher-order harmonics should be equal, which is easy to realize
by short-circuited and open-circuited conditions. However, according to Eq. (7.18) for a half-
sinusoidal current waveform, the phases for any higher-order harmonic component should dif-
fer from the phase for the fundamental frequency by 90. This condition is easily realized in a
Class-B load network, where the fundamental component of the drain voltage is in phase with
the fundamental component of the drain current, but, for all higher-order current harmonics, the
impedance of the resonant circuit will be capacitive because the drain current harmonics mostly
flow through the shunt capacitor. Therefore, the accurate harmonic phasing is very important
to improve effectiveness of a Class-F load network. The amplifier drain efficiency and power
7-19
gain will be significantly reduced if the values of the quality factor of the load-network
inductors are sufficiently small. For example, the maximum value of the drain efficiency can
reach only 71% when an inductor quality factor at the fundamental frequency is Qind = 30, as
shown in Fig. 7.15(b).
12.5 17.5 20
efficiency, %
10
60
20
15 Pin, dBm
40
22.5
gain, dB
14
16
18
12.5 17.5 20
efficiency, %
10
60
20
15 Pin, dBm
40
22.5
gain, dB
14
16
18
a).
b).
20
40
vd, V
0 1.0 2.0 3.0 t, nsec
c).
Fig. 7.15. Drain efficiency, power gain, and voltage waveform.
Therefore, it is preferred at high power level to use the load networks with microstrip
lines. Figure 7.16 shows the equivalent circuit of a simulated 500-MHz single-stage microstrip
LDMOSFET power amplifier using an active device with the same geometry. The input and
output matching circuits represent a T-type matching circuit each, consisting of a series mi-
crostrip line, a parallel open-circuit stub, and a series capacitor. To provide even-harmonic
short-circuit termination and third-harmonic peaking for a Class-F mode, an RF grounded quar-
terwave microstrip line and a combination of the series short-length microstrip line and open-
circuit stub with electrical length of 30 at the fundamental frequency are used. Such an output
circuit configuration approximates the square drain voltage waveform with a good accuracy, as
shown in Fig. 7.17(a), and provides the drain efficiency over 75% with a maximum output
power of 8 W, as shown in Fig. 7.17(b). The resulting smaller value of the drain efficiency
7-20
compared to the theoretically achievable one can be explained by the nonoptimized imped-
ances at higher-order harmonics since, unlike a lumped inductor, the transmission line exhibits
an equidistant impedance performance in the frequency domain with consecutive poles and
zeros at the characteristic frequencies. This means that using a simple T-type transmission-line
transformer does not provide high impedance conditions at all higher-order harmonics simulta-
neously.
500
24 V
300
1.5 k
Pout
4.5 pF
50 45
100 pF
2.5 pF
Pin
50 75
30 90
30 12
50 73
30 30
50 13
Fig. 7.16. Simulated microstrip LDMOSFET Class-F power amplifier.
20
40
vd, V
0 1.0 2.0 3.0 t, nsec
12.5 17.5 20
efficiency, %
10
60
20
15 Pin, dBm
40
22.5
gain, dB
14
16
18
a).
b).
Fig. 7.17. Drain voltage waveform, efficiency, and power gain.
Figure 7.18 shows the circuit schematic of a 2-GHz microstrip GaN HEMT power am-
plifier operating in a Class-F mode [15]. The GaN HEMT device on a SiC substrate used in this
power amplifier was provided by Cree having a 3.6-mm gate periphery and maximum operating
frequency of about 40 GHz. Both input and output matching networks terminate the second,
third, and fourth harmonics and some of the higher-order even harmonics using the quarterwave
transmission lines. The device output impedance at the fundamental of 70 Ω was chosen for the
7-21
design as it was a good tradeoff of efficiency and output power. In this case, the load net-
work provides the impedance matching at the fundamental and the corresponding Class-F har-
monic control at the second, third, and fourth harmonics simultaneously. The fundamental
matching was provided by choosing the optimum value of the transmission-line characteristic
impedances Z2 and Z3. Tuning the output matching network which includes the device output
capacitance resulted in a very high third-harmonic impedance of about 400 Ω, whereas the
impedances at the second and fourth harmonics were of about 0.5 Ω and 0.7 Ω, respectively.
Note that high impedance at the fundamental with corresponding high supply voltage was cho-
sen to minimize the effect of the parasitic bondwire and package inductors to provide the near
short-circuited Class-F conditions at the second and higher-order even harmonics, whose effect
becomes significant at higher operating frequencies. An input matching network was designed
to provide a second-harmonic short by using a quarterwave transmission line close to the gate
and conjugate matching at the fundamental. Two shunt RC networks at the input were added to
provide the stability of operation. As a result, the power amplifier achieved the maximum drain
efficiency of 87% and power-added efficiency (PAE) of 83% at an output power of 17.8 W and
at a drain supply voltage of 42.5 V, with a maximum power gain of 15.8 dB and its compressed
value of 13.4 dB at peak PAE. Vdd
TL1
TL2, 2
TL3, 30
90
RL
Z2
Z3
Vg
TL4 90
TL5, 5
6
C1
R1 R2
C2
TL6
Pin
Fig. 7.18. Circuit schematic of transmission-line Class-F GaN HEMT power amplifier.
7.2. Inverse Class F
Effect of the inclusion of the parallel resonant circuit tuned to the second harmonic and
located in series at the anode, as shown in Fig. 7.19(a), was first described and analyzed in the
early 1940s [5, 16]. It was shown that the symmetrical anode current waveform and level of its
depression can be provided with the opposite phase conditions between the fundamental-fre-
quency and second-harmonic components and an optimum value of the ratio between their volt-
age amplitudes. It was noted that high operation efficiency can be achieved even when imped-
ance of the tank circuit to second harmonic is equal or slightly greater than that of the tank
circuit to fundamental frequency. In practical vacuum-tube amplifiers intended for operation at
very high frequencies, the peak output power and anode efficiency can therefore be increased
7-22
by 1.15 to 1.2 times [17]. In addition, it was suggested to use an additional resonator, tuned
to the fourth harmonic and connected in series with the second-harmonic resonator, as shown
in Fig. 7.19(b), to maximize the anode efficiency of the vacuum-tube amplifier with approxi-
mate square voltage-driving waveform [18].
RL
2f0
f0
a).
b).
RL
2f0
f0
4f0
Fig. 7.19. Biharmonic and polyharmonic inverse Class-F power amplifiers.
As a simple solution to realize 180 out-of-phase conditions between the voltage funda-
mental-frequency and second-harmonic components at the device output in vacuum-tube am-
plifiers, it was proposed to use a second-harmonic tank resonator connected in series to the
device input [16]. Such an approach makes it possible to flatten the anode voltage waveform in
active region avoiding the device saturation mode. In this case, the driver stage is loaded by the
nonlinear diode-type input grid impedance of the final-stage tube providing a flattened grid
voltage waveform, which includes the fundamental-frequency and second-harmonic compo-
nents. The presence of the strong second-harmonic component results in a second-harmonic
voltage drop across the resonator. The loaded quality factor of the second-harmonic resonator
must be high enough to neglect the voltage drop at the fundamental frequency. As a result, the
second-harmonic resonator has no effect on the voltage fundamental-frequency component.
However, it provides a phase shift of 180 for the second-harmonic component, as increasing
in a voltage drop across the resonator results in decreasing in the voltage drop across the grid-
cathode terminals.
Figure 7.20 shows that the shapes of the voltage and current waveforms can be signifi-
cantly transformed with increased voltage peak factor and current flattening by adding one ad-
ditional harmonic component with a proper phase. For example, the combination of the funda-
mental-frequency and third harmonic components with 180 out-of-phase shift at the center of
symmetry results in a flattened current waveform with depression in its center, as shown in Fig.
7-23
7.20(a), which can be minimized by using the proper ratio between the amplitudes of the
fundamental and third harmonics. Similarly, the combination of the fundamental and second
harmonics, which are in phase at the center of symmetry, sharpens the voltage waveform cor-
responding to minimum values of the voltage waveform, as shown in Fig. 7.20(b).
2 t
v n = 1, 2
Vcc
0
2 t
i n = 1, 3
I0
0
a).
b). Fig. 7.20. Fourier current and voltage waveforms with third and second harmonics.
7.2.1. Idealized inverse Class-F mode
Generally, an infinite number of even-harmonic tank resonators can maintain a square
current waveform with a half-sinusoidal voltage waveform at the collector. Figure 7.21(a)
shows the basic schematic of an inverse Class-F power amplifier with a multiple-resonator out-
put filter to control the harmonic content of its collector (anode or drain) voltage and current
waveforms, thereby shaping them to reduce dissipation and to increase efficiency. The term
“inverse” means that collector voltage and current waveforms are interchanged compared to a
conventional case under the same idealized assumptions. Consequently, for a purely sinusoidal
current flowing into the load, the ideal collector current waveform is composed by the funda-
mental component and odd harmonics approximating a square waveform. At the same time, the
collector voltage waveform is composed by the fundamental component and even harmonics
approximating a half-sinusoidal waveform. As a result, the shapes of the collector current and
voltage waveforms provide a condition when the current and voltage do not overlap simultane-
ously, similarly to a conventional Class-F mode. Such a condition, with symmetrical collector
7-24
voltage and current waveforms, corresponds to an idealized inverse Class-F operation
mode with 100% collector efficiency.
iR
i I0
v Vcc
a).
b).
RL
2f0
f0
2nf0
RL
2f0
f0
4f0 2nf0
iodd
Vcc
veven
4f0
Fig. 7.21. Basic circuits of inverse Class-F power amplifier with parallel resonant circuits.
Similar analysis of the distribution of voltages and currents in the inverse Class-F load
network as for a conventional Class-F mode results in equations for the collector current and
voltage waveforms as
i(t) = 2I0 i(t + ) (7.42)
where I0 is the dc current, and
v(t) = VR (sint + sint) (7.43)
where VR is fundamental-frequency amplitude at the load. From Eq. (7.42), it follows that max-
imum value of the collector current cannot exceed that of 2I0, and the time duration with max-
imum amplitude defined as i = 2I0 coincides with that with minimum amplitude defined as i =
0. Because the collector current is zero when the switch is turned off, the only possible wave-
form for the collector current is a square wave composing of only dc, fundamental-frequency,
and odd-harmonic components.
By using a Fourier analysis of the current and voltage waveforms, the following equations
for the dc voltage, fundamental voltage and current components in the collector voltage and
current waveforms can be obtained:
The fundamental current component can be calculated using Eq. (7.42) as
02
0R1
4 sin2
1
ItdtIII . (7.44)
The dc voltage Vcc can be calculated from Eq. (7.43) as
R
0
Rcc
2 sin2
2
1
VtdtVV . (7.45)
The fundamental voltage component can be calculated from Eq. (7.43) as
7-25
R
0
2R1 sin2
1 VtdtVV
. (7.46)
Then, the relationship between the dc power P0 and the output power at the fundamental
frequency P1 can be given as
00cc11
1 4
2
2
1
2 P
IVIVP
(7.47)
resulting in a theoretical collector efficiency of 100%.
The impedance conditions seen by the device collector for an idealized inverse Class-F
mode must be equal to
0
cc2
11 8
I
VRZ
(7.48)
harmonics oddfor 0 12n Z (7.49)
harmonicseven for 2n Z . (7.50)
7.2.2. Inverse Class F with quarterwave transmission line
An idealized inverse Class-F operation mode can be represented by using a sequence of
the series resonant circuits tuned to the fundamental and odd harmonics, as shown in Fig.
7.22(a). In this case, it is assumed that each resonant circuit has zero impedance at the corre-
sponding fundamental frequency f0 and odd-harmonic components (2n + 1)f0 and infinite im-
pedance at even harmonics 2nf0 realizing the idealized inverse Class-F square current and half-
sinusoidal voltage waveforms at the device output terminal. As a result, the transistor which is
driven to operate as a switch sees the load resistance RL at the fundamental frequency, whereas
the odd harmonics are shorted by the series resonant circuits.
An infinite set of the series resonant circuits tuned to the odd harmonics can be effectively
replaced by a quarterwave transmission line with the same operating capability. Such a circuit
representation of an inverse Class-F power amplifier with a series quarterwave transmission
line loaded by the series resonant circuit tuned to the fundamental frequency is shown in Fig.
7.22(b) [7, 19]. The series-tuned output circuit presents a load resistance at the frequency of
operation to the transmission line. At the same time, the quarterwave transmission line trans-
forms the load impedance according to
L
20
R
ZR (7.51)
where Z0 is the characteristic impedance of a transmission line. For even harmonics, the open
circuit on the load side of the transmission line is repeated, thus producing an open circuit at
7-26
the drain. However, the quarterwave transmission line converts the open circuit at the load
to a short circuit at the drain for odd harmonics with resistive load at the fundamental frequency.
Vdd
Z0, /4
vin RL
C0 L0 Cb
R
b).
iR
i I0
v Vdd
a).
RL
f0
3f0 5f0 (2n + 1)f0
Fig. 7.22. Inverse Class-F power amplifier with series quarterwave transmission line.
Consequently, for a purely sinusoidal current flowing into the load due to infinite loaded
quality factor of the series fundamentally tuned circuit, the ideal drain current and voltage wave-
forms can be represented by the corresponding normalized square and half-sinusoidal wave-
forms, respectively. Here, a sum of odd harmonics approximates a square current waveform,
and a sum of the fundamental and even harmonics approximates a half-sinusoidal drain voltage
waveform. As a result, the shapes of the drain current and voltage waveforms provide a condi-
tion when the current and voltage do not overlap simultaneously. The quarterwave transmission
line causes the output voltage across the load resistor RL to be phase-shifted by 90 relative to
the fundamental-frequency components of the drain voltage and current.
7.2.3. Load networks with lumped and distributed parameters
Theoretical results show that the proper control of the second harmonic can significantly
increase the collector efficiency of the power amplifier by flattening of the output current wave-
form and minimizing the product of integration of the voltage and current waveforms. Practical
realization of a multi-element high-order LC resonant circuit can cause a serious implementa-
tion problem, especially at higher frequencies and in monolithic integrated circuits, when only
three harmonic components can be effectively controlled. Therefore, it is sufficient to be con-
fined to the three- or four-element resonant circuit composing the load network of the power
amplifier. In this case, the operation with the second-harmonic open circuit and third-harmonic
short circuit is a promising concept for low-voltage power amplifiers [20].
7-27
In addition, it is necessary to take into account that, in practice, both extrinsic and
intrinsic transistor parasitic elements such as the output shunt capacitance or serious inductance
have a substantial effect on the efficiency. The output capacitance Cout can represent the collec-
tor capacitance Cc in the case of the bipolar transistor or the sum of drain-source capacitance
and gate-drain capacitance, Cds + Cgd, in the case of the FET device. The output inductance Lout
is generally composed of the bondwire and lead inductances for a packaged transistor, whose
effect becomes significant at higher frequencies.
Lout
Rout
Cout
To output matching
circuit
L1
C1
Fig. 7.23. Second-harmonic impedance-peaking circuit.
Figure 7.23 shows the equivalent circuit of the second-harmonic impedance-peaking load
network, where the series circuit consisting of an inductor L1 and a capacitor C1 creates a reso-
nance at the second harmonic. Because the device output inductance Lout and capacitance Cout
are tuned to create an open-circuited condition at the second harmonic, the device collector sees
resultant high impedance at the second harmonic. To achieve the second-harmonic high imped-
ance, an external inductance may be added to interconnect the device output inductance Lout
directly at the output terminal (collector or drain) if its value is not sufficient. As a result, the
values of the load-network parameters are defined as
out20
out 4
1
CL
120
1 4
1
CL
. (7.52)
As a first approximation for comparison between different operation classes, the output
device resistance Rout at the fundamental frequency required to realize an inverse Class-F oper-
ation mode with second-harmonic peaking can be estimated as an equivalent resistance Rout =
(invF)1R determined at the fundamental frequency for an ideal inverse Class-F mode. For the same
supply voltage Vcc and output power P1 at the fundamental, assuming zero saturation voltage
and using Eqs. (7.14) and (7.48) yield
(B)1
2(F)1
22
0
cc2
)invF(1 2
8
8
RRI
VR
(7.53)
where (F)1R is the output resistance at the fundamental frequency in a conventional Class-F
mode and (B)1R is the output resistance at the fundamental frequency in an ideal Class-B mode.
7-28
1
Cbypass
Cout
Vdd
To output matching
circuit
Z0, 2
3
Rout
TL1
TL2
TL3
Fig. 7.24. Transmission-line impedance-peaking circuit for inverse Class F.
The ideal inverse Class-F power amplifier cannot provide all the voltage required by the
third- and higher-order odd harmonic short-circuit termination using a single parallel transmis-
sion line, as can be easily realized by a quarterwave transmission line for even harmonics in the
conventional Class-F power amplifier. In this case, with a sufficiently simple circuit schematic
convenient for practical realization, applying the current second-harmonic peaking and voltage
third-harmonic shorting can result in a maximum drain efficiency of more than 80% [21]. The
output impedance-peaking load network of such a microstrip power amplifier is shown in Fig.
7.24, and its circuit structure is similar to that used to provide a conventional Class-F operation
mode.
As it follows from Eq. (7.53), the equivalent output resistance for an ideal inverse Class-
F mode is higher by more than 2.4 times compared to a conventional Class-B mode. Therefore,
using an inverse Class-F mode simplifies the corresponding load-network design by minimizing
the impedance transformation ratio. This is very important for high output power level with a
sufficiently small load impedance. However, maximum amplitude of the output voltage wave-
form can exceed the supply voltage by about three times. In this case, it is required to use the
device with high breakdown voltage or to reduce the supply voltage. The latter, however, is not
desirable because it may result in lower power gain and efficiency.
For such an inverse Class-F microstrip power amplifier, it is necessary to provide the
following electrical lengths for the transmission lines at the fundamental frequency:
4
3
1 2 tan
2
1
3 3
1
out 0 01
21
CZ (7.54)
where Z0 is the characteristic impedance of the microstrip lines. The transmission line TL1 with
electrical length 1 = 60 at the fundamental frequency provides a short-circuited condition for
the third harmonic and introduces a capacitive reactance at the second harmonic. The open-
circuit stub TL3 with electrical length 3 = 45 creates a short-circuited condition at the right
7-29
end of the transmission line TL2 at the second harmonic. Thus, the transmission line TL2
having an inductive reactance is tuned to the parallel resonance condition at the second har-
monic with the device output capacitance Cout and short-circuited transmission line TL1.
7.2.4. Design example of inverse Class-F power amplifier
In a hybrid power amplifier where the packaged device is used, the presence of a transistor
output series bondwire and lead inductance Lout creates some problems in providing an accepta-
ble second- or third-harmonic open- or short-circuit termination. In this case, it is convenient to
use a series transmission line as a first element of the load network connected to the device
output, as shown in Fig. 7.25(a), where the transmission line TL1 is placed between the device
drain and shunt short-circuited quarterwave transmission line TL3. However, if the length of a
combined series transmission line TL1 + TL2 becomes very long in a Class-F mode with a short
circuit at the second harmonic and an open circuit at the third harmonic and additional funda-
mental-frequency matching circuit is required, then such a load network in an inverse Class-F
mode is compact, convenient for harmonic tuning, and very practical.
Vdd
TL3
TL2, 2
TL4
90
30
RL
a).
Cout
2
R
Device output
90 30 RL
b).
TL1, 1
Lout 1
Z1 Z1
Z2
Fig. 7.25. Transmission-line inverse Class-F power amplifier and its equivalent circuit.
Figure 7.25(b) shows the equivalent circuit of a transmission-line inverse Class-F load
network, where the complex-conjugate load matching is provided at the fundamental frequency.
Both high reactance at the second harmonic and low reactance at the third harmonic are created
at the device output by using two series transmission lines TL1 and TL2, whose electrical lengths
depend on the values of the device output shunt capacitance Cout and series inductance Lout,
quarterwave short-circuit stub TL3, and open-circuit stub TL4 with electrical length of 30 [10,
22]. The output shunt capacitance Cout can represent both intrinsic bias-dependent drain-source
7-30
capacitance Cds and extrinsic bias-independent drain pad-contact capacitance Cdp of the
nonlinear large-signal equivalent circuit for GaN HEMT device, whereas the series output in-
ductance Lout is modeled by a combined effect of the metallization, bond wire, and package
inductances [23].
The harmonic conditions for an inverse Class-F load network seen by the device multi-
harmonic current source derived from Eqs. (7.48) through (7.50) for the first three harmonic
components including fundamental are
RZ Re 0net (7.55)
2Im 0net Z (7.56)
0 3Im Im 0net0net ZZ (7.57)
where the load resistance (or equivalent output resistance) R seen by the device output at the
fundamental frequency is defined in an ideal inverse Class-F mode by Eq. (7.53).
R at fundamental
TL1 + TL2
Z1, 1 + 2
TL4 Z2
30
a).
b).
Cout
Lout
RL
Infinite reactance at second harmonic
Z1, 21
Cout
Lout
c).
Zero reactance at third harmonic
Cout
Lout Z1, 3(1 + 2)
TL1
TL1 + TL2
Fig. 7.26. Load networks seen by the device output at corresponding harmonics.
Figure 7.26(a) shows the transmission-line load network seen by the device multi-
harmonic current source at the fundamental frequency, where the combined series transmission
line TL1 + TL2 (together with an open-circuit capacitive stub TL4 with electrical length of 30)
provides an impedance matching between the optimum equivalent output device resistance R
7-31
and the standard load resistance RL by proper choice of the transmission-line characteristic
impedances Z1 and Z2, where Cout and Lout are the elements of the matching circuit. For simplic-
ity of calculation, the characteristic impedances of the transmission lines TL1 and TL2 are set to
be equal to Z1.
The load network seen by the device current source at the second harmonic (considering
the short-circuit effect of the grounded quarterwave transmission line TL3) is shown in Fig.
7.26(b), where the transmission line TL1 provides an open-circuited condition for the second
harmonic at the device output by forming a second-harmonic tank together with the shunt ca-
pacitor Cout and series inductance Lout. Similar load network at the third harmonic is shown in
Fig. 7.26(c), where the open-circuit effect of the grounded quarterwave transmission line TL3
and short-circuit effect of the open-circuit stub TL4 at the third harmonic are used. In this case,
the combined transmission line TL1 + TL2, which is short-circuited at its right-hand side and
connected in series with an inductance Lout provides a short-circuited condition for the third
harmonic at the device output. Depending on the actual physical length of the device package
lead, the on-board adjustment of the transmission lines TL1 and TL2 can easily provide the re-
quired open-circuited and short-circuited conditions (as well as an impedance matching at the
fundamental frequency) because of their series connection to the device output.
By using Eqs. (7.56) and (7.57), the electrical lengths of the transmission lines TL1 and
TL2, assuming the same characteristic impedance Z1 for both series transmission-line sections,
can be defined from
0 2tan 2
1 2
1 1out0out0
ZLC (7.58)
0 3tan 3 2 1 1out0 ZL (7.59)
with the maximum total electrical length 1 + 2 = /3 or 60 at the fundamental frequency or
180 at the third harmonic when Lout = 0.
As a result, the electrical lengths of the transmission lines TL1 and TL2 as analytical func-
tions of the device output series inductance Lout and shunt capacitance Cout are obtained as
out 0 1
outout2
011 2
2 1tan
2
1
CZ
CL
(7.60)
1 1
out012
3tan
3
1
3
Z
L (7.61)
where the transmission-line characteristic impedance Z1 can be set in advance. In order to omit
an additional matching section at the fundamental frequency, the inverse Class-F load network
can also be used to match the equivalent device fundamental-frequency impedance R with the
7-32
standard load impedance RL (usually equal to 50 ). In this case, it is necessary to properly
optimize both characteristic impedances Z1 and Z2.
Fig. 7.27. Transmission-line 10-W inverse Class-F GaN HEMT power amplifier.
Figure 7.27(a) shows the test board of a transmission-line inverse Class-F power ampli-
fier based on a 28-V 10-W Cree GaN HEMT power transistor CGH40010P and transmission-
line load network with the second- and third-harmonic control, as shown in Fig. 7.25(a). The
input matching circuit provides the fundamental-frequency complex-conjugate matching with
the standard 50- source. The parameters of the series transmission line in the load network
were optimized for implementation convenience. In this case, the device input and output pack-
age leads as external elements were properly modeled to take into account effect of their in-
ductances, and their models were then added to the simulation setup. The simulation results of
a transmission-line inverse Class-F GaN HEMT power amplifier shown in Fig. 7.40(b) are
based on a nonlinear device model supplied by Cree and technical parameters for a 30-mil
RO4350 substrate. The maximum output power of 41.3 dBm, power gain of 13.3 dB (linear
gain of about 18 dB), drain efficiency of 80.3%, and PAE of 76.5% are achieved at an operating
frequency of 2.14 GHz with a supply voltage of 28 V and a quiescent current of 40 mA. The
experimental results of the test board shown in Fig. 7.27(a) were very close to the simulated
results obtaining a maximum output power of 41.0 dBm, a drain efficiency of 76.0%, a PAE of
72.2%, and a power gain of 13.0 dB at an operating frequency of 2.14 GHz (gate bias voltage
Vg = 2.8 V and drain supply voltage Vdd = 28 V), achieved without any tuning of the input
matching circuit and load network [10].
7-33
7.3. Class E with shunt capacitance
In late 1940s and early 1950s, during experimental tuning of the vacuum-tube amplifiers
operating in a saturation mode, it was noticed and then concluded that, when the second and
higher-order harmonics are properly phased, efficiency significantly increases when the load
contains reactive components for harmonics, which form the proper shapes of anode voltage
and current [24]. In this case, detuning of the resonant circuit is provided in the direction of
higher frequencies when the operating frequency is lower than the resonance frequency of the
resonant circuit. As a result, anode efficiencies of about 92 to 93% were achieved for the phase
angles of the output load network within 30 to 40, resulting in the proper inductive impedance
at the fundamental frequency and capacitive reactances at the harmonic components seen by
the anode of the active device [25]. A few years later, it was discovered that very high efficien-
cies could be obtained with a series resonant LC circuit connected to a transistor [26]. The exact
theoretical analysis of the single-ended switching-mode power amplifier with a shunt capaci-
tance and a series LC circuit was then given by Kozyrev [27].
7.3.1. Optimum load-network parameters
The single-ended switching-mode power amplifier with a shunt capacitance was intro-
duced as a Class-E power amplifier by Sokals in 1975, and it has found widespread application
because of its design simplicity and high operation efficiency [28, 29]. This type of high-effi-
ciency power amplifiers was then widely used in different frequency ranges and with different
output power levels ranging from several kilowatts at low RF frequencies up to about 1 W at
microwaves [30]. The characteristics of a Class-E power amplifier can be determined by defin-
ing its steady-state collector voltage and current waveforms. The basic circuit of a Class-E
power amplifier with shunt capacitance is shown in Fig. 7.28(a), where the load network con-
sists of a capacitor C shunting the transistor, a series inductor L, a series fundamentally tuned
L0C0 circuit, and a load resistor R. In a common case, a shunt capacitance C can represent the
intrinsic device output capacitance and external circuit capacitance added by the load network.
The collector of the transistor is connected to the supply voltage by an RF choke with high
reactance at the fundamental frequency. The transistor is considered an ideal switch that is
driven in such a way as to provide the instant device switching between its on-state and off-
state operation conditions. As a result, the collector current and voltage waveforms are deter-
mined by the switch when it is turned on and by the transient response of the load network when
the switch is turned off.
7-34
R
L C0
C
Vcc Vbe vb
L0
R C
iC iR i I0
L
v Vcc
C0 L0
a).
b). Fig. 7.28. Basic circuits of Class-E power amplifier with shunt capacitance.
To simplify the analysis of a Class-E power amplifier, whose simplified equivalent circuit
is shown in Fig. 7.28(b), the following assumptions are introduced:
the transistor has zero saturation voltage, zero saturation resistance, infinite off-re-
sistance, and its switching action is instantaneous and lossless
the total shunt capacitance is independent of the collector and is assumed linear
the RF choke allows only a constant dc current and has no resistance
the loaded quality factor QL = L0/R = 1/C0R of the series resonant L0C0 circuit tuned
to the fundamental frequency is high enough for the output current to be sinusoidal at
the switching frequency
there are no losses in the circuit except only in the load R
for simplicity, a 50% duty ratio is used.
For a lossless operation mode, it is necessary to provide the following optimum conditions
for voltage across the switch (just prior to the start of switch on) at t = 2, when transistor is
saturated:
0 2
ttv (7.62)
0
2
ttd
tdv (7.63)
where v(t) is the voltage across the switch.
The detailed theoretical analysis of a Class E power amplifier with shunt capacitance for
any duty ratio is given in [31], where the load current is assumed to be sinusoidal,
sin RR tIti (7.64)
where is the initial phase shift.
7-35
When the switch is turned on for 0 t < , the current through the capacitance
0 C
td
tdvCti
(7.65)
and, consequently,
sin R 0 tIIti (7.66)
under the initial on-state condition i(0) = 0. Hence, the dc current can be defined as
sin R 0 II (7.67)
and the current through the switch can be rewritten by
sin sin R tIti . (7.68)
When the switch is turned off for t < 2, the current through the switch i(t) = 0,
and the current flowing through the capacitor C can be written as
sin R 0С tIIti (7.69)
producing the voltage across the switch by the charging of this capacitor according to
t
tdtiC
tv
1
С
sin cos cos R ttC
I. (7.70)
Applying the first optimum condition given by Eq. (7.62) enables the phase angle to
be determined as
482.32 2
tan 1
. (7.71)
As a result, the normalized steady-state collector voltage waveform for t < 2 and
current waveform for 0 t < are
sin cos
2
2
3
cc
ttt
V
tv (7.72)
1 cos sin
2
0
ttI
ti . (7.73)
Figure 7.29 shows the normalized (a) load current, (b) collector voltage waveform, and
(c) collector current waveforms for an idealized optimum (or nominal) Class-E mode with shunt
capacitance. From collector voltage and current waveforms, it follows that, when the transistor
is turned on, there is no voltage across the switch, and the current i(t), consisting of the load
sinusoidal current and dc current, flows through the device. However, when the transistor is
turned off, this current is flowing through the shunt capacitor C. The jump in the collector cur-
rent waveform at the instant of switching off is necessary to obtain nonzero output power at the
7-36
fundamental frequency delivered to the load, which can be defined as an integration of the
product of the collector voltage and current derivatives over the entire period [32].
-1.5
-1
-0.5
0
0.5
1
1.5
60 120 180 240 300
iR/I0
t,
a).
0
0.5
1
1.5
2
2.5
0 60 120 180 240 300
i/I0
t,
c).
0 0.5
1 1.5
2 2.5
3 3.5
0 60 120 180 240 300
v/Vcc
t,
b).
Fig. 7.29. Normalized (a) load current and collector (b) voltage and (c) current wave-
forms for idealized optimum Class E with shunt capacitance.
The peak collector voltage Vmax and current Imax can be determined by differentiating the
appropriate waveforms given by Eqs. (7.72) and (7.73), respectively, and setting the results
equal to zero, which gives
ccccmax 3.562 2 VVV (7.74)
00
2
max 2.8621 1 2
4 III
. (7.75)
The fundamental-frequency voltage across the switch consists of two quadrature compo-
nents, whose amplitudes can be found using Fourier formulas and Eq. (7.72) as
2cos2 2sin2
sin 1
R2
0
R
C
ItdttvV (7.76)
7-37
2sin2 sin 2
cos 1
2R2
0
L
C
ItdttvV . (7.77)
As a result, the optimum series inductance L, shunt capacitance C, and load resistance R
for the supply voltage Vcc and fundamental-frequency output power Pout can be obtained by
1.1525 R
L V
V
R
L (7.78)
.18360 RR
VI
CCR
(7.79)
out
2cc
out
2cc
20.5768
4
8
P
V
P
VR
. (7.80)
Finally, the phase angle of the load network seen by the switch at the fundamental fre-
quency required for an idealized optimum (or nominal) Class-E mode with shunt capacitance
can be obtained through the load-network parameters using Eqs. (7.78) and (7.79) as
CRR
LCR
R
L
1tan tan 1 1 = 35.945. (7.81)
When realizing a Class-E operation mode, it is very important to know up to which max-
imum frequency such an idealized efficient operation mode can be extended. In this case, it is
important to establish a relationship between the maximum operation frequency fmax, shunt ca-
pacitance C, output power Pout, and supply voltage Vcc by using Eqs. (7.79) and (7.80) when
𝑓 0.0507 𝑃 /𝐶𝑉 (7.82)
where C = Cout is the device output capacitance limiting the maximum operation frequency of
an idealized optimum Class-E power amplifier with shunt capacitance.
The high-QL assumption for the series resonant L0C0 circuit can lead to considerable er-
rors if its value is substantially small in real circuits [33]. For example, for a 50% duty ratio,
the values of the load-network parameters for the loaded quality factor QL less than unity can
differ by several tens of percentages. At the same time, for QL 7, the errors are found to be
less than 10% and they become less than 5% for QL 10. To match the required optimum Class-
E load-network resistance R with a standard load impedance RL, usually equal to 50 , the
series resonant L0C0 circuit should be followed (or fully replaced) by the matching circuit, in
which the first element represents a series inductor to provide high impedance at the second
and higher-order harmonics [27].
7-38
7.3.2. Effect of saturation resistance, finite switching time, and nonlinear shunt capacitance
In practical power amplifier design, especially when a value of the supply voltage is suf-
ficiently small, it is very important to predict the overall degradation of power amplifier effi-
ciency due to finite value of the transistor saturation resistance. Figure 7.30(a) shows the sim-
plified equivalent circuit of a Class-E power amplifier with shunt capacitance, including the
saturation resistance (on-resistance) rsat connected in series to the ideal switch. To obtain a
quantitative estimate of the power losses due to the contribution of rsat, the saturated output
power Psat can be obtained with a simple approximation when the current i(t) flowing through
the saturation resistance rsat is determined in an ideal case by Eq. (7.73).
a).
c).
R C
L
Vcc
C0 L0
C
L
Vcc
C0 L0
rsat
b).
i(s)
1 2
i
2 +1
s
R
s
Fig. 7.30. Equivalent Class-E load networks (a) with saturation resistance and (c) nonlinear capacitance and (b) current waveform with finite time delay.
An analytical expression to calculate the power losses due to the saturation resistance rsat,
whose value is assumed constant, can be represented in the normalized form as
0
2
cc0
sat
0
sat 2
tdtiVI
r
P
P (7.83)
where P0 = I0Vcc is the dc power. As a result, Eq. (7.83) can be rewritten as
R
r
R
r
V
Ir
P
P sat2
2sat2
cc
0sat
0
sat 365.1 4
28
2 28
8
2
. (7.84)
The collector efficiency can be calculated from
7-39
0
sat
0
sat 0
0
out 1
P
P
P
PP
P
P
. (7.85)
Consequently, the presence of the saturation resistance results in finite value of the satu-
ration voltage Vsat, which can be defined from
R
rV
V
satcc
sat
365.1 1
1 1
(7.86)
where Vsat is normalized to the dc supply voltage Vcc [34].
More detailed theoretical analysis of the time-dependent behavior of the collector voltage
and current waveforms shows that, for finite value of the saturation resistance rsat, the optimum
conditions for idealized operation mode given by Eqs. (7.62) and (7.63) do not correspond an-
ymore to minimum dissipated power losses, and there are optimum nonzero values of the col-
lector voltage and its derivative at switching time instant corresponding to minimum overall
power losses [24, 35]. For example, even for small losses with the normalized loss parameter
Crsat = 0.1 for a duty ratio of 50%, the optimum series inductance L is almost two times
greater, whereas the optimum shunt capacitance C is of about 20% greater than those obtained
under nominal conditions. Thus, generally the nominal switching conditions given by Eqs.
(7.62) and (7.63) can be considered optimum only for idealized case of a Class-E load network
with zero saturation resistance providing the switching-mode transistor operation when it oper-
ates in pinch-off and saturation regions only. However, they can be considered as a sufficiently
accurate initial guess for further design and optimization in a real Class-E power amplifier de-
sign.
For an ideal transistor without any memory effects due to intrinsic phase delays, the
switching time is equal to zero when the rectangular input drive results in a rectangular output
response. Such an ideal case assumes zero device feedback capacitance and zero device input
resistance. However, at higher frequencies, it is very difficult to realize the driving signal close
to the rectangular form, as it leads to the significant circuit complexity. Fortunately, to realize
high-efficiency operation conditions, it is sufficient to drive the power amplifier simply with a
sinusoidal signal. The finite-time transition from the saturation mode to the pinch-off mode
through the device active mode takes place due to the device inertia when the base (or channel)
charge changes to zero with some finite delay time s, as shown in Fig. 7.30(b). To minimize
the switching time interval, it is sufficient to slightly overdrive the transistor with a signal am-
plitude by 20 to 30% higher than is required for a conventional Class-B power amplifier.
The power dissipated during this on-to-off transition can be calculated assuming zero on-
resistance as
7-40
s
2
1 s tdtvtiP (7.87)
where the collector voltage during the transition time s = s is defined as
s
1
Cs tdtiC
v . (7.88)
The short duration of the switching time and the proper behavior of the resulting collector
(or drain) waveform allows us to make an additional assumption of a linearly decreasing col-
lector current during fall time s = s, starting at i(s) at time s and decaying to zero at time
2 = [36]. As a result, the power dissipated during transition can be then written by assuming
in view of a short transition time that i(s) = i() = 2I0 as
12
12
2s
cc
2s0
0
s
CV
I
P
P. (7.89)
As a result, the collector efficiency can be estimated as
12 1 1
2s
0
s
P
P. (7.90)
As follows from Eq. (7.89), the power losses due to nonzero switching time are suffi-
ciently small and, for example, for s = 0.35 or 20, they are only about 1%, whereas they are
approximately equal to 10% for s = 60. A more exact analysis assuming linear variation of
the collector current during on-to-off transition produces similar results when efficiency de-
grades to 97.72% for s = 30 and to 90.76% for s = 60 [37]. Considering an exponential
collector current decay rather than linear during the fall time shows similar result for s = 30
when = 96.8%, but the collector efficiency degrades more significantly at longer fall times
when, for example, = 86.6% for s = 60 [38].
In a common case, the intrinsic output device capacitance is nonlinear, as shown in Fig.
7.30(c). If its contribution in overall shunt capacitance is sufficiently large, it is necessary to
consider the nonlinear nature of this capacitance when specifying the breakdown voltage. For
example, the collector voltage waveform will rise in the case of the output capacitance de-
scribed by abrupt diode junction in comparison with the linear capacitance, and its maximum
voltage can be greater by about 20% for a 50% duty ratio [27, 39]. However, stronger nonline-
arity of the shunt capacitance causes the peak voltages to be higher [40]. At the same time, the
deviations of the optimum load-network parameters are insignificant, less than 5% in a wide
range of supply voltages. Because the nonlinear capacitance is largest at zero voltage, the col-
lector waveform will rise more slowly than in the linear case. As the collector voltage increases,
the capacitance will decrease, and hence the voltage should begin to rise faster than in the linear
7-41
case. If the shunt capacitance consists of both nonlinear and linear capacitances, the col-
lector voltage waveform is intermediate and located between the two extreme cases of entirely
nonlinear or entirely linear capacitance [41].
7.3.3. Load network with transmission lines
The transmission lines are often preferred over lumped inductors at microwave frequen-
cies for high-power amplifiers because of the convenience of their practical implementation,
more predictable performance, less insertion loss, and less effect of the parasitic elements. For
example, the matching circuit can be composed with any types of the transmission lines, in-
cluding open- or short-circuit stubs, to provide the required matching and harmonic suppression
conditions. In this case, to approximate the idealized Class-E operation mode of the microwave
power amplifier, it is necessary to design the transmission-line load network satisfying the re-
quired idealized optimum impedances at the fundamental-frequency and harmonic components.
The device output capacitance can fully represent the required shunt capacitance, whose nom-
inal value is defined by Eq. (7.79). Consequently, the main challenge is to satisfy the idealized
optimum requirements for the fundamental-frequency impedance ZL(0) shown in Fig. 7.31(a)
and harmonic impedances ZL(n0) shown in Figs. 7.31(b), which can be written using Eq. (7.78)
as
49.052 tan 1 1 0L jRR
LjRLjRZ
(7.91)
0L nZ (7.92)
where 0 is the fundamental angular frequency and n 2 is the harmonic number.
c).
2
2 0 t
v/Vcc
3
1
3 4
R
L
ZL(0)
Cout
Transistor output
a).
ZL(n0)
Cout
Transistor output
b).
Fig.7.31. Optimum load impedance and two-harmonic Class-E voltage waveform.
7-42
Generally, it is practically impossible to realize these conditions for an infinite num-
ber of harmonic components by using only transmission lines. However, as it turns out from
the Fourier-series analysis, a good approximation to Class-E mode may be obtained with the
dc, fundamental-frequency, and second-harmonic components of the voltage waveform across
the switch [42, 43]. Figure 7.31(c) shows the collector (drain) voltage waveform containing
these two harmonic components (dashed curve) plotted along with an ideal voltage waveform
(solid curve). In practical implementation, the two-harmonic Class-E load network designed for
microwave applications will include the series microstrip line l1 and open-circuit stub l2, as
shown in Fig. 7.32(a). The electrical lengths of microstrip lines l1 and l2 are chosen to be of
about 45 at the fundamental frequency to provide an open-circuit condition seen from the de-
vice output at the second harmonic, according to Eq. (7.92). Their characteristic impedances
are calculated to satisfy the required inductive impedance condition at the fundamental fre-
quency given by Eq. (7.91). However, for a packaged active device, its output lead inductance
should be accounted for by shortening the length of l1.
RL
Vcc
b).
a).
l1 l2
Cout
RL
Vdd
Transistor output l1
l2 Cout
90 @ 2.7 GHz
90 @ 1.8 GHz
ZL
Transistor output
Fig. 7.32. Equivalent circuits of Class-E power amplifiers with transmission lines.
In some cases, a value of the device output capacitance exceeds the required nominal
value for a Class-E mode with shunt capacitance. In this situation, it is possible to approximate
Class-E mode with high efficiency by setting a properly optimized load at the fundamental
frequency and strong reactive load at the second- and third-harmonic components [44]. Such a
harmonic-control network consists of open-circuit quarterwave stubs at the second- and third-
harmonic components separately, as shown in Fig. 7.32(b), where the third-harmonic quarter-
wave stub is located before the second-harmonic quarterwave stub. As a result, a very high
collector efficiency can be achieved even with values of the device output capacitance higher
than conventionally required at the expense of lower output power, while keeping the load at
the second and third harmonics strictly inductive (inverse mode).
7-43
7.3.4. Practical Class-E power amplifiers
High level of output power with very high operational efficiency can be easily achieved
in a Class-E mode by using high-voltage power MOSFET devices at high (HF) and very high
(VHF) frequencies. Figure 7.33(a) shows the circuit schematic of a 27.12-MHz, 500-W Class-
E MOSFET power amplifier with a drain efficiency of 83% at a supply voltage of 125 V [45].
The input ferrite transformer provides the 2:1 transformation voltage ratio to match the gate
impedance, which is represented by the parallel equivalent circuit with a capacitance of 2200
pF and a resistance of 210 Ω. Use of the external parallel resistor of 25 Ω simplifies the match-
ing procedure and improves the amplifier stability conditions. The transformer secondary wind-
ing provides an inductance of 19 nH, which is required to compensate for the device input
capacitance at the fundamental. High-quality passive components are necessary to use in the
low-pass L-type output network, where the quality factor of the bare copper wire inductor was
equal to 375. The series blocking capacitor consists of three parallel disc ceramic capacitors.
To realize a Class-E operation with shunt capacitance, it is sufficient to be limited to only the
output device capacitance with a value of 125 pF. This is just slightly larger than that required
to obtain the idealized optimum drain voltage and current Class-E waveforms.
a).
Pin
50
56 pF 47 nH
Pout 50
24 pF CRF24060
90 nH
30 V
22 pF
b).
82 pF
13.5 V
90 nH 470 pF
1 nF
12 pF
47 nH
220 nH
68 pF 47 pF
47 nH 56 nH
Pin
T1
125 V
25
75-380 pF
210 nH
Pout
30 nF
0.1 F
75-380 pF
ARF448A
6 H
10 nF 10 nF 0.1 F
Fig. 7.33. High-power lumped Class-E power amplifiers.
Figure 7.33(b) shows the simplified circuit schematic of a silicon carbide (SiC) MESFET
Class-E power amplifier that provides a maximum drain efficiency of 86.8% at an output power
7-44
of 20.5 W at 145 MHz reached at a drain voltage of 30 V, with an input drive power level
of 27 dBm [46]. The nominal Class-E impedance of approximately 18 was matched to a 50-
load with a low-pass three-section L-type matching network to suppress harmonics by at least
60 dB below the carrier. The input of the active device was matched to 50- source by means
of a high-pass filter network to prevent the attenuation of the high-frequency harmonic compo-
nents of the driving signal. Because this power amplifier was designed to provide linear ampli-
fication by restoring the input signal envelope with drain amplitude modulation, the drain bias
network was built with a low-pass filter that allows drain modulating frequencies of up to a few
megahertz to pass through it with minimum attenuation, while at the same time achieving ac-
ceptable isolation at the carrier frequency and its harmonics.
Pout
Pin
Vg
C1
R1
TL5 TL1
TL2
TL3 C2
TL4
Fig. 7.34. Circuit schematic of transmission-line Class-E power amplifiers.
Figure 7.34 shows the circuit schematic of a K-band transmission-line Class-E power
amplifier using a single-section load network, which is well suited for monolithic implementa-
tion at upper microwave frequencies [47]. The electrical parameters of the capacitive stubs TL2
and TL3 were designed to provide low impedances at the second and third harmonics by making
the electrical length of the stubs exactly one quarter-wavelength at a particular harmonic. At
the same time, the characteristic impedances of the stubs are chosen to provide the desired
capacitive reactance for load impedance transformation at the fundamental frequency. The elec-
trical parameters of the series transmission line TL1 are determined by the requirements to pro-
vide the optimum inductive impedance with a load angle of 49.05 at the fundamental and to
transform the low impedance of the stub inputs toward higher reactances at the selected har-
monics. As a result, by using a GaAs pHEMT technology and coplanar waveguides for trans-
mission-line implementation, an output power of 20 dBm, a drain efficiency of 59%, and a
power gain of 7.5 dB were achieved at an operating frequency of 24 GHz with a supply voltage
of 2.4 V when both the second and third harmonics are suppressed by more than 30 and 35 dB,
respectively.
7-45
7.4. Class E with finite dc-feed inductance
In practice, it is impossible to realize RF choke with infinite impedance at the fundamen-
tal frequency and other harmonic components. Moreover, using a finite dc-feed inductance has
an advantage of minimizing size, cost, and complexity of the overall circuit. The detailed ap-
proach to analyzing the effect of a finite dc-feed inductance on the idealized Class-E mode with
shunt capacitance and series filter was first described in [48]. An analysis was based on the
Laplace-transform technique to solve a second-order differential equation describing the be-
havior of a Class-E load network with finite dc-feed inductance. Later this approach was ex-
tended to the load network with finite QL-factor of the series filter and finite device saturation
resistance [49, 50]. However, because the results of excessive analytical and numerical calcu-
lations are given only for a few special cases, it is difficult to figure out the basic behavior of
the load-network elements and derive simple equations for their parameters. Later, it was ana-
lytically shown for a 50% duty ratio based on the optimum Class-E conditions that the series
excessive reactance can be either inductive or capacitive depending on the values of the dc-feed
inductance and shunt capacitance [51, 52].
7.4.1. General analysis and optimum load-network parameters
The generalized second-order load network of a switching-mode Class E power amplifier
with finite dc-feed inductance is shown in Fig. 7.35(a) [53-55]. The load network consists of a
shunt capacitor C, a parallel inductor L, a series inductor Lb, a series reactance X, a series reso-
nant L0C0 circuit tuned to the fundamental frequency, and a load resistance R. In a common
case, a shunt capacitance C can represent the intrinsic device output capacitance and external
circuit capacitance added by the load network, a series inductor Lb can be considered a a
bondwire and lead inductance, a parallel inductance L represents the finite dc-feed inductance,
and a series reactance X can be positive (inductance), negative (capacitance), or zero depending
on the certain Class-E mode. The active device is considered an ideal switch that is driven to
provide the device instant switching between its on-state and off-state operation modes. To
simplify an analysis of the general-circuit Class-E power amplifier, whose simplified equivalent
circuit is shown in Fig. 7.35(b), it is best to introduce the preliminary assumptions similar to
those for the Class-E power amplifier with shunt capacitance, assuming that the losses in the
reactive circuit elements are negligible, the duty ratio is 50%, the loaded quality factor of the
series L0C0 circuit is sufficiently high, and to set an inductance Lb to zero. For a lossless opera-
tion mode, it is necessary to provide the optimum zero-voltage and zero-voltage-derivative con-
ditions for voltage v(t) across the switch just prior to the start of switch on, when transistor is
saturated, given by Eqs. (7.62) and (7.63).
7-46
R L C
Vcc
C0 L0
R C
iC iR
i
L v
Vcc
iL
L0 C0
a).
b).
Lb
Lb
iLb
VR
VX
jX
jX
Fig. 7.35. Equivalent circuits of the Class-E power amplifiers with generalized load network.
The output current flowing through the load is written as sinusoidal by
sin RR tIti (7.93)
where IR is the load current amplitude and is the initial phase shift.
When the switch is turned on for 0 t < , the voltage on the switch is v(t) = Vcc
vL(t) = 0, the current flowing through the capacitance is iC(t) = C(dvL/dt) = 0, and
sin 0 1
RL
0
ccR L tIitdVL
tititit
sin sin Rcc tItL
V (7.94)
where the initial value for the current iL(t) flowing through the dc-feed inductance L at t = 0
can be found using Eq. (7.93) for i(0) = 0 as iL(0) = IRsin.
When the switch is turned off for t < 2, the switch current i(t) = 0, and the current
iC(t) = iL(t) + iR(t) flowing through the capacitance C can be rewritten as
sin 1
RL cc tIitdtvVLtd
tdvC
t
(7.95)
under the initial off-state conditions v() = 0 and
sin R cc
RL LIL
Viii .
Equation (7.95) can be represented in the form of the linear nonhomogeneous second-
order differential equation
0 cos
Rcc2
22
tLIVtvtd
tvdLC (7.96)
the general solution of which can be obtained in the normalized form
7-47
cos
1 1 sin cos
2
2
2 1cc
tq
pqtqCtqC
V
tv (7.97)
where
LCq
1
(7.98)
cc
R V
LIp
(7.99)
and the coefficients C1 and C2 are determined from the initial off-state conditions [36].
The dc supply current I0 can be found using Fourier formula and Eq. (7.94) by
sin cos 2 2
2
2
1
2R
2
0
0 p
ItdtiI . (7.100)
In an idealized Class-E operation mode, there is no nonzero voltage and current simulta-
neously that means a lack of power losses and gives an idealized collector efficiency of 100%.
This implies that the dc power P0 and fundamental output power Pout are equal,
R
VVI
2
2R
cc0 (7.101)
where VR = IRR is the fundamental voltage amplitude across the load resistance R.
As a result, by using Eqs. (7.100) and (7.101) and considering that R = 2RV /2Pout, the
optimum load resistance R for the specified values of a supply voltage Vcc and fundamental
output power Pout can be obtained by
out
2cc
2
cc
R 2
1
P
V
V
VR
(7.102)
where
sin cos 2
2
1
2
cc
R
pV
V. (7.103)
The normalized load-network inductance L and capacitance C can be appropriately de-
fined using Eqs. (7.98) through (7.100) as
sin cos 2
2
/ p
pR
L (7.104)
R
LqCR
/ 1 2 . (7.105)
The series reactance X, which may have an inductive, capacitive, or zero reactance in
special cases depending on the load-network parameters, can be generally calculated using two
quadrature fundamental-frequency voltage Fourier components
7-48
sin 1
2
0
R tdttvV
(7.106)
tdttvV
cos 1
2
0
X . (7.107)
The fundamental-frequency current flowing through the switch consists of two quadrature
components, whose amplitudes can be found using Fourier formulas and Eq. (7.94) by
tdttiI
sin 1
2
0
R
2sin
2
sin 2 cos R
p
I (7.108)
tdttiI
cos 1
2
0
X
2R sin 2
cos 2 sin
p
I. (7.109)
Generally, Eq. (7.97) for normalized collector voltage contains three unknown parameters
q, p, and , which must be analytically or numerically determined. In a common case, the pa-
rameter q can be considered a variable, and the other two parameters p and are calculated
from a system of two equations resulting from applying two optimum zero-voltage and zero-
voltage derivative conditions given by Eq. (7.62) and (7.63) to Eq. (7.97). Figure 7.36 shows
the dependences of the optimum parameters p and versus q for a Class E with finite dc-feed
inductance.
5
10
15
20
0
5
0
20
40
60
80
20
p ,
0.8 1.1 1.4 1.7 q
Fig. 7.36. Optimum Class-E parameters p and versus q.
7-49
Based on the calculated optimum parameters p and as functions of q, the optimum
load-network parameters of the Class-E load network with finite dc-feed inductance can be
determined using Eqs. (7.102) through (7.105). The series reactance X can be calculated by the
ratio of two quadrature fundamental-frequency voltage Fourier components given in Eqs.
(7.106) and (7.107) as
R
X V
V
R
X . (7.110)
0
10
15
10
15
0.8 1.1 1.4 1.7
L/R
5
5
1.5
1.0
0.5
0
0.5
1.0
1.5
a).
X/R
0.5
1.0
1.25
0.8 1.1 1.4 1.7
0.75
b).
CR
0.25
0.5
1.0
1.25
0.75
0.25
q
q 0.5
RPout /Vcc 2
Fig. 7.37. Normalized optimum Class-E load network parameters.
The dependences of the normalized optimum dc-feed inductance L/R and series reac-
tance X/R are shown in Fig. 7.37(a), whereas the dependences of the normalized optimum shunt
capacitance CR and load resistance 2ccout /VRP are plotted in Fig. 7.37(b). Here, the value of
the series reactance X changes its sign from positive to negative, which means that the inductive
reactance is followed by the capacitive reactance. As a result, there is a special case of the load
network with a parallel circuit and a load resistor only when X = 0 at q = 1.412. In this case, the
maximum value of the optimum load resistance R can be provided for the same supply voltage
7-50
and output power, thus simplifying the matching with the standard load of 50 . In addi-
tion, the values of a dc-feed inductance L become sufficiently small, making Class-E mode with
a parallel circuit very attractive for monolithic applications. The maximum operation frequency
fmax is realized at q = 1.468, where the normalized optimum shunt capacitance CR reaches its
maximum.
7.4.2. Parallel-circuit Class E
The theoretical analysis of a switching-mode parallel-circuit Class-E power amplifier
with a series filter, whose basic circuit schematic is shown in Fig. 7.38(a), was first published
by Kozyrev with calculation of the voltage and current waveforms and some graphical results
[27, 56]. The load network consists of a finite dc-feed inductor L, a shunt capacitor C, a series
L0C0 resonant circuit tuned to the fundamental frequency, and a load resistor R. In this case, the
switch sees a parallel connection of the load resistor R and parallel LC circuit at the fundamental
frequency, as shown in Fig. 7.38(b), where also the real and imaginary collector fundamental-
frequency current components IX and IR and the real collector fundamental-frequency voltage
component VR are indicated.
R L C
Vcc
C0 L0
R C L
IX
IR
VR
a).
b).
Fig. 7.38. Equivalent circuits of parallel-circuit Class-E power amplifier.
In the case of a parallel-circuit Class-E load network without series phase-shifting reac-
tance, because the parameter q is unknown a priori, generally it is necessary to solve a system
of three equations to define the three unknown parameters q, p, and . The first two equations
are the result of applying two optimum zero-voltage and zero-voltage-derivative conditions
given by Eq. (7.62) and (7.63) to Eq. (7.97). Because the fundamental-frequency collector volt-
age is fully applied to the load, this means that its reactive part must have zero value, resulting
in an additional equation
7-51
0 cos 1
2
0
X tdttvV
. (7.111)
Solving the system of three equations with three unknown parameters numerically gives
the following values [57, 58]:
q = 1.412 (7.112)
p = 1.210 (7.113)
= 15.155. (7.114)
Figure 7.39 shows the normalized (a) load current and collector (b) voltage, and (c) cur-
rent waveforms for an idealized optimum parallel-circuit Class-E operation mode. From col-
lector voltage and current waveforms, it follows that, like other Class-E subclasses, there is no
nonzero voltage and current simultaneously. When this happens, no power loss occurs and an
idealized collector efficiency of 100% is achieved.
1.0
0.5
0
0.5
1.0
60 120 240 300 t,
iR/I0
180
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0 60 120 180 240 300 t,
v/Vcc
a).
b).
0
0.5
1.0
1.5
2.0
2.5
60 120 180 240 300 t, 0
i/I0
c).
Fig. 7.39. Normalized (a) load current and collector (b) voltage and (c) current waveforms for idealized optimum parallel-circuit Class E.
By using Eqs. (7.102) through (7.105), the idealized optimum (or nominal) load resistance
R, parallel inductance L, and parallel capacitance C can be appropriately obtained by
7-52
out
2cc 1.365
P
VR (7.115)
R
L 0.732 (7.116)
R
.C
6850
. (7.117)
The dc supply current I0 can be calculated from Eq. (7.100) as
R 0 0.826 II . (7.118)
The phase angle seen from the device collector at the fundamental frequency can be
represented either through two fundamental-frequency current quadrature Fourier components
IX and IR given by Eqs. (7.108) and (7.109) or as a function of the load-network elements by
RC
L
R
tan 1 = 34.244. (7.119)
If the calculated value of the optimum Class-E load resistance R is too small or differs
significantly from the standard load impedance (usually equal to 50 Ω), it is necessary to use
an additional matching circuit to deliver maximum output power to the load. It should be noted
that, among a family of the Class-E load networks, a parallel-circuit Class-E load network offers
the largest value of R, thus simplifying the final matching design procedure. In this case, the
first series element of such matching circuits should be the inductor to provide high impedance
conditions for harmonics, as shown in Fig. 7.40.
RL
Device output L1
C1 C L
Matching circuit
C2
R
Fig. 7.40. Parallel-circuit Class-E power amplifier with lumped matching circuit.
The peak collector current Imax and peak collector voltage Vmax can be determined from
Eqs. (7.94), (7.97), and (7.118) as
0max 2.647 II (7.120)
ccmax 3.647 VV . (7.121)
The maximum frequency fmax can be calculated using Eq. (7.115) and (7.117) when C =
Cout, where Cout is the device output capacitance, as
7-53
2ccout
outmax 0.0798
VC
Pf (7.122)
which is 1.57 times higher than the maximum operation frequency for an optimum Class-E
power amplifier with shunt capacitance given by Eq. (7.82).
7.4.3. Even-harmonic Class E
The well-defined analytic solution based on an assumption of the even-harmonic resonant
conditions when the finite dc-feed inductance and parallel capacitance are tuned to any even-
harmonic component was given in [59]. The load network of an even-harmonic Class E is
shown in Fig. 7.41, where the series capacitor CX is needed to compensate for the excessive
inductive reactance caused by the preliminary choice of the specified load-network parameters.
The value of this capacitance can be found from the consideration of two fundamental-fre-
quency voltage quadrature components across the switch given by Eqs. (7.106) and (7.107).
R L C
Vcc
C0 L0 CX
Fig. 7.41. Equivalent circuit of the even-harmonic Class-E power amplifier.
Since, for an even-harmonic Class-E operation mode, the dc-feed inductance is restricted
to values that satisfy an even-harmonic resonance condition and it is assumed the fundamental-
frequency voltage across the switch and output voltage across the load have a phase difference
of /2, the two unknown parameters can be set in this specified case as
q = 2n (7.123)
= 90 (7.124)
where n = 1, 2, 3, … .
The third parameter p can be found using an idealized optimum zero voltage-derivative
condition given by Eq. (7.63) as
8
1 4
2
2
n
np
. (7.125)
The dc supply current I0 can be found from Eq. (7.100) by
R2
2
0
0 1 42
1
2
1 I
ntdtiI
. (7.126)
7-54
As a result, the normalized steady-state collector voltage waveform for t < 2
and current waveform for period of 0 t < are
2cos 2sin 4
sin2
1
cc
tntnn
tV
tv (7.127)
tnnt
n
I
ti
cos 1 4 1 4
8 2
222
0
. (7.128)
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0 60 120 180 240 300 t,
v/Vcc
a).
b).
0
0.5
1.0
2.5
4.0
60 120 180 240 300 t, 0
i/I0
c).
iR/I0
4
2
0
2
4
6
t, 300 240 180 120 60
3.5
3.0
2.0
1.5
Fig. 7.42. Normalized (a) load current and collector (b) voltage and (c) current waveforms for idealized optimum even-harmonic Class E.
Figure 7.42 shows the normalized (a) load current, (b) collector voltage, and (c) collector
current waveforms for an idealized optimum even-harmonic Class-E mode. If the collector volt-
age waveform corresponding to even-harmonic Class E is very similar to the collector voltage
waveform corresponding to Class E with shunt capacitance, then the behavior of the collector
current waveform is substantially different. For even-harmonic Class-E configuration, the col-
lector current reaches its peak value, which is four times as high as the dc current, at the end of
7-55
the conduction interval. Consequently, in the case of a sinusoidal driving signal it is im-
possible to provide close to the maximum collector current when the input base current is
smoothly reducing to zero.
The optimum load-network parameters for the most practical case when n = 1 can be
calculated from
out
2cc
out
2cc 0.056
18
1
P
V
P
VR (7.129)
RR
L 3.534 8
9 (7.130)
RRC
1
0.071 1
9
2 (7.131)
RRC
1
0.204 1
3 32
4
2X
. (7.132)
The main problem of an even-harmonic Class-E operation mode is a substantially small
value of the load resistance R, which is over an order of magnitude smaller than for a Class E
with shunt capacitance and much smaller than for a parallel-circuit Class E.
The phase angle between the fundamental-frequency voltage and current components
seen by switch is equal to
RCRC
RC
L
R
X2
X
2X 1
1
4
3
= 22.302 (7.133)
whereas the maximum frequency fmax, up to which an idealized optimum even-harmonic Class-
E mode can be realized, is calculated from
2ccout
out2
ccout
out2max 0.203
2
VC
P
VC
Pf
(7.134)
where Cout is the device output capacitance.
7.4.4. Load networks with transmission lines
At microwave frequencies, the parallel inductance L can be replaced by a short-length
short-circuited transmission line TL according to
ωL θZ tan0 (7.135)
where Z0 and are the characteristic impedance and electrical length of such a transmission
line, respectively [60]. By using Eq. (7.116) defining the idealized optimum (or nominal) par-
allel inductance L for a parallel-circuit Class-E mode, Eq. (7.135) can be rewritten as
0
0.732 tanZ
Rθ . (7.136)
7-56
Generally, the load-network circuit can be composed with any types of transmission
lines, including open-circuit or short-circuit stubs to provide the required matching and har-
monic-suppression conditions. In some cases, for example, for compact small-size power-am-
plifier modules designed for handset or small-cell wireless transmitters, the series microstrip
lines and shunt chip capacitors are usually used in the external output matching circuits. How-
ever, to maintain the optimum-switching conditions at the fundamental frequency, such an out-
put matching circuit should contain the series transmission line as the first element.
30 , 8
Cbypass
Cout
3.5 V
5 pF 4 pF 50
50 12
50 , 16 10 pF
Znet(0)
Znet(20)
Znet(30)
Znet()
b).
a).
R
Fig. 7.43. Transmission-line load network of parallel-circuit Class-E power amplifier
for handset application.
Figure 7.43(a) shows an example of the transmission-line Class-E load network of a two-
stage 1.75-GHz GaAs HBT power amplifier with an output power of 33 dBm, which was de-
signed for a cellular handset transmitter, and includes the series microstrip line with two shunt
chip capacitors [57]. However, because of the fixed electrical lengths of the transmission lines,
it is impossible to realize simultaneously the required inductive impedance at the fundamental
frequency with the purely capacitive reactances at higher-order harmonics. For example, at the
second harmonic, the real part of the load network impedance Znet(20) is sufficiently high, as
shown in Fig. 7.43(b). Nevertheless, even such an approximation provides a good proximity to
the parallel-circuit Class-E operation mode, resulting in a high operating efficiency of the power
amplifier. In this case, there is no need to use an additional RF choke for dc supply current,
because its function can be performed by the same short-length parallel microstrip line required
to provide an optimum inductive impedance at the fundamental frequency.
The circuit schematic of a two-stage InGaP/GaAs HBT power amplifier intended to
operate in the WCDMA handset transmitters is shown in Fig. 7.44(a) [61]. The MMIC part of
this power amplifier contains the transistors with emitter areas of the first and second stage as
7-57
large as 540 μm2 and 3600 μm2, input matching circuit, interstage matching circuit, and
bias circuits on a die with overall dimension of less than 1 mm2. The broadband capability of
the PA was verified with regard to the DCS1800 and PCS1900 frequency bands. Without any
tuning of the output matching circuit, a saturated output power greater than 30 dBm and a PAE
greater than 50% were obtained. Using high-Q capacitors in output matching circuit can
improve the power-added efficiency by about 8%. The power gain of 22.5±0.5 dB and the input
return loss greater than 13 dB were measured from 1.6 GHz to higher than 2 GHz. At the same
time, this power amplifier without any additional tuning could provide the high-linearity
performance for WCDMA band (1920-1980 MHz) at a 3.5-dB backoff output power of 27 dBm
with a power gain of 22.6 dB and a sufficiently high efficiency. The measured PAE reached
value of 38.3% at center bandwidth frequency of 1.95 GHz with an adjacent channel leakage
power ratio (ACLR) of –37 dBc at a 5-MHz offset.
Pin
Vg
Vdd
1 k
12
/4
470 pF
15 pF
470 pF
9.1 pF
1 nH
Pout
MRF21010
a).
3.5 V
Pout
Bias circuit
Bias circuit
Z0 = 50 = 15
Pin
2.7 V
MMIC
b).
Fig. 7.44. Schematics of Class-E power amplifiers with transmission-line matching.
Figure 7.44(b) shows the circuit schematic of a 1-GHz 12-V LDMOSFET parallel-circuit
Class-E power amplifier with a drain efficiency of 70.4% and an output power of more than 38
7-58
dBm [62]. In this case, the series LC resonant circuit is replaced by a low-pass L-type
output matching circuit with a series transmission line to match the low optimum Class-E re-
sistance to a 50- load, having almost zero series excessive reactance X. The quarterwave trans-
mission line in the gate bias circuit provides RF isolation from the dc-voltage supply, and the
12- gate resistor is required for stability reason.
7.5. Class E with shunt capacitance and shunt filter
Class E with shunt capacitance and shunt filter represents an alternative to Class E with
shunt capacitance and series filter when high loaded quality of the shunt filter is provided by
higher value capacitance rather than inductance, thus making such a Class-E power amplifier
more compact when no need to use high-value inductors in both dc-supply and resonant circuits.
In this case, much better harmonic suppression can be achieved by using a high-Q shunt filter
with a low-value shunt capacitance. The theoretical analysis and practical implementation of a
vacuum-tube Class-E amplifier with shunt filter was first provided in late 1960s [24]. This cir-
cuit was analyzed by solving the second-order differential equation for voltage across shunt
capacitor but the final design equations for the load-network parameters were not derived in
explicit form. The anode voltage and current waveforms were analytically derived and numer-
ically calculated for the specific case of q = 2.
7.5.1. Basic analysis and optimum load-network parameters
The optimum parameters of a single-ended Class-E power amplifier with shunt capaci-
tance and shunt filter can be determined based on an analytical derivation of its steady-state
collector voltage and current waveforms. Figure 7.45(a) shows the basic circuit configuration
of a Class-E power amplifier with shunt capacitance and shunt filter, where the load network
consists of a shunt capacitor C, a series inductor L, a blocking capacitor Cb, a shunt fundamen-
tally tuned L0C0 circuit, and a load resistor R [63, 64]. In this case, the shunt L0C0 circuit oper-
ates as a harmonic filter creating zero impedance at the second- and higher-order harmonics
instead of the open-circuit harmonic conditions corresponding to classical Class-E power am-
plifier with shunt capacitance and series filter. In a common case, a shunt capacitance C can
represent the intrinsic device output capacitance and external circuit capacitance added by the
load network. The dc power supply is generally connected by an RF choke with infinite reac-
tance at the fundamental and any higher-order harmonic component. The active device is con-
sidered an ideal switch that is driven at the operating frequency to provide instantaneous switch-
ing between its on-state and off-state operation conditions.
7-59
R
L
C0 C
Vcc
L0
C
iC
iR
i
L
v
a).
b).
Cb
R C0 L0 vR
iL
Vcc
I0
Vcc
Fig. 7.45. Basic circuits of Class-E power amplifier with shunt filter.
To simplify the analysis of a Class-E power amplifier with shunt filter, whose equivalent
circuit is shown in Fig. 7.45(b), the following several assumptions are introduced:
the transistor has zero saturation voltage, zero saturation resistance, infinite off-resistance,
and its switching is instantaneous and lossless
the shunt capacitance is assumed to be constant
the shunt L0C0 filter has zero impedance at the second- and higher-order harmonics
there is no loss in the circuit except the load R
for simplicity, a 50% duty ratio is used.
For idealized lossless operation mode, it is necessary to provide the zero-voltage and zero-
voltage-derivative conditions for voltage across the switch (just prior to the start of switch on)
at the instant t = 2, when transistor is saturated. Then, expressions for the collector current
(0 t < ) and voltage ( t < 2) for ideal L0C0-circuit tuned to the fundamental frequency
when the sinusoidal current iR = IR sin(t + ) flows into the load can be written as
cos cos RccL t
L
Vt
L
Vtiti (7.137)
0 sin Rcc2
22
tVVtvtd
tvdLC (7.138)
where is the initial phase shift and VR = IRR is the voltage amplitude across the load resistance
R [63].
The general solution of Eq. (7.138) can be given in the normalized form as
𝐶 cos 𝑞𝜔𝑡 𝐶 sin 𝑞𝜔𝑡 1
sin 𝜔𝑡 𝜑 (7.139)
7-60
where 𝑞 1/√𝐿𝐶 and the coefficients C1 and C2 are determined from the initial off-state
conditions. The fundamental-frequency voltage across the switch consists of two quadrature
components with an amplitude of the real component defined by Fourier formula as
sin 1
2
0
R tdttvV
. (7.140)
As a result, by solving a system of three equations – two of them defined by the Class-E
switching conditions given by Eqs. (7.62) and (7.63) and the third one for VR given by (7.140)
– the three unknown parameters can be calculated as
= 41.614 (7.141)
q = 1.607 (7.142)
0.9253 cc
R V
V. (7.143)
The dc current I0 can be determined by applying a Fourier-series expansion to Eq. (7.137).
Then, the optimum normalized series inductance L and shunt capacitance C can be defined
using Eqs. (7.141) through (7.143) and assuming an idealized collector efficiency of 100%
given by Eq. (7.101) as
R
L 1.4836 (7.144)
RC
0.261
(7.145)
whereas the optimum load resistance R can be obtained for the given supply voltage Vcc and
fundamental output power Pout by
out
2cc
out
2cc
2
cc
R
out
2R
4281.0 2
1
2
1
P
V
P
V
V
V
P
VR
. (7.146)
Figure 7.46 shows the normalized collector (a) voltage and (b) current waveforms for
idealized optimum Class-E mode with shunt filter during the entire interval 0 t 2. From
the collector voltage and current waveforms, it follows that, when the transistor is turned on,
there is no voltage across the switch and the current from the inductor flows through the switch.
However, when the transistor is turned off, this current flows through the capacitor C. In this
case, there is no nonzero voltage and current simultaneously, which means a lack of the power
losses that gives an idealized collector efficiency of 100%.
7-61
0 t
0 t 2
i/I0
2.0
1.0
v/Vcc
2
3.0
2.0
1.0
a).
b). Fig. 7.46. Normalized collector (a) voltage and (b) current waveforms for
idealized optimum Class E with shunt filter.
The phase angle of the load network at fundamental seen by the switch which is re-
quired for an idealized optimum (or nominal) Class-E mode with shunt capacitance and shunt
filter can be determined through the load-network parameters using Eqs. (7.144) and (7.145) as
945.23 1
tan tan 1 1
CRR
LCR
R
L
(7.147)
The peak collector voltage Vmax and current Imax are defined as
(7.148)
(7.149)
that shows that the voltage peak factor is as high as in classical Class E with shunt capacitance
and series filter [36].
In Table 7.2, the optimum impedances seen by the device collector at the fundamental-
frequency and higher-order odd and even harmonic components are illustrated by the appropri-
ate circuit configurations. As it is seen, Class-E mode with shunt capacitance and shunt filter
shows different impedance properties from other alternative Class-E load networks. At even
harmonics, its optimum impedances can be established by the parallel LC circuit, similarly to
Class E with quarterwave line and series filter. However, at odd harmonics, the optimum im-
pedances for Class E with shunt capacitance and shunt filter differ from Class E with series
3.677 cc
max V
V
2.768 0
max I
I
7-62
filter and Class E with quarterwave line where impedances are defined by the shunt capac-
itances, because they are also provided by the parallel LC circuits.
Table 7.2. Optimum impedances at fundamental and harmonics.
Class E with shunt capacitance and series filter
f0 (fundamental)
Class-E load network 2nf0
(even harmonics) (2n+1)f0
(odd harmonics)
C
L
R
C C
C
C
L
R
Class E with quarterwave line
and series filter [36]
Class E with shunt capacitance
and shunt filter C
L
R
C L
C L C L
Table 7.3. Load-network parameters for different Class-E modes.
Normalized load-network
parameter
Class E with shunt capacitance and series filter
Class E with quarterwave line and
series filter [36]
Class E with shunt capacitance
and shunt filter
R
L 1.1525 1.349 1.4836
CR 0.1836 0.2725 0.261
2cc
out V
RP 0.5768 0.465 0.4281
out
2ccoutmax
P
VCf 0.0507 0.093 0.097
The optimized load-network parameters of the different Class-E modes including Class E
with series filter, Class E with quarterwave line, and Class E with shunt filter are shown in
Table 7.3 in a normalized form. As can be seen, Class E with shunt filter offers the larger value
of the shunt capacitance C for the same load R and much higher value of the maximum operat-
ing frequency fmax for the same dc supply voltage Vcc, device output capacitance Cout, and output
power Pout, compared to Class E with shunt capacitance and series filter. At the same time,
difference between Class E with quarterwave line and Class E with shunt filter is not so signif-
icant because the quarterwave line being grounded at its end through bypass capacitor operates
for even harmonics as a shunt filter.
7-63
Note that generally the shunt capacitance can differ from its nominal Class-E value
defined by Eq. (7.145) at high operating frequencies because the value of the device output
capacitance is too large. To compensate for the excess capacitance, need to add an additional
reactive element between the shunt filter and the load resistance, similar to Class E with finite
dc-feed inductance. An example of such a Class-E load network with an additional reactance
where the value of the circuit parameter q is smaller than its nominal value given by Eq. (7.142)
was analyzed in [65]. In this case, a shunt capacitance with optimum value was connected in
parallel to the load resistance.
7.5.2. Load network with transmission lines
Figure 7.47 shows the circuit schematic of a high-efficiency Class-E power amplifier with
transmission-line shunt filter and output matching circuit, where the nominal load resistance R
= ReZnet(0) is matched to the standard load impedance RL = 50 at the fundamental frequency
using an output transmission-line L-type impedance transformer. Here, the shunt harmonic filter
is composed of 45 short-circuit and open-circuit stubs to create short-circuited conditions at
even harmonics. To create a short-circuited condition at the third harmonic at the right-hand
side of the series inductor represented by a short-length series transmission line with the char-
acteristic impedance Z0 and electrical length , the series transmission line with electrical length
of 60 and an open-circuit stub with electrical length of 30 are used.
Vdd
45
RL
Z0,
45
Z1, 60
Z2, 30 C Znet
Fig. 7.47. Schematic of Class-E power amplifiers with transmission-line load network.
For electrical length of a sufficiently short series transmission line with the characteristic
impedance Z0 and electrical length of less than 45, the required optimum value of for
Class-E mode with shunt capacitance and shunt filter using (7.144) can be approximated by
0
1 4836.1 tan Z
R . (7.150)
7-64
The output matching circuit is necessary to match to the required optimum Class-E
resistance R calculated in accordance with (7.146) to the standard load resistance of 50 Ω. In
addition, it is required to provide a short-circuit condition at the third harmonic component.
This can be easily done using the output matching topology in the form of an L-type transformer
with the series transmission line and open-circuit stub. Its load-network impedance Znet at the
fundamental can be written as
L2121
211 2L1net
60tan 30tan
60tan 60tan30tan
RZZjZZ
ZjZZZRZZ
(7.151)
where Z1 and Z2 are the characteristic impedances of the series transmission line and shunt
open-circuit stub, respectively.
Consequently, the complex-conjugate matching with the load at the fundamental can be
provided by proper choice of the characteristic impedances Z1 and Z2. Separating Eq. (7.151)
into real and imaginary parts and considering that ReZnet = R and ImZnet = 0, the system of two
equations with two unknown parameters can be written as
0 34 3 3 L2 2
21
2L
221 RRZZRRZZ (7.152)
0 3 3 12212L
2 2
21 ZZZZRZZ (7.153)
which enables the characteristic impedances Z1 and Z2 to be properly calculated.
This system of two equations can be explicitly solved as a function of the parameter r =
RL/R, resulting in
r
r
R
Z
3
1 4
L
1 (7.154)
r
r
Z
Z 1
2
1 . (7.155)
As a result, for specified value of the parameter r with the required optimum load re-
sistance R, corresponding to Class E with shunt capacitance and shunt filter, and standard load
RL = 50 Ω, first the characteristic impedance Z1 is calculated from (7.154) and then the charac-
teristic impedance Z2 is calculated from (7.155). For example, if the required optimum load
resistance is equal to R = 20 Ω, resulting in r = 2.5, the characteristic impedance of the series
transmission line is equal to Z1 = 35 Ω and the characteristic impedance of the open-circuit stub
is equal to Z2 = 58 Ω.
7.5.3. Design example of transmission-line Class-E power amplifier
Figure 7.48 shows the simulated circuit schematic, which approximates the transmission-
line Class-E power amplifier with shunt filter and based on a 28-V 10-W Cree GaN HEMT
power transistor CGH40010F and transmission-line load network including a shunt filter and a
7-65
transmission-line matching section. The input matching circuit provides a complex-conju-
gate matching with the standard 50- source. The load network was slightly modified by opti-
mizing the parameters of the series and shunt transmission lines because the device output ca-
pacitance Cout and series inductance Lout formed by drain bondwires and package lead do not
match the required exact values of C and L for a nominal Class-E mode with shunt filter.
2.45 V
Pin
Z = 50 Ohm
C = 3 pF
28 V
R = 10 Ohm
Subst = RO4350 W = 350 mil L = 380 mil
CGH40010F
Subst = RO4350 W = 45 mil L = 250 mil
Subst = RO4350 W = 180 mil L = 520 mil
Subst = RO4350 W = 150 mil L = 270 mil
Subst = RO4350 W = 67 mil L = 415 mil
Subst = RO4350 W = 180 mil L = 450 mil
Subst = RO4350 W = 120 mil L = 230 mil
Subst = RO4350 W = 67 mil L = 415 mil
Z = 50 Ohm
C = 5 pF
Fig. 7.48. Circuit schematic of transmission-line Class-E GaN HEMT power amplifier with shunt filter
For the transmission-line GaN HEMT Class-E power amplifier with shunt filter using a
30-mil RO4350 substrate, the simulated drain efficiency of 83%, a PAE of 80.4%, and a power
gain of 15 dB at an output power of 40.3 dBm with a quiescent current of 30 mA are achieved
at an operating frequency of 2.14 GHz with a supply voltage of 28 V, as shown in Fig. 8. The
second and third harmonics were suppressed by greater than 50 dB.
Fig. 7.49. Simulated results of transmission-line Class-E GaN HEMT power amplifier with
shunt filter.
7.6. Biharmonic Class-EM power amplifier
A basic limitation of a Class-E operation mode at higher frequencies is significant effi-
ciency degradation due to the increased switching power losses with increasing values of the
7-66
turn-off switching time. To minimize this undesirable effect, it is necessary to find a solu-
tion without instant jump in an ideal collector current waveform at turn-off to allow efficient
operation at frequencies high enough that the switch turn-off transition would occupy a sub-
stantial fraction of the waveform period, of 30% and more. However, the Class-E power am-
plifier can deliver nonzero output power only if at least one of the switch waveforms, either
voltage or current, has a jump under assumption that the circuit comprises an ideal switch and
linear passive components [32]. To satisfy the requirements of both jumpless voltage and cur-
rent waveforms and sinusoidal load waveform with nonzero output power delivered to the load,
it is necessary to allow power flow in the system at two or more harmonically related frequen-
cies. This can be done by using nonlinear reactive elements in the load network to convert the
fundamental-frequency power to a desired harmonic frequency or by injecting the harmonic-
frequency power into the load network from an external source.
The simplest low-order implementation approach having jumpless switch voltage and
current waveforms, called the biharmonic Class-EM mode and described in [66], comprises the
two-part output stage including
main amplifier that consumes dc power equal to approximately 75% of the load power
and converts this power and the power generated by the auxiliary amplifier to power
at the output frequency f
smaller auxiliary amplifier (or varactor frequency multiplier) phased locked to the
main amplifier, which generates approximately 25% of the load power at the frequency
2f.
The main amplifier has jumpless switch voltage and current waveforms, whereas the aux-
iliary amplifier can be a conventional Class-E power amplifier. If the frequency multiplier is
fed from the output of the main amplifier, the load power is reduced by the amount of power
converted by the frequency multiplier from frequency f to frequency 2f to change the waveform
shapes to continuous ones. The higher-order implementations can use harmonic components of
order higher than two, or multiple harmonics. For operation at higher frequencies, the bi-
harmonic Class-EM power amplifier can be energetically superior to a conventional Class-E
power amplifier using the same power device and supplying the same output power at the same
operating frequency. That is because it can tolerate slow transistor turn-off with much less ef-
ficiency loss. In addition, less input drive is needed for the biharmonic Class-EM power ampli-
fier because slower switching times are tolerable when considering that switching times are
inversely proportional to the square root of the input driving power.
7-67
50
IRFZ24N
11.5 V
179.8 H
603 pF
3.5 MHz
110 pF
6.4 H
11.5 V
7 MHz
510 pF
IRFZ24N
100 H 4.78 H
Injection auxiliary generator
Zinj = Rinj + jXinj
Z = R + jX
Fig. 7.50. Biharmonic Class-EM power amplifier schematic.
Figure 7.50 shows the circuit schematic of a biharmonic Class-EM MOSFET power am-
plifier designed to operate at 3.5 MHz with second-harmonic power injection from an auxiliary
amplifier operating at 7 MHz. The derivation of the ideal drain waveforms of the main amplifier
assumes that the resultant current of the active device, operating as a switch, and its shunt ca-
pacitor contains only dc, fundamental, and second-harmonic components written as
2sin 2cos sin cos 2B2A1B1A0 tItItItIIti (7.156)
where I0 is the dc current, I1A and I1B are the quadrature fundamental current components and
I2A and I2B are the quadrature second-harmonic current components, respectively. The shunt
capacitances at the transistor drains can be composed of the device output capacitances and
external capacitances.
For a 50% duty ratio when the switch is turned off during 0 < t , the current through
the switch i(t) = 0, and the current iC(t) flowing through the capacitor C fully represents the
current i(t) given in Eq. (7.156), reproducing the voltage across the switch by charging of this
capacitor according to
tdtiC
tvt
1
0 . (7.157)
The conditions for a biharmonic Class-EM optimum operation with jumpless voltage and
current waveforms, v(t) and i(t), are written as
0 0
tti
(7.158)
7-68
0
t
ti (7.159)
0
t
tv (7.160)
0
0
ttd
tv
. (7.161)
Substituting Eq. (7.156) into Eq. (7.157) and applying the boundary conditions given by
Eqs. (7.158) through (7.161) yield
0 1A I (7.162)
01B 2 II
(7.163)
02A II (7.164)
02B 4 II
. (7.165)
As a result, the normalized steady-state idealized switch voltage waveform for a period
of 0 t < and current waveform for a period of t < 2 are obtained by
2cos 2sin
4 sin
2 1
0
tttI
ti (7.166)
3 24sin 2cos cos 4 8 2
dd
tttt
V
tv (7.167)
where Vdd is the dc supply voltage.
Figure 7.51(b) shows the normalized switch voltage and current waveforms for an ideal-
ized optimum biharmonic Class EM with second-harmonic power injection. From switch volt-
age and current waveforms, it follows that, when the transistor is turned on, there is no voltage
across the switch and the current i(t) consisting of the dc, fundamental, and injected second-
harmonic components flows through the device. However, when the transistor is turned off, this
current flows through the shunt capacitance C. There is no jump in the switch current waveform
at the instant of switching off compared to the switch current corresponding to a Class E with
shunt capacitance, the voltage and current waveforms of which are shown in Fig. 7.51(a). How-
ever, the voltage peak factor is higher in a biharmonic Class-EM mode exceeding a value of 4.
Note that injecting a higher-order harmonic component will generally increase the voltage peak
factor even more. Also, there is no solution for a biharmonic Class-EM mode with third-har-
monic injection and duty ratio of 50%. The voltage peak factor can exceed a value of 7 for a
third-harmonic injection with a duty ratio of 33%. The voltage and current waveforms of the
auxiliary amplifier are the usual waveforms corresponding to a Class E with shunt capacitance.
7-69
b).
0 0.5
1 1.5
2 2.5
3 3.5
0 60 120 180 240 300
v/Vdd, i/I0
a).
t, 360
Voltage Current
0 0.5
1 1.5
2 2.5
3 3.5
0 60 120 180 240 300
v/Vdd, i/I0
t, 360
Voltage Current
4
Fig. 7.51. Normalized ideal switch waveforms of (a) Class-E with shunt capacitance and
(b) biharmonic Class-EM with second-harmonic power injection.
In a biharmonic Class-EM mode, it is assumed that the dc power P0 = I0Vdd is equal to
approximately 75% of the output load power Pout delivered to the load that results in
dd
outcc0 4
3
V
PVI . (7.168)
The fundamental-frequency load-network impedance of the main amplifier and the sec-
ond-harmonic injection-port impedance of the auxiliary amplifier can be determined by a Fou-
rier-series analysis of the voltage and current waveforms. As a result, the optimum shunt ca-
pacitance C and load-network impedance Z = R + jX for the main amplifier as a function of the
dc supply voltage Vdd and output power Pout are written as
2dd
out
64
3
V
PC
(7.169)
out
2dd
29
128
P
VR
(7.170)
out
2dd
3
2
9
32 3 32
P
VX
(7.171)
whereas the optimum injection-port impedance Zinj = Rinj + jXinj for the auxiliary amplifier can
be calculated from
7-70
out
2dd
2inj16 9
128
P
VR
(7.172)
out
2dd
2
2
inj16 9
16 3 16
P
VX
. (7.173)
The measured output power of a second-harmonic Class-EM power amplifier was 13.2 W
with overall PAE of 85.2% at an operating frequency of 3.5 MHz. The injected power at 2f
necessary to achieve jumpless drain waveforms was measured as 29.8% of the total dc power
of the main amplifier instead of the theoretical value of 25% due to the resistive power losses
in reactive components, finite loaded quality factors of the series filters, and harmonic power
conversions in the nonlinear device capacitances. To achieve simple and accurate design for the
Class-EM power amplifier with higher-order circuits, the numerical design procedure can be
applied [67]. The analytical expressions for Class-EM power amplifier considering the funda-
mental-frequency and harmonic components in the output currents of the main and auxiliary
circuits are given in [68].
0
20
40
60
0 5 10 15 20 25
PAE, %
s/T, %
Class EM
80
Class E
Fig. 7.52. Efficiency versus switching time for Class-EM and Class-E power amplifiers.
Figure 7.52 shows the comparison between power-added efficiencies of the second-har-
monic Class-EM and classical Class-E power amplifiers as functions of the normalized transistor
switching time s [66]. It is assumed that the switching time is inversely proportional to the
input-drive power. The plots were simulated for power amplifiers delivering the output power
3.2 W at an operating frequency of 870 MHz using a pHEMT device with a gate periphery of
0.5 m 50 mm in the main amplifier. The peak value of a PAE for the biharmonic Class-EM
power amplifier is 3.3% lower than that for the classical Class-E power amplifier. However, a
PAE for the Class-EM power amplifier varies by just 2% for all switching times from 6% to
30% of the period, whereas a PAE for the Class-E power amplifier drops monotonically from
its peak to 73.5% of its peak value for switching times of 30% of the period. In an alternative
7-71
configuration of the biharmonic Class-EM power amplifier, one of the harmonics existing
at drain of the main stage is filtered, amplified, phase shifted, and injected back to output of the
main stage [69]. As a result, with second harmonic injection scheme delivering a 250-mW
power while consuming 370 mW of power, an output power of 29 dBm with a power gain of
14 dB and a peak PAE of 63% was obtained at 2.4 GHz using a 0.25-m pHEMT technology.
Ropt CS1
iR
is1
LC1 vs1
VDC1
iDC1
L1 C1
jX1
Main circuit
TL1
/4
ZM
TL2 /4
jX2
L2
C2
CS2
is2
LC2 vs2
VDC2
iDC2
Auxiliary circuit iinj
S1
S2
Isolation circuit
Fig. 7.53. Circuit schematic of Class-EM power amplifier with isolation circuit.
An analysis of the Class-EM power amplifier can be simplified and accurate explicit de-
sign equations for the load-network parameters can be derived by using an isolation circuit
incorporated between the main and auxiliary circuits, thus resulting in a new configuration of
the Class-EM power amplifier as shown in Fig. 7.53 [70]. Here, the main and auxiliary circuits
each consists of a shunt capacitance (Cs1, Cs2), an RF choke (LC1, LC2), a series resonant circuit
(L1C1 tuned at the fundamental f0, L2C2 tuned to 2f0), and a series reactance (X1, X2), respec-
tively. The isolation circuit consists of a series quarterwave transmission line (TL1) and an open-
circuit quarterwave stub (TL2), providing a short-circuited termination at fundamental and odd
harmonics with the corresponding open-circuited termination due to TL1. Thus, the impedance
ZM presented by the auxiliary circuit to the main circuit is sufficiently high with good isolation
of the main circuit from auxiliary one at fundamental and odd harmonics. In this case, an anal-
ysis of the main and auxiliary circuits can be done separately.
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