Chapter 4 Digital Logic Families

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CHAPTER 4Digital Logic Families

SOLUTIONS

Ans.1 (A)The truth table shows the circuit to be an AND gate for positive logic

1 2 0Actual Logic Actual Logic Actual Logic

0 0 0 0 1 0

1 0 0 1 1 1

Ans.2 (B)The truth table show the circuit to be an OR gate for a negative logic


1 1 1 0 1 1

1

0

1 0 0 0

Ans.3 (B)If either or both of 12are logic high, then 0is high otherwise 0 = 0. Thus ORlogic.

Ans.4 (C)Each of diode logic perform AND function

= = Ans.5 (D)

All diodes are in reverse bias hence all diode current are zero.

Ans.6 (A)Since 1 = 25 , 1, 20is OFF


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0 =2 5 2 0

20.5+

40 0.5

20.5= 25.4

1 = 2 =25.4 25

1= 0.4 , 0 = 0

Ans.7 (C)When 1 = 02 = 10 = 5 , we assume 1ON,

2 0Since 0 , 0 = 52 us reverse biased by 20 V. Hence it is off, 1is forward biased by 5 V hence it is ONTo have 0 ON 0must be greater than 0

0 = 5

20+

5 01

> 0

=> + 5 + 120 > 0=> 125

Ans.8 (A)Each diode causes a voltage level loss of 0.75 V.

Therefore 0.75 n < 2.5V=> = 3

Ans.9 (D)If 1 > ,1is saturated and 0 = If 2 > ,2is saturated and 0 = Further if 12are both saturated, 0 = However, if both 12 < ,

Both 12are OFF and 0 = The following truth table shows NOR logic


0 0 1 0 1 0 1 0 0 1 1 0

Ans.10(CThe circuit responses to actual voltage 12 are unchanged; however theinterpretation differs. The logic entries in the truth table in previous solution take on


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Digital Logic Families CHAPTER 4


the logic complement value.When the resulting truth table is constructed, the NAND gate function is apparent.

Ans.11(D) = +5, = = 0.2

Ans.12(D)If 1 > , 1 is saturated and 01 = . If 2 > , 2 is saturated and01 = . Also if 12are both saturated, 01 = . Otherwise, 01 = .A truth table shows NOR logic for 01as output


1 1 0 0 0 1 1 0 0 0 1 0

Ans.13(B)The 3stage is simply an inverted (a NOT gate). Thus output 02is the logic compementof 01 . Therefore, this is a OR gate.

Ans.14(A)When 1is saturated, 01 is logic LOW otherwise 01is logic HIGH. The following tableshown AND logic

1 2 11 1 1

0 1 01 0 0

0 0 0

Ans.15(C)The 2stage is simply an inverter. Thus output 2is the logic complement of 01.

Ans.16(C)If 1 = 2 , 1 . If 12 > , while 21 , 1(2) is ON and 2(1) isOFF and 1 . If 1 = 2 > , both 12 are ON and 1 2 ( ). The

truth table shows NAND logic1 2 0

Actual Logic Actual Logic Actual Logic

0 0 1 1 0 1 0 1 1 1 1 2 0

Ans.17(A)The 3stage is simple an inverter. Hence AND logic

Ans.18(C)


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For each successive gate, that has a transistor in saturation, the current required is

=

=

=5 0.2

50640= 0.15

For n attached gate = To assume no logic error

0 = 0 > = 3.5

3.5

=5 3.5

6400.15 = 15.6 => 15

Ans.19(A)Let 1 = 2 = 0, then 3will be ON, 12 OFF and 4ON, hence 0 = .Let 1 = 0 2 = then 3 will be ON, 1 OFF 4 OFF, 2 ON, hence0 = .Let 1 = 2 = 0 , then 3OFF, 4ON, 2OFF hence 0 =

Finally if 1 = 2 = , 34 will be OFF and 1, 2 will be ON.Hence 0 = 0 . Thus the given CMOS gate satisfies the function of a negative NANDgate.

Ans.20 (C)If = then 1 is ON and = 0 . If = = = 0 then32are ON but 1is OFF.Hence = 0 . If = 0 and either or both , are 0 V then 1is OFF and either orboth 23 will be OFF, which implies no current flowing through 4. Hence = .Thus given circuit satisfies the logic equation + .

Ans.21(A)Let 1 = 2 = 0 = (0) then 43 will be ON and 2 1 OFF hence0 = = (1).Let 1 = 0, 2 = then 42 will be ON but 3 1 be OFF hence0 = 0 = (0).Let 1 = , 2 = 0, then 4 3will be OFF and 1ON hence 0 = 0 = 0Finally if 1 = 2 = , 12 will be ON but 4will be OFF hence 0 = 0 = (0).Thus the given CMOS satisfy the function of a positive NOR gate.

Ans.22(A)If either one or both the inputs are 0 = 0the corresponding FET will be OFF, thevoltage across the load FET will be 0 V, hence the output is . If both inputs are1 = , both 12are ON and the output is 0 = 0 . It satisfy NAND gate.

Ans.23(B)If both the inputs are at 0 = 0, the transistor 12are OFF, hence the outputis 1 = .If either one or both of the inputs are at 1 = , the corresponding FET will be ONand the output will be 0 = 0. Hence it is a NOR gate.

Ans.24 (A)If all inputs A, B and C are HIGH, then input to inverter us LOW and output Y is HIGH. If


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all inputs are LOW, then input to inverter is also LOW and output Y is HIGH.In all other case the input to inverter is also LOW and output Y is LOW.

= + = + + +

Ans.25 (B)The operation of this circuit is given below:

A B C Y 0 ON OFF HIGH

0 0 1 ON ON OFF OFF OFF ON HIGH

1 1 OFF OFF ON ON LOW

1 1 OFF OFF ON ON LOW

= +

Ans.26(C)The operation of circuit is given below

A C C D Y

1 OFF ON LOW 0 0 ON ON OFF OFF HIGH

0 0 1 0 ON ON OFF ON OFF OFF ON OFF HIGH

0 1 1 0 ON OFF OFF ON OFF ON ON OFF LOW

1 0 1 0 OFF ON OFF ON ON OFF ON OFF LOW

1 1 1 0 OFF OFF OFF ON ON ON ON OFF LOW

= + +

Ans.27(B)If input E is LOW, output will not be LOW. It must be HIGH. Option (B) satisfy thiscondition.

Ans.28(A)In this circuit parallel combination are OR gate and series combination are AND gate.

Hence

= + + +

Ans.29(A)When an output is HIGH, it may be as low as ( ) = 2.4 . The minimum voltagethat an input will respond to as a HIGH is ( ) = 2.0 . A negative noise spike thatcan drive the actual voltage below 2.0 V if its amplitude is greater than

= ( ) ( )= 2.4 2.0 0.4

Ans.30(A)When an output is LOW, it may be as high as ( ) = 0.4 . The maximum voltagethat an input will respond to as a LOW is ( ) = 0.8 . A positive noise spike thatcan drive the actual voltage below 0.8 V level if its amplitude is greater than

= ( ) ( )= 0.8 0.4 0.4

Ans.31(B)


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A positive noise spike can drive the voltage above 1.0 V level if the amplitude is greater

than = ( ) ( )

= 1 0.1 = 0.9 ,A negative noise spike can drive the voltage below 3.5 V if the amplitude is greater than

= ( ) ( )

= 4.9 3.5 = 1.4

Ans.32(B)( ) = ( )

= 0.8 0.5 = 1.3 ( ) = ( )

= 0.5 + 2 = 1.5

Ans.33(C) = ( ) ( )

= ( ) ( ) = 2.7 2.0 = 0.7 = 0.8 0.5 = 0.3

Ans.34(B) = 2.5 2.0 = 0.5 = 0.8 0.4 = 0.4

Ans.35(D)( ) = 0.5 ( ) = 0.3

Ans.36(B) =

( )( )

=8

0.1 = 80

=( )( )

=400

20= 20

The fanout is chosen the smaller of the two.

Ans.37(B)In high state the loading on the output of gate 1 is equivalent to six 74LS input load.

Hence load = 6 = 6 2 0 120

Ans.38(C)The NAND gate represent only a single input load in the LOW state. Hence only five

loads in the LOW state.Load = 5 = 5 0.4 = 2

Ans.39(A)


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The 2(Integrated injection logic) has higher density of integration than TTL becauseit does not required transistors with high current gain and hence they have smallergeometry.

Ans.40(B)The correct order of increasing noise is

RTL, ECL, DTL, MOS,

Ans.41(B)The figure is as shown below

Ans.42(D)When any of the input or the input or all the inputs are high then transistor goes into

saturation and output will be low.When all inputs are zero then transistor is in cut off region and output will be high. This

is a NOR gate. = + +

Ans.43(B)If either A or B is low, then diode 12 will conduct, and point E will be at low.If both A and B are high, diode 12 both are off, and point E is at high. Thus12from the AND function =and similarly = 5 6from a OR gate, so

= + , = +

Ans.44B = 0 then first transistor will be cut-off and current through left resistor will drive thesecond transistor into saturation

Then 0 = , + 1.25 103 103 = 1.35

Ans.45D1 =1

/ = 1 +2

= 1 +2 =1.2

Ans.46C


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When = 3 1will be in reverse active mode i.e. reverse on the 2will be on.

Ans.47DAns.48BAns.49BAns.50DAns.51CTTL-Transistor logic

C MOS complementary Metal Oxide Semiconductor

Ans.52A(i)CMOS has the largest fan-out(ii)CMOS has the lowest power consumption.

Ans.53Bfigure

Ans.54BFigure of merit (pJ)= Propagation delay time (ns) Power dissipation (mW)

Ans.55BAns.56BAns.57AAns.58*

The correct sequence isA B C D

5 4 1 2

Ans.59CAns.60AAns.61A

ECL gate operates in active and cut off region. The switching speed ECL gate is very highbecause it does not enter in saturation and thus the propagation delay is reduced.

Ans.62CAns.63CAns.64AAns.65CAns.66DAns.67BAns.68AAns.69CAns.70DAns.71C

A. HTL - High noise immunityB. CMOS - High fan-outC. 2 - Lowest product of power and delayD.

ECL - Highest speed of operation


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Ans.72BCMOS - Lower power consumption

Ans.73A2 - Multiple collectors.

Ans.74DTotem pole refers to the output buffer.Ans.75D

CMOS has high input impedance and low output impedance.

Ans.76DECL is fastest among all logic families.

PMOS slowest among all logic families then NMOS then CMOS.MOS devices are slower then BJT.

Ans.77AAns.78A

=Which is NAND Gate

Ans.79ATTL has = 10 . fan out = 10ECL is fastest logic family i.e. lowest propagation delay

2uses multi-collector o/p-so due to this fan out increases.

NMOS required less silicon area compare to P-MOS

Ans.80D = ( )

= ( )

Ans.81DDirect coupled logic family suffers with current hogging problem diode transistor logic = 30 ns due tot this speed of operation is slow compare to TTL, ECL etc. bus fastcompare to RTL

ECL fastest among all logic family having = 1 RTL = 50 slow speed of operation compare to TTL, ECL, DTL etc.DTL is suitable for monolithic ICs

Ans.82BECL highest power consumingCMOS least power consuming

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Chapter 4 Digital Logic Families