Chapter 5 Basic Computer Organization and Designpds15.egloos.com/pds/200910/22/32/CA_Chap5.pdf · 2009-10-22 · Computer System Architecture. Chapter 5 Basic Computer Organization

Chapter 5 Basic Computer Chapter 5 Basic Computer Organization and DesignOrganization and Design

상명대학교

디지털미디어학부

2009년 2학기김석규

Computer System Architecture

Chapter 5 Basic Computer Organization and Design 2

55--1 Instruction Codes1 Instruction CodesA program - a set of instructions that specify the operations, operand, and the sequenceInstruction Cycle-

Fetch : The computer reads each instruction from memory and places it in a control register.

-

Decode : The control then interprets the binary code of the instruction-

Execution : proceeds to execute it by issuing a sequence of microoperationsInstruction code-

A group of bits that instruct the computer to perform a specific

operation-

Divided into partsOperation code-

The most basic part of instruction code-

A group of bits that define such operations as add, subtract, multiply, shift, and complement

-

Consist of at least n bits for a given 2n(or less) distinct operations-

Sometimes called a microoperation

because it specifies a set of microoperations



Stored Program Organization

Accumulator (AC)-

Computers that have a single processor register usually assign to it the name accumulator



Indirect AddressWhen the second part of the instruction specifies-

an operand –

immediate

operand-

the address of an operand –

direct address-

the address of a memory word where the address of the operation can be found –

indirect addressThe indirect address instruction needs two references to memory to fetch an operandEffective address – the address of the operand



55--2 Computer Registers2 Computer RegistersThe memory unit has a capacity of 4096 words – each word contains 16 bits

List of Registers (TABLE 5-1)Data Register (DR) 16Address Register (AR) 12-

12bits since this is the width of a memory address

Accumulator (AC) 16Instruction Register (IR) 16Program Counter (PC) 12-

Hold the address of the next instruction to be read from memory after the current instruction is executed

Temporary Register (TR) 16Input Register (INPR) 8Output Register (OUTR) 8

Basic Computer registers and memory (Figure 5-3)



Common Bus SystemThe basic computer has 8 registers, a memory unit, and a control unitPaths must be provided to transfer information from one register to another and between memory and registersA more efficient scheme for transferring information in a system with many registers is to use a common bus.





When the contents of AR or PC are applied to the 16-bit common bus, the 4 most significant bits are set to 0’sWhen AR or PC receive information from the bus, only the 12 least significant bits are transferred into the registerINPR and OUTR communicate with the 8 least significant bitsInput of AC : adder and logic circuit1)

Output of AC(16bit) : register microoperation

-

complement AC, shift AC2)

DR(16bit) : arithmetic and logic microoperations

–

add DR to AC or AND DR to AC-

Result of an addition is transferred to AC and the end carry-out of the addition is transferred to flip-flop E (extended AC bit)

3)

INPR(8bit) Register transfer using bus and operation performed in the adder and logic circuit an occur during the same clock cycleeg) DR ← AC and AC ← DR-

Placing the content of AC on the bus (with S2

S1

S0

= 100)-

Enabling the LD input of DR-

Transferring the content of DR through the adder and logic circuit int

AC-

Enabling LD input of AC



55--3 Computer Instructions3 Computer InstructionsInstruction format

The register reference instructions -

recognized by the operation code 111 with a 0 in the leftmost bit (bit 15) of the instruction-

An operation on or a test of the AC-

Remaining 12bits are used to specify the operation or test

Input-output instruction-

Does not need to reference to memory-

Remaining 12bits are used to specify the type of I/O operation





Instruction Set CompletenessThe set of instructions are said to be complete if the computer includes a sufficient number of instructions in each of the following categories:1.

Arithmetic, logical, and shift instructions-

ADD, CMA (Complement AC), INC (increment AC)-

CIR, CIL-

AND, CMA, CLA (clear AC)2.

Instructions for moving information to and from memory and processor registers-

LDA (Load AC), STA (Store AC)3.

Program control instructions together with instructions that check status conditions-

BUN (Branch Unconditional), BSA (Branch and Save return address), ISZ (Increment and skip if zero) with 4 skip instructions (SPA, SNA, SZA, SZE)

4.

Input and output instructions-

INP, OUT



55--4 Timing and Control4 Timing and ControlClock pulses

The timing for all registers in the basic computer is controlled by a master clock generatorThe clock pulses do not change the state of register unless the register is enabled by a control signalThe control signals are generated in the control unit

2 major types of control organizationHardwired control-

The control logic is implemented with gates, flip-flops, decoders, and other digital circuits-

Fast mode of operation

Microprogrammed control-

The control information is stored in a control memory-

Easy to change



Control unit of basic computer



Timing signalsThe sequence counter SC can be incremented or cleared synchronously

eg) D3

T4

: SC ←

0①

D3

becomes active②

D3

T4

becomes active③

This signal is applied to the CLR

④

On T4

, SC is cleared to 0⑤

T0

becomes active instead of T5

Relation between the clock transition and timing signaleg) T0

: AR ←

PC-

During the time T0

is active, PC is loaded onto the bus and LD of AR is enabled. The actual transfer occurs at the end of the clock cycle when clock goes through a positive transition



55--5 Instruction Cycle5 Instruction CycleInstruction Cycle

1.

Fetch an instruction from memory2.

Decode the instruction

3.

Read the effective address from memory if the instruction has an indirect address

4.

Execute the instructionThis process continues indefinitely unless HALT instruction is encountered

Fetch and decodeInitially, PC is loaded with the address of the first instruction and SC is cleared to 0

)15( ),110( ),1412( Decode,..., :1 ],[ :

:

702

1

0

IRIIRARIRDDTPCPCARMIRT

PCART

←−←−←+←←

←



When T0=11.

Place the content of PC onto the bus by making the bus selection inputs S2S1S0 = 010

2.

Transfer the content of the bus to AR by enabling the LD input of AR

When T1=11.

Enable the read input of memory

2.

Place the content of memory onto the bus by making S2S1S0 = 111

3.

Transfer the content of the bus to IR by enabling the LD input of IR

4.

Increment PC by enabling the INR input of PC



Determine the Type of InstructionStart

SC ← 0

AR ← PC

IR ← M[AR], PC ← PC + 1

Decode operation code in IR (12-14)AR ← IR (0-11), I ← IR (15)

D7

I I

ExecuteInput-outputinstructionSC ← 0

ExecuteRegister-reference

instructionSC ← 0

AR ← M[AR] Nothing

Executememory-reference

instructionSC ← 0

T0

T1

T2

(Register or I/O) = 1 = 0 (Memory-reference)

T3 T3 T3 T3

(I/O) = 1 = 0 (register) (indirect) = 1 = 0 (direct)

ninstructio I/Oan Execute :ninstructio referenceregister a Execute :

Nothing :

][ :

37

3'

7

3'

3'

7

'

7

ITDTID

TID

ARMARITD ←



Register-Reference InstructionsUse bit 0 through 11 of the instruction code to specify one of 12 instructions-

These 12 bits are available in IR(0-11), and transferred to AR during time T2



55--6 Memory6 Memory--Reference InstructionsReference InstructionsAND to AC

ADD to AC

LDA: Load to AC

STA: Store AC

BUN: Branch Unconditionally

0 , :][ :

50

40

←∧←←

SCDRACACTDARMDRTD

0 ,CE , :][ :

out51

41

←←+←←

SCDRACACTDARMDRTD

0 , :][ :

52

42

←←←

SCDRACTDARMDRTD

0 ,][ :43 ←← SCACARMTD

0 ,C :44 ←← SCARPTD



BSA: Branch and Save Return AddressSubroutine or procedure call

0 , :1 ,][ :

55

45

←←+←←

SCARPCTDARARPCARMTD



ISZ: Increment and Skip if Zero

0 ),1( then )0( if ,][ :1 :

][ :

66

56

46

←+←=←+←

←

SCPCPCDRDRARMTDDRDRTD

ARMDRTD





55--7 Input7 Input--Output and InterruptsOutput and InterruptsI/O Configuration

FGI : control flip-flop-

1 bit input flag-

The flag is needed to synchronize the timing rate between the input device and the computer

-

Initially, FGI is set to 0•

When a new information is shifted into INPR, FGI is set to 1

•

When the information in INPR is transferred in parallel into AC, FGI is cleared to 0

FGO : output flag-

Initially, FGO is set to 1•

When a new information is transferred from AC to OUTR, FGO is cleared to 0

•

When the information in OUTR is transferred to output device, FGO is set to 1 again

INPR-

consists of 8 bits and holds an alphanumeric input information



I/O Instructions



Program InterruptProgrammed control transfer-

The difference of information flow rate between the computer and that of the I/O device makes this type of transfer inefficient

Consider a computer that can go through an instruction cycle in 1μs-

The I/O device can transfer information at maximum rate of 10 character per second ≡

one character every 100,000 μs

-

2 instructions are executed when the computer checks the flag bit and decides not to transfer

at the maximum rate, the computer will check the flag 50,000 times between each transfer

Computer is wasting time



Alternative to the programmed controlled procedure is to let the external device inform the computer when it is ready for the transfer uses the interrupt facilityWhile the computer is running a program, it does not check the flags-

When a flag is set, the computer is momentarily interrupted from proceeding with the current program and is informed of the fact that a flag has been set-

The computer deviates momentarily from what it is doing to take care of the input or output transfer-

It then returns to the current program to continue what it was doing before the interrupt



Interrupt flip-flop R-

When R = 0, the computer goes through an instruction cycle-

If R = 1, it goes through an interrupt cycle



Interrupt cycleHardware implementation of a branch and save return address operation

eg)



The condition for setting R = 1

This procedure can be done with the following sequence of microoperations

Modified fetch phase -

fetch and decode phase use the three control signals R’T0 , R’T1 , R’T2 instead of T0 , T1 , T2 (Figure. 5-9)

1 :))(('2'

1'

0 ←+ RFGOFGIIENTTT

0 ,0 ,0IEN ,1C :0 ,]M[A :

,0 :

2

1

0

←←←+←←←

←←

SCRPCPRTPCTRRRTPCTRARRT



55--8 Complete Computer Description8 Complete Computer Description

Table 5-6

Control Functions and Microoperations

for

the Basic Computer



55--9 Design of Basic Computer9 Design of Basic ComputerThe basic computer consists of the following components

1.

A memory unit with 4096 words of 16 bits each2.

Nine registers : AR, PC, DR, AC, IR, TR, OUTR, INPR, SC

3.

Seven flip-flops : I, S, E, R, IEN, FGI, and FGO4.

Two decoders: a 3x8 operation decoder and 4x16 timing decoder

5.

A 16-bit common bus6.

Control logic gates

7.

Adder and logic circuit connected to the input of AC



Control Logic GatesThe output of the control logic circuit-

Signals to control the inputs of the nine registers-

Signals to control the read and write inputs of memory-

Signals to set, clear, or complement the flip-flops-

Signals for S2

, S1

, and S0

to select a register for the bus-

Signals to control the AC adder and logic circuit



Control of Registers and MemoryStatements that changes the content of AR

1 :0 :

][ :)110( :'

:'

45

0

3'7

2

0

+←←←

−←←

ARARTDARRT

ARMARITDIRARTRPCARTR

45

0

3'720

)(INR)(CLR

:'')(LD

TDARRTAR

ITDTRTRAR

==

++=



Read control? ← M[AR]

462103'71 )('Read TDDDDITDTR +++++=

][ :][ :][ :][ :][ :

][ :'

46

42

41

40

3'7

1

ARMDRTDARMDRTDARMDRTDARMDRTDARMARITD

ARMIRTR

←←←←←

←



Control of Single Flip-flopseg) IEN

Figure 5-17 Control inputs for IEN

37

6

7

ere wh0 :1 :

ITDpIENpBIENpB

=←←

0 :2 ←IENRT



Control of Common Bus

76542

76321

75310

encoder for the functionsBoolean

xxxxSxxxxSxxxxS

+++=+++=+++=



To determine the logic for each encoder input, it is necessary to find the control functions that place the corresponding registeronto the buseg) To find the logic that makes x1

=1, find all the register transfer statements that have AR as a source

eg) the data output from memory are selected for the bus when x7

=1 and S2

S1

S0

=111 same as memory read operation

ARPCTDTDTDxARPTD

←+=⇒←

: C :

55

554444 1

462103'71 )('7 TDDDDITDTRx +++++=



55--10 Design of Accumulator Logic10 Design of Accumulator Logic



Control of AC Register



Adder and Logic Circuit

Documents

Chapter 5 Basic Computer Organization and Designpds15.egloos.com/pds/200910/22/32/CA_Chap5.pdf · 2009-10-22 · Computer System Architecture. Chapter 5 Basic Computer Organization