CHƯƠNG 2_VHDL

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CHNG 2

NGN NG M T PHN CNG VHDL

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Cu trc ca mt chng trnh VHDL

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Cu trc ca mt chng trnh VHDL

Ngoi cc khi trn trong 1 thit k VHDLcn c th c cha thm cc khi:

Configuration

Package

Package Body

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ngha ca cc khi

Entity m t external interfaceca thc thc thit k, cng cc thuc tnh lin quanvi interface.

Architecture m t hot ng bn trongca thc th (entity) gn vi n

Mtpackage declarationc dng khai

bo cc d liu dng cho ton b thit k,bao gm:Constants, data types, subtypes,subprogram v function declarations, v.v

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ngha ca cc khi

Mtpackage bodyl mt dependentunitca mtpackage, n cha ccthng tin chi tit v cc i tng trong

package. Th vin l mt tp hp cc n v thit

k (design unit) c kim chng

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Khai bo thvin

Khai bo th vin phi c t u tintrong mi thit k VHDL.

C php:

Library Tn th vin; use Danh sch cc gi trong th vin; V d:

Library IEEE; use IEEE.std_logic_1164.all;

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Mt sgi trong thvin IEEE

Gi IEEE.STD_LOGIC_1164 cung cp cckiu d liu std_ulogic, std_logic,std_ulogic_vector, std_logic_vector, cc hm

logic and, or, not, nor, xor Gi IEEE.STD_LOGIC_ARITH nh ngha

cc kiu d liu s nguyn v cc phpton trn cc kiu d liu ny.

Gi IEEE.NUMERIC_BIT Cung cp cc hms hc logic lm vic vi cc kiu d liusigned, unsigned c l chui ca cc BIT.

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M tthc th(entity)

Khai bo ENTITY dng m t giao tipbn ngoi ca mt phn t.

C php:

Entity entity_nameis

[generic (generic_declaration);]

[port (port_declaration);]

end [entity_name];

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Khai bo Generic

L khai bo cc tham s tnh (hay cc hng s)c s dng trong thit k

C php:

generic ( constant_name: type [:=init_value]);

Trong :

Type: kiu hng

Init_value: gi tr ca hng

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Khai bo cng (port)

Khai bo tt c cc cng giao tip trong thitk.

C php:

Port ( port_name: [mode] type [:= init_value] ; port_name:[mode] type [:=init_value]);

Trong :

Mode: ch hng vo ra ca cng Type: kiu d liu ca cng Init_value: gi tr khi to ca cng

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Cc mode sdng trong khai bo cng

In: cng vo

Out: cng ra

Inout: cng 2 hng, c th l cng vo cngc th l cng ra

Buffer: l cng m c th c s dngnh tin hiu bn trong cng c th c s

dng nh cng out

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Bi tp Hy khai bo entity cho cc mch sau: 1. B cng y 2. b cng n bt ( n

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Architecture

Architecture m t hot ng bn trong cathit k.

C 3 kiu architecture:

Behavioral: kiu m t hnh vi

Dataflow : kiu lung d liu

Structure : kiu cu trc

Ty thuc vo mi thit k c th chn cc kiuarchitecture khc nhau.

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Architecture theo m hnh dataflow

C php:

ARCHITECTURE architecture-name OF entity-name IS

signal-declarations; -- khai bo tn hiuBEGIN

concurrent-statements; -- cc cu lnh ng thiEND architecture-name;

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Nhng cu lnh ng thi theo cu trc Dataflow :

Cu lnh Concurrent s dng cho m hnhDataflow c thi hnh mt cch ng thi.

c s dng m t cc kt ni gia

cc khi thit k, m t cc khi thit kthng qua cch thc lm vic ca n.

Cc pht biu ng thi c thc hin

song song c lp vi nhau.

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Nhng cu lnh ng thi theo cu trcDataflow

Php gn tn hiu ng thi

C php:

Signal

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Php gn tn hiu kiu vector

Php gn tn hiu cng c p dng cho kiuvector:

V d

SIGNAL x: STD_LOGIC_VECTOR(7 DOWNTO 0);x

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V d: Thit kmch cng y library IEEE;

use IEEE.STD_LOGIC_1164.all;

entity FA is

port(

A : in STD_LOGIC;

B : in STD_LOGIC;

Cin : in STD_LOGIC;

S : out STD_LOGIC; Cout : out STD_LOGIC

);

end FA;

architecture FA_dataflow of FA is

begin

S

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Bi tp

1. Thit k mch tr y

2. Thit k mch nhn

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Gn tn hiu c iu kin

Tn hiu c gn chn mt trong nhiu gitr ty thuc vo iu kin

C php:

signal

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V d: thit kmch mux 4-1 library IEEE;


entity Mux4_1 is port(

A : in STD_LOGIC;

B : in STD_LOGIC;

X : in STD_LOGIC_VECTOR(3 downto 0);

Y : out STD_LOGIC

); end Mux4_1;

architecture mux4_1_dataflow of Mux4_1 is

signal s:std_logic_vector(1 downto 0);

begin

s

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Bi tp

Thit k mch so snh 2 s 1 bt

Thit k mch kim tra chn l ca chui tnhiu 8 bt

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Php gn tn hiu la chn

Cc gi tr khc nhau c gn ph thucvo mt iu kin no

C php:

WITH biu thc SELECT signal

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V d: thit kmch mux 4-1 library IEEE;


entity Mux4_1 is port(

A : in STD_LOGIC;

B : in STD_LOGIC;

X : out STD_LOGIC_VECTOR(3 downto 0);

Y : in STD_LOGIC

);

end Mux4_1; architecture mux4_1_dataflow of Mux4_1 is

signal s:std_logic_vector(1 downto 0);

begin

s

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Bi tp

1. Thit k mch m ha thp phn nhphn

2. Thit k mch gii m 7 on

3. Thit k mch m ha nh phn - gray 4bit

4. Thit k mch m ha nh phn4 bit -jonhson

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Nhng cu lnh theo kin trc behavior

Kiu kin trc behavior c vit ging nhlp trnh tun t.

Tt c cc lnh tun t c t trongprocess.

Bn thn process l mt lnh ng thi.

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Cu lnh process

C php:

Tn_process: PROCESS (danh sch tn hiu nhy)

khai bo bin cc b; BEGIN

cc cu lnh tun t;

END PROCESS tn_process;

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Cu lnh process

Danh sch tn hiu nhy l cc tn hiu u vo catin trnh.

Cc tn hiu nhy c phn tch nhau bi du ,

Cc cu lnh trong process c thc hin theotrnh t t trn xung cho n khi ht process vc tip tc thc hin li khi c t nht 1 tn hiutrong danh sch tn hiu nhy thay i.

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Php gn tn hiu

C php:

tn_signal

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Php gn tn hiu c tr

C php:

Php gn ny khng c thc thi ngay mphi i 1 khong thi gian tr.

C 2 loi tr:

Transport Delay.

Inertial Delay.

Tn_signal

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Transport Delay

Cn gi L l tr truyn dn, l khong thigian cho vic thc hin 1 cng vic no .

V d:

S

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Inertial Delay

Cn c gi l tr qun tnh. L khongthi gian thit b khng c phn ng vi uvo.

Tr ny c mc nh trong VHDL. V d:

S

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Php gn bin

t cho bin mt gi tr no .

C php:

Tn_bin := biu thc;

V d:

X := 1

Y := not x;

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Cu lnh if

Dng la chn thc hin 1 trong nhiu lnhc lit k ty thuc vo iu kin.

C php:

If iu_kin then cu lnh1 ;

Else

cu lnh2;

End if;

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Cu lnh if

If iu_kin1 then

cu lnh1 ;

Elsif iu_kin 2 then

cu lnh2; .

Else

Cu lnh n; End if;

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V d: thit kmch demux 1-4

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Bi tp

Thit k mch cng v tr y : c 1ng la chn php ton cng hoc tr.

Thit k b gii m 3 ng vo 8 ng ra.

Thit k b m ha 8 vo 3 ra.

Thit k mch 3 trng thi

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Gi : bng chn l bgii m 138

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Gi : bng chn l bm ha 138

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Cu lnh case

C php:

CASE biu_thc ISWHEN la chn 1 => lnh 1;WHEN la_chn 2 => lnh 2;WHEN OTHERS => lnh n;END CASE;

Ty thuc vo kt qu ca biu thc bng la chn no

th cu lnh tng ng s c thc hin. Nu kt quca biu thc khng bng la chn no th cu lnh sauwhen others c thc hin

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V dThit kmch gii m 7 on

B3 B2 B1 B0 a b c d e f g

0 0 0 0 1 1 1 1 1 1 0

0 0 0 1 0 1 1 0 0 0 0

0 0 1 0 1 1 0 1 1 0 1

0 0 1 1 1 1 1 1 0 0 1

0 1 0 0 0 1 1 0 0 1 1

0 1 0 1 1 0 1 1 0 1 1

0 1 1 0 1 0 1 1 1 1 1

0 1 1 1 1 1 1 0 0 0 0

1 0 0 0 1 1 1 1 1 1 1

1 0 0 1 1 1 1 1 0 1 1

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Cu lnh wait

C php:

WAIT UNTIL iu_kin;

Cu lnh tip theo ch c thc hin khiiu kin c tha mn

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V d: thit kD- flip flop

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Bi tp

Thit k RS flip flop

Thit k T flip flop

Thit k JK flip flop

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Cu lnh for

C php:

Sau mi ln cu lnh thc hin bin chyc cng thm 1 n v

FOR tn_bin IN gi tr u TO [ DOWNTO] gi tr cui LOOPcu lnh cn lp;

END LOOP;

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V d: thit kmch kim tra chn l8 bt

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Bi tp

m s cc bt 0 lin nhau trong mt chuid liu 16 bt

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Cu lnh while

C php:

While iu_kin loop

cu lnh cn lp;

End loop;

Hot ng: cu lnh c thc hin lp i lpli trong trng hp iu kin ng

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Cu lnh loop

C php:

Loop

cu lnh cn lp;

exit when iu_kin;

End loop;

Cu lnh c lp i lp li nu iu kin saiv dng li khi iu kin ng

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Function (hm)

Khai bo hm:Function tn_hm(danh sch cc i s) return kiu_hm;

Ni dung hm:Function tn_hm(danh sch cc i s) return kiu_hm is

begincc cu lnh;

End tn_hm;

Gi hm:

Tn_hm(danh sch cc tham s thc);Ch : cc i s ch l tn hiu hoc thucmode in

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Procedure (th tc) Khai bo:

Procedure tn_th_tc(danh sch i s);

Cu trc th tc:

Procedure tn_th_ tc(danh sch i s) is

Begin

cc cu lnh;

End tn_th_tc;

Ch : cc i s ch thuc mode in,out, inout Li gi:

Tn_th_tuc(danh sch tham s thc);

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Bi tp Thit k b m thun k = 16

Thit k b m nghch k = 32 Thit k b m thun nghch k = 16 c t

c gi tr ban u.

Thit k b ghi dch 4 bt vo ni tip ra songsong

Thit k b ghi dch 8 bt vo song song ra songsong

Thit k b ghi dch 8 bt vo song song ra nitip

Thit k b ghi dch 8 bt vo ni tip ra ni tip

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My trng thi hu hn FSM

Cc mch logic: Mch t hp

Mch dy

Mch dy hot ng thng qua mt dy cctrng thi hu hn do n c xem nhmt my trng thi hu hn (FSM)

h l

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Phn loi FSM

My trng thi hu hn c phn thnh 2loi: Moore FSM : l my trng thi c gi tr ca u

ra ch ph thuc vo trng thi hin ti m khngph thuc vo gi tr u vo.

Mealy FSM: l my trng thi c gi tr ca u rakhng ch ph thuc vo trng thi hin ti m

cn ph thuc vo gi tr u vo.

M h h hi h h M

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M hnh my trng thi hu hn Moore

M h h hi h h M l

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M hnh my trng thi hu hn Mealy

h h h

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Phn tch mch tun t

Vit cc phng trnh kch

Vit cc phng trnh trng thi

Lp bng trng thi

Vit phng trnh u ra

Lp bng cho u ra

V gin trng thi.

Ph h h

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Phn tch mch tun t

Phng trnh kch: l cc phng trnh logicbiu din trng thi k tip trong FSM.

Thc cht y l cc phng trnh biu din

cc u vo ca flip flop.

Ph h h

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Phn tch mch tun t

Phng trinh trng thi: biu din trng thik tip ca flip flop, n ph thuc vo : trng thi hin ti ca flip flop.

Hnh vi, chc nng ca flip flop Cc u vo ca flip flop

Ph h h

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Phn tch mch tun t

Bng trng thi: c suy ra t cc phngtrnh trng thi, l bng lit k cc trng thica FSM.

Gin trng thi: l th m t hot ngca FSM, mi nt trong th biu din 1trng thi ca FSM

Ph t h t thi i

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Phn tch my trng thi moore n gin

Ph t h t thi i

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Phng trnh kch:

Phng trnh trng thi:

Ph t h t thi i

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Bng trng thi:

Ph t h t thi i

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Phng trnh u ra:

Bng u ra:

Phn tch my tr ng thi moore n gin

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hnh trng thi

Ph h FSM M l

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Phn tch FSM Mealy

Ph h FSM M l

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Phn tch FSM Mealy

Bng u ra:

Ph t h FSM M l

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Phn tch FSM Mealy

hnh trng thi:

T h h t t

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Tng hp mch tun t

Lp gin trng thi.

Lp bng trng thi.

Lp bng u ra.

Vit cc phng trnh kch.

Vit phng trnh u ra.

V s mch.

Lp m VHDL cho FSM

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Lp m VHDL cho FSM

Khai bo cc trng thi.

Vit process cho cc trng thi.

Vit process cho u ra.

Cc cu lnh kiu Structural

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Cc cu lnh kiu Structural

Cu trc ny cho php lin kt cc thnhphn hoc cc khi logic vi nhau.

Cc thnh phn hoc cc khi logic s dng

kin trc phi c khai bo nh cccomponent trong phn architecture nhngni dung ca chng c th c vit trongcng 1 file hoc khc file

Khai bo Component :

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Khai bo Component :

C php

COMPONENT tn_component IS

PORT (danh sch cc cng);

END COMPONENT;

Cu lnh port map

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Cu lnh port map

C php:

Cu lnh ny c nhim v ch ra cch lin ktcc thnh phn hay cc khi vi nhau

tn_nhn: tn_component PORT MAP

(danh sch cc port);

Cu lnh Generate

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Cu lnh Generate

Cu lnh ny cho php sao chp cc linhkin ging nhau.

C php:

Tn_nhn: for tn_bin in ch_s_u to[downto ] ch_s_cui generate

Cu lnh port map;

End generate tn_nhn;

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CHƯƠNG 2_VHDL