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Combinational Logic
Discussion D2.5
Combinational Logic
CombinationalLogicinputs outputs
Outputs depend only on the current inputs
Sample Combinational Circuit
11
From circuit to truth table
From truth table to circuit
No reduction With reduction
a b c x y
0 0 0 1 0
0 0 1 0 0
0 1 0 1 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 1
1 1 0 1 0
1 1 1 0 0
Using K-maps to reduce
Direct implementation
2-variable 3-variable 4-variable
Recall… Karnaugh Maps for logic reduction
Ummmm, NO. Let the software minimize for you…
BCD 7-Segment Decoder
BCD 7-Segment Decoder – K-map for ‘a’
BCD 7-Segment Decoder
All signals:
a, b, c, d, e, f, g
Structural VHDL for the BCD to 7-seg Decoder
Structural VHDL for the BCD to 7-seg Decoder
Structural VHDL for the BCD to 7-seg Decoder
DECLARING THE COMPONENTS THAT YOU WILL USE
Structural VHDL for the BCD to 7-seg Decoder
WIRE IT UP
Structural VHDL for the BCD to 7-seg Decoder
OR… AN EASIER WAY USING GATES FROM THE 1164 STANDARD LIBRARY (STILL STRUCTURAL)
Structural VHDL for the BCD to 7-seg Decoder
OR… EVEN EASIER YET A BEHAVIORAL DESCRIPTION