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Combinational Logic
Prof. MacDonald
2 Input NOR – depletion NFET load
l Pull Down Network can pull OUT down if either or both inputs are above Vih – consequently the NOR function.
l Depletion NFET could really be any load.
Vdd
A B
Out
2 Input NOR – depletion NFET load
l If both A and B are low (<VIL) – load charges OUT high
Vdd
A B
Out
Parallel Transistor Configurations
l Two same-type transistors in parallel have their transconductances added if on at same time.
l If both transistors are on simultaneously and the L values are the same for both, we can add the widths to get an effective single transistor equivalent.
l When both are on, (W/L)eq is sum of all ratios
8/1 8/1
16/1
Series Transistor Configurations
(W/L)eq = (W/L)a + (W/L)b or if Ls equal, simply add Ws
W
L
W
L
W
L
Series Transistor Configurations
l Two same-type transistors in series have their resistances added if on at same time.
l If both transistors are on simultaneously and the W values are the same for both, we can add the lengths to get an effective single transistor equivalent.
8/1
8/2 = 4/1
8/1
Series Transistor Configurations
(W/L)eq = 1 / (sum of reciprocals) or if Ws are equal, simply add Ls
W
L W
L
2 Input NOR – depletion NFET load
If both A and B is high– NFET heavy inverter
Vdd
A B
Out
Noise Margins
Voh = Vdd Vol depends on which driver(s) is on – worst-case? Vih and Vil calculated as inverter
Vdd
A B
Out
Power
Worst-case is A and B high. Idload = Ida + Idb for static power Dynamic power (charging/discharging cap) the same for all cases.
Vdd
A B
Out
Generalized Depletion NOR
Can increase inputs to any value (theoretically). What is the limit?
Vdd
A B
Out
C
2 Input Depletion NAND
Only when both transistors (A and B) are on will the output be driven low – out = !(A & B)
Vdd
B
A
2 Input Depletion NAND
Since transistors are in series, the equivalent pull down transistor (assuming the two are the same) is (W/2L).
Vdd
B
A
Depletion NANDs and body effect
Consider the case where B is held on, but the gate of A transitions from low to high. The intermediate node will be at a non-zero value at the beginning. Vbs != 0.
Vdd
B
A intermediate node
Depletion NANDs and diffusion cap
Consider the case where B is held on, but the gate of A transitions from low to high. The intermediate node will be at a non-zero value at the beginning. Vbs != 0.
Vdd
B
A diffusion cap may or may not already be charged when output transitions from high to low. This varies delay.
Generalized Depletion NANDs
Can have more than two inputs – but cap and body effect get worse. Vdd
C
B
A
CMOS NANDS and NOR
Consider transistor sizings for balanced circuits…
out
A
A
B
B
out A
A
B
B
NAND Layout
n-well
A
vdd
B
gnd
OUT
active area
metal 1
poly
Legend
CMOS NOR Transistor sizing Consider transistor sizings for balanced circuits…
out
A
A
B
B out
W*4
W*4
W W W
W*2
CMOS NAND Transistor Sizing
Consider transistor sizings for balanced circuits…
out
A
A
B
B
out W
2*W
2*W
2*W
2*W 2*W
CMOS NAND Transistor Sizing
Consider transistor sizings for balanced circuits…
out
A
A
C
C
out W
2*W
3*W
3*W
3*W
B
B
Fanin (number of inputs)
There is a limit to the number of inputs that can be used.
A
A
B
B
C D E
C
D
E
Fanout (number and/or size of loads) There is a limit to the number of gates that can be driven.
Fanout (number and/or size of loads) Small gates (widths) struggle to drive large gates due to
capacitance. Typically, synthesis limits the fanout to 20 or less.
NAND VTC
Vout
Vin
out
A
A
B
B
One input only
Inverter
Both inputs
Complex CMOS Logic
Can make single stage gates that implement: AND-OR-Inverter (AOI) OR-AND-Inverter (OAI)
Given a function F = ((A*B)+C)’ Invert the function to get N network
F’ = (A*B)+C Take dual of N network equation to get PFET network
F’d = (A’+B’)*C’ Remember that PFETs invert inputs naturally
Conversion to NAND-NAND logic
f = abc’ + ab’c + acd AND – OR logic
(f’)’ = ((abc’ + ab’c + acd)’)’ Double inversion
f = ((abc’)’(ab’c)’(acd)’)’ NAND - NAND
NAND-NAND Conversion
f = abc’ + ab’c + acd f = ((abc’)’(ab’c)’(acd)’)’
Conversion to NOR-NOR logic
f = (a+b+c’)(a+b’+c)(a+c+d) OR-AND logic
(f’)’ = (((a+b+c’)(a+b’+c)(a+c+d))’)’ Double inversion
f = ((a+b+c’)’+(a+b’+c)’+(a+c+d)’)’ NOR-NOR
NOR-NOR Conversion
(a+b+c’)(a+b’+c)(a+c+d) ((a+b+c’)’+(a+b’+c)’+(a+c+d)’)’
Multi-level Conversion to NAND
1 2 3 4 5
a
a’
b
b
c
c’
d
d
e
e’
Alternative Gate Symbols
( A * B) ’ A’ + B’
( A + B) ’ A’ * B’
Alternative Gate Symbols
( A’ * B’) ’ A + B
( A’ + B’) ’ A * B
Bubble conversion
g f
e d
c
b
a
Bubble conversion - step one
g f
e d
c
b
a
Invert OR gate inputs (converting to NAND) Invert AND gate outputs (converting to NAND)
Bubble conversion - step two
g’ f’
e d
c’
b
a’
Ensure all inversions come in pairs (canceling each other out) (i.e. invert input literals or add inverters)
Bubble conversion - step three
g’ f’
e d
c’
b
a’
Replace all Inverted-input OR gates with NAND gates
Complex CMOS Logic
out
A
A
B
B
C
C
out
PFET network
NFET network
A B C
A B C
Complex CMOS - Equivalent Inverter
out
A
A
B
B
C
C
For pull down, the equivalent pull down strength (W/L ratio) has three cases: A and B on – W/Leq = 1 / (1/(W/La) + 1/(W/Lb) C only – W/Lc
or all three W/Leq = W/Lc + 1 / (1/(W/La) + 1/(W/Lb)
Complex CMOS Logic - Euler
C
B
A
C
B A
NFET network PFET network
Find common Euler path which does not traverse any branch more than once.
out
A
A
B
B
C
C
Complex CMOS Logic
Given a function F = ((A*B)+C)’ what is best layout to share diffusions when possible. One solution but not best Vdd
Gnd
out
A B C
nwell active area
active area in pwell
Complex CMOS Logic
Given a function F = ((A*B)+C)’ what is best layout to share diffusions when possible. Switch S/D of C for better. Vdd
Gnd
out
A B C
Pass Gates
In most static CMOS, a PFET network pulls high and a dual NFET network pulls low.
In a pass gate configuration, they tie inputs to outputs. Pass gates can either be “ON” and pass a value or be “OFF” and tri-state an output.
One NFET can do this, but passes high values poorly. One PFET can do this too, but passes low values poorly.
in out
enable
Pass Gates
Couple of problems, not only will it not drive a full logic high, the effective R skyrockets to infinity as you approach Vdd-Vt. This means that it also slows down as well as and provides no drive strength when statically high, thus the
output is susceptible to coupling noise.
in out
enable
Charge Sharing (and Pass Gates)
Common interview question… Basis for DRAM operation. At t=0, the gate is low, C1 (50 fF) is charged to 2 volts, C2 (25 fF) is charged to 3 volts. Later, the gate is turned on. What is voltage of C1 and C2? Simple Eng101, but most grads can’t do it.
C1 C2
gate
v1 v2
Complementary Transmission Gates
Use a PFET and NFET in parallel, passes ones and zeros. Never used by logic designers, circuit designers hide them. TGs act as switches, either providing a resistive short or an open circuit. Does not provide drive, attenuating the signal. Susceptible to “above Vdd” or “below Gnd” noise at input.
Noise problems with TGs
Consider the case where the TG is off, but the input is capacitively coupled down from 0 to – 2*Vt.
Then Vgs > Vt and the NFET will turn on momentarily. Consider the case where the TG is off, but the input is
capacitively coupled up from Vdd to Vdd + 2*Vt. Then Vgs > Vt and the PFET will turn on momentarily. Morale of the story, never let a global signal drive a source,
only the transistor gate.
Effective Resistance of TGs
For passing low values, the NFET is fully on. For passing high values, the PFET is fully on. The effective resistance stays relatively constant regardless of the input voltage (as opposed to how pass gates respond).
Reff
Vin
Vt Vdd-Vt
Vdd
NFET R
PFET R
Combination
Textbook Transmission Gate Mux
d1
d0
s
out
Referred to as “soft node” Usually limited to 5 or 6 TGs.
Real Transmission Gate Mux
d1
d0
s
out
Need input inverters for noise and output inverter to cancel inversion and provide drive strength
TG Logic
Implements F = A*B + C
c’
c
c
b
b’
b’
f a
NFET Pass Gate Logic
Implements F = A^B b’ b
a
a’
f
Couple of major problems though: 1) really needs 4 transistors to get both complements, 2) if F is high, you’ll have a Vt drop (slow and consumes power) 3) inputs are unbuffered to source (noise).
CPL Logic
Implements F = A^B
b’ b
b
b’
a
a’
a
a’
f’
f f’
f
Full Adder Cell
l Very common circuit in processors l Slow and large (compared to NANDs) l Complete macro cell
– adds two 1 bit numbers – provides 1 bit sum and carry out
l Many can be connected together S = A^B^C Cout = AB + BC + AC
A B Cin S Cout 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1
Full Adder Cell
A B Cin S Cout 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1
S A B Cin
Cout
Ripple Carry Adder
full adder
a b
s
cin cout
full adder
a b
s
cin cout
full adder
a b
s
cin cout
full adder
a b
s
cin cout
A[3:0] B[3:0]
4
4
Sum[4:0]
0
5
Adder/Subtracter
full adder
a b
s
cin cout
full adder
a b
s
cin cout
full adder
a b
s
cin cout
full adder
a b
s
cin cout
A[3:0] B[3:0]
4
4
Sum[4:0]
5
subtract
Standard CMOS Full Adder
Full Standard CMOS Adder 40 transistors – 20 PFETs / 20 NFET Delay Robust (even at low Vdd), Good Noise Immunity
I3
I9 I10
I4
I7 I8
I6
I5
I1 I2
I12
I19 I20
I14
I17 I18
I16
I15
I11 I13
I25 I26
I29 I30
I28
I27
I23
I22
I24
I21 I33
I34
Cout
I31
I32 Sum
A
B
Cin
A
B
BN B
AN
A
Cin
B
BN
A
CinN
SumN CoutN
Transmission Gate Adder
Standard Transmission Gate Adder 26 transistors - 13 PFET / 13 NFET
I17
I18
I15
I16
I13 I14
I11
I12
I9
I10 Sum
Cout
I3 I4
I1
I2
I7 I8
I5
I6
I21
I22
I19
I20
I25
I26
I23
I24
A
B
Cin
Complementary Pass Gate Logic
Swing Restoring CPL Adder 32 transistors – 8 PFETs / 24 NFETs improved leakage over straight CPL
I13
I14 I32
I31
I1
I2
A
AN I3
I4
B BN
I5 I6
Cin
CinN I7
I8
I11
I12
SumN
I9
I10
Sum
I15
I16
B
BN I17
I18
AN CinN
I21 I22
A
AN I23
I24
I17
I18 B
BN I19 I20
I27
I28
Cout
I25
I26
CoutN
Cin A AN CinN Cin A
LEAN Adder
Single Ended Pass Logic (LEAN) Adder 22 transistors - 5 PFETs / 17 NFETs highest density
I7
I4
B
I3 I11
Cin
I5
I6
I17
I19
I20
Sum
I8
I12
A
I1
I2 I9
I13
I18
I21
I22
Cout
I10
I14
I15 I16
