Communications Aspect OfThe Wildforce Board

Chatchai Khunpitiluck

RATS : November 22nd, 1999

212/3/99

Outline

� Motivation

� Wildforce board– Specification

– Communication features

� Communications– Fault injection

– Fault tolerance

� On-going work– Soft microprocessor

� Summary

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Motivation

� ROAR

� Real design in hardware– Verify proof of concept

– Explore reconfiguration techniques

– Test fault detection mechanisms

– Real fault can be implemented

412/3/99

Wildforce Board

� Components– 5 of 4036XLA FPGAs

– A crossbar

– 5 MB of memory

512/3/99

Communications

CPE0

PE1 PE2 PE3 PE4

CROSSBAR

� Host computer - Wildforce Board

� PE - PE

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Host - Board Communications

� Fifo

� Memory

CPE0

PE1 PE2 PE3 PE4

CROSSBAR

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PE - PE Communications

� Crossbar [6x36b bi-dir]

� Systolic bus [3x36b bi-dir]

� Handshake signal bus [8x1b bi-dir]

� Additional handshake signal bus [2x8b bi-dir]

CROSSBARCPE0

PE1 PE2 PE3 PE4

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Fault Injection

� Physical design– Not fault-free

– Permanent fault

– Temporary fault

– Concurrent with program execution

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Fault Injection

� Memory fault– Bit values read does not match bit values

previously written

� To simulate memory fault– Application does normal operation

– Another application accesses the memoryand modifies bits

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Fault Injection : Idea

� A: normal operation

� B: fault injection

Memory Entries 32 bits

A: Stores

B: flips bits

A: ...A: Reads

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Fault Injection

� Parameters– Fault pattern is a f(address, data)

– Probability of an address to apply fault pattern

� Permanent Fault– Probability of a memory not fault-free = 100%

– Fault function:� f(a,d) = d | 0x0004 bit[2] stuck-at 1

� f(a,d) = if (a is in range) return (d & 0xff7f);addresses in range are faulty

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Fault Injection : Application

� A: memdiag.exe

� B: faulty.exe

A

B

A

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Fault Tolerance

� Fault can be masked if appropriateredundancy is incorporated into thesystem

� Redundancies [Wicks 91]– Information redundancy

– Time redundancy

– Software redundancy

– Hardware redundancy

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Fault tolerance : TMR

� Triple Modular Redundancy (TMR)– Hardware redundancy

– 3 Modules

– 1 Voter

� Wildforce limitations– Size of design

– Size of information to be voted

– Communications among PEs

1512/3/99

TMR Implementation

� Output of each module = 8 bits

� Can place the voter anywhere

PE1 PE2 PE3 PE4

CPE0CROSSBAR

36-bit buses

8-bit buses

1 2 3 V

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TMR Implementation

� Output of each module = 16 bits

� Can place the voter anywhere

PE1 PE2 PE3 PE4

CPE0CROSSBAR

36-bit buses

8-bit buses

1 2 3 V

1712/3/99

TMR Implementation

� Output of each module = 32 bits

� Can place the voter in PE2, PE3 only

PE1 PE2 PE3 PE4

CPE0CROSSBAR

36-bit buses

8-bit buses

1 2 V 3

1812/3/99

On-going work

� Soft Microprocessor– Motorola 2901

� Why?– Microprocessor!

– Better understanding of VHDL

– Go through design steps to obtain Xilinxconfiguration file

– Can leverage into a larger and morecomplicate design

1912/3/99

Motorola 2901

� 2901– RISC

– 4 bit

– No floating point unit

– Can be cascaded

2012/3/99

Motorola 2901

� Implementation– 8% of 4036XLA (4 bits)

– 41 MHz

2112/3/99

Summary

� Communications– enable data transfer among processing

elements

– troublesome for data wider than 36 bits

� Fault Injection– Concurrent fault injection is possible

– Can use this model in debugging designs

� Soft Microprocessor

2212/3/99

References

� [Wicks 91] Wicks, J. and Martin H., “Design of a fault-tolerant RISC Microprocessor Using VHDL,” Proceedingsof SSST, pp 354-358.