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CS305 Computer Architecture, Mid-Semester ExaminationTuesday 15 September 2009, 2-4pm, Maximum marks: 25

Instructions: READ CAREFULLY BEFORE ANSWERING

• Write answers only in the space provided. Extra rough-work sheets will be provided.

• Write your name and roll number in all the sheets.

• You are allowed to use only your own hand-written notes. Xerox copies or printed material (including books) are not allowed.

• Answer crisply and clearly; avoid lengthy answers. State any necessary assumptions made.

• Provide explanations and/or calculation steps wherever appropriate. Just stating the final answer may not fetch you any marks.

• Your handwriting should be legible and your drawings neat.

• Use a pen to answer the questions; you can use pencil (only) for the drawings.

• There are 6 questions in 8 pages.

• The appendix provides useful information: (1) SPEC2000 instruction mix, (2) MIPS multi-cycle datapath (for instruction subset), (3) FSM control for the multi-cycle implementation.

1. Short answer questions [4 x 1 = 4 marks]

(a) Why is the assembler temporary register $at needed in the MIPS architecture? Answer by giving an appropriate example from the standard MIPS instruction set.

(b) Give an example use of the kernel-reserved registers $k0-$k1 in the MIPS architecture.

(c) A C-code dynamically linked library needs to be compiled into assembly language. For procedures in this library, can the compiler decide not to save/restore some of $s0-$s7? Why or why not? Explain your answer.

(d) In the above question, suppose that the library procedures do not call any other outside procedure. For a given non-leaf library procedure, can the compiler decide not to save/restore some of $t0-$t9? Why or why not? Explain your answer.

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2. Implementing a pseudo-instruction [based on Ex-5.48, 3+1+1=5 marks]

We want the MIPS assembler to support a pseudo-instruction called bcp, which stands for block-copy. The pseudo-instruction is of the following form

bcp $t1, $t2, $t3

This instruction copies a sequence of words from one portion in memory to another. $t1 gives the starting address of the destination, $t2 gives the starting address of the source, and $t3 gives the number of words to be copied. The contents of the three registers need not be preserved at the end of the pseudo-instruction.

(a) Write the assembly code to translate this pseudo-instruction to an appropriate block of code. Your code must be as efficient as possible, and commented appropriately.

(b) For a 100-word copy, how many instructions are executed?

(c) Assuming the multi-cycle implementation as given in the appendix, what is the CPI of the above block of code, and how many cycles are needed for the 100-word copy?

3. Choices in processor design, performance analysis [based on Ex-5.47, 3+2=5 marks]

Consider 3 MIPS implementations as follows. M1 is the multi-cycle implementation as given in the appendix, and it runs with a 2 GHz clock. M2 is an implementation where the register-file write-back can be completed in the same cycle as a memory read or an ALU operation. But this comes at a penalty of having a reduced clock frequency of only 1.6 GHz. M3 is like M2, but has the additional feature that memory address computation and memory access are done in the same cycle. But M3 runs only at 1 GHz.

(a) Compare the performance of M1, M2, and M3 based on the SPEC2000 integer benchmark. Make and state appropriate assumptions for the cycle lengths of various instructions. These assumptions must be consistent with the multi-cycle implementation given in the appendix. Which is the fastest machine?

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(b) Now change the instruction mix such that the machine which was the slowest in (a) above, is now the fastest. Explain the intuition behind your answer (no marks for just giving the answer without explaining the intuition).

4. Changes in the multi-cycle implementation for M2 and M3 in Q3 above [2+3= marks]

(a) Compared to the state machine given in the appendix (for M1), how will the state machine change, for the implementation of M2? How will the state machine further change for the implementation of M3? You only have to describe/draw the change(s); no need to draw the entire new state machine.

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(b) Compared to the datapath given in the appendix (for M1), how will the datapath be different for the implementation of M2? How will the datapath further be different for the implementation of M3? Draw (only) the relevant changes, showing appropriate connections/markings.

5. Atomic compare and swap instruction [1.5+1+2+1.5=6 marks]

In the Operating Systems course, you will learn (or have already learnt) the need for atomic instructions. In this question, we are going to implement one such instruction, swpz, which stands for swap if zero. The instruction should take three register arguments, compare one of them to zero. If this compared register is zero, then the instruction should swap the values in the other two register arguments. If the compared register is not zero, this instruction has no effect.

We are going to consider adding support for swpz in the multi-cycle implementation. Answer the sub-questions below. Hint-1: the sub-questions below are all inter-related; you may have to think of the answers in parallel, rather than one at a time. Hint-2: recall that register $zero has the value zero always; you can use this to simplify your implementation.

(a) Write down the actions in the various cycles of execution of swpz.

(b) Define an appropriate format for this new instruction.

(c) Draw the changes required in the datapath (given in the appendix) to add support for this new instruction. Your implementation should not change the register file itself. Indicate

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any additional control lines required.

(d) Draw the changes to the state machine given in the appendix. Indicate the relevant control signals in any new states you may add.

6. Optional questions [0 marks]

(a) Your comments on the house system so far. You can comment on its positives, negatives, appropriateness of students' reactions, possible incentives, suggestions for improvement, etc.

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(b) Name any three current chief ministers of states in India, and the corresponding states.

(c) Name the seven sister states of Eastern India.

Appendix

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