CSCI 660 EEGN-CSCI 660 Introduction to VLSI Design Lecture 4 Khurram Kazi

New York Institute of Technology

Engineering and Computer Sciences

CSCI 660

EEGN-CSCI 660

Introduction to VLSI DesignLecture 4

Khurram Kazi



CSCI 660 2

Review of ROM/RAM assignment

resetb

Pattern Generator

Design Under Test

(RAM Model)

clk

rwb

Address

Data In

AnalyzerData Out



CSCI 660 3

Signal Generator using Finite State Machine Method

CLOCK

Zero One Two Three Four Five Six Seven

Wave

Wstate



CSCI 660 4

Signal Generator using Finite State Machine Method

library ieee;use ieee.std_logic_1164.all;

ENTITY signal_gen1 IS PORT ( clk: IN STD_LOGIC;

reset: IN STD_LOGIC; wave: OUT STD_LOGIC);

END signal_gen1;

Architecture finite_state_machine OF signal_gen1 IS

TYPE states IS (zero, one, two, three, four, five, six, seven);signal Wstate,: states;signal temp : STD_LOGIC;

BEGINwave <= temp;

PROCESS (clk, reset)Begin

IF (reset = '0') then Wstate <= zero;ELSIF (clk'EVENT and clk = '1') THENCASE Wstate IS WHEN zero => temp <= '0'; Wstate <= one; WHEN one => temp <= '1'; Wstate <= two; WHEN two => temp <= '0'; Wstate <= three; WHEN three => temp <= '1'; Wstate <= four; WHEN four => temp <= '1'; Wstate <= five; WHEN five => temp <= '1'; Wstate <= six; WHEN six => temp <= '0'; Wstate <= seven; WHEN seven => temp <= '0'; Wstate <= zero;END CASE;

END PROCESS;END finite_state_machine;



CSCI 660 5

Clock divider

CLOCK

CLOCK/2

CLOCK/4

CLOCK/8

CLOCK/16

Do the clocks have to be 50% duty cycle?

How would you design a divide by 3 clock??

Bits change on every rising clock edge!



CSCI 660 6

Serial to parallel conversionlibrary ieee;use ieee.std_logic_1164.all;

ENTITY ser_to_par is generic(N : integer := 8); port( clk : in STD_LOGIC;

sin : in STD_LOGIC; resetb : in STD_LOGIC;

par_dout : out std_logic_vector ((n-1) downto 0));

end ser_to_par;

architecture behavior of ser_to_par issignal par_reg : std_logic_vector((n-1) downto 0);signal bit_counter : integer;signal shiftreg : std_logic_vector ((n-1) downto 0);beginshiftin: process (clk, resetb) begin if (resetb = '0') then shiftreg <= (others => '0'); elsif rising_edge(CLK) then shiftreg <= shiftreg((n-2) downto 0) & sin; end if;end process shiftin;

Parallel_load_data: process (clk, resetb)begin if (resetb = '0') then par_reg <= (others => '0'); elsif rising_edge (clk) then if(bit_counter = (n-1)) then par_reg <= shiftreg; end if; end if;end process;

process (clk, resetb)begin if (resetb = '0') then bit_counter <= 0; elsif rising_edge (clk) then if (bit_counter = n - 1) then bit_counter <= 0; else bit_counter <= bit_counter + 1; end if; end if;end process;

end behavior;



CSCI 660 7

SONET Frame



CSCI 660 8

SONET Framer Framing States within the SONET Framer

Out of Frame (OOF) In this state when out of reset state and if contiguous

24 errored frames (i.e. 24 invalid framing patterns) Errored Frame (EF)

In this state if 2 contiguous errored frames received (i.e. 2 invalid framing patterns)

Severely Errored Frame (SEF) In this state if 4 contiguous errored frames received

(i.e. 4 invalid framing patterns) In Frame

When 2 contiguous valid frames received



CSCI 660 9

Scrambling in SONET (STS-1)1 + x6 + x7: Why scramble data?

1234567 datain dataout unscrambled data

1 1111111 1 0 1

2 0111111 1 0 1

3 0011111 0 1 0

4 0001111 0 1 0

5 0000111 0 1 0

6 0000011 1 0 1

7 0000001 1 0 1

8 1000000 1 1 1

9 0100000 1 1 1

10 0010000 0 0 0

11 0001000 0 0 0

dataoutdatainclk

QD QD QD QD QD QD QD

All FFs should be set to a logic1

On the receive side use the same circuit. The receive data goes in the “datain” pin and the original unscrambled data is extracted on “dataout”.

A1A2 Bytes are NOT scrambled



CSCI 660 10

PRBS (Pseudo Random Binary Sequence)

PRBS is a very powerful pattern generator and that can be self- checking on the receiving end.

Use one of the PRBS pattern generator as the data source for the payload area within the SONET frame



CSCI 660 11

Sample code of LFSR (3bit LFSR)

LIBRARY ieee;USE ieee.std_logic_1164.all;USE ieee.std_logic_arith.all;

ENTITY lfsr IS

PORT ( clk : IN std_logic resetb : IN std_logic; lfsr_out : OUT std_logic );END lfsr;

ARCHITECTURE behavior of lfsr IS

signal lfsr_reg : std_logic_vector (2 downto 0);

signal tap1 : std_logic;

BEGIN

Process (clk, resetb)BEGIN

if (resetb = '0') then lfsr_reg <= (others => '1'); --presetting the LFSRelsif (clk'event and clk = '1') then lfsr_reg <= lfsr_reg(1 downto 0) & tap1;end if;

end process;

tap1 <= lfsr_reg(0) xor lfsr_reg(2); lfsr_out <= lfsr_reg(2);

END behavior;



CSCI 660 12

Data Com bytes (D1-D3)D1-D3 bytes are the 1st three bytes in

the 3rd row of the STS-1 frame. These bytes are used as a 192 kbps data channel for operations functions, such as Operations, Administration, Management and Provisioning (OAM&P). These bytes are used between 2 “section” type equipment (like regenerator)



CSCI 660 13

Data Com bytes D4-D12

These bytes (1st three bytes of rows 6,7 and 8) represent a 576 kbps message-based channel used for OAM&P messages between SONET line-level network equipment.



CSCI 660 14

Clock generator block

Input serial clock Internal byte_clock also output clock

(spe_clk)D1_3_clockD4_12_clk

All the clocks going to different blocks need to be generated from this block



CSCI 660 15

Some recommendation for test benches (package)

Package package_name IS(package delcrations)

End package_name;e.g.PACKAGE SONET_Pkg ISSignal tb_d1Byte : std_logic_vector (7 downto 0);Signal tb_d2Byte : std_logic_vector (7 downto 0);Signal tb_d3Byte : std_logic_vector (7 downto 0);Signal tb_d4Byte : std_logic_vector (7 downto 0);Signal tb_d5Byte : std_logic_vector (7 downto 0);Signal tb_d6Byte : std_logic_vector (7 downto 0);Signal tb_d7Byte : std_logic_vector (7 downto 0);Signal tb_d8Byte : std_logic_vector (7 downto 0);Signal tb_d9Byte : std_logic_vector (7 downto 0);Signal tb_d10Byte : std_logic_vector (7 downto

0);Signal tb_d11Byte : std_logic_vector (7 downto

0);Signal tb_d12Byte : std_logic_vector (7 downto

0);END SONET_Pkg;

1) write this package in a vhdl file, e.g. “SONET_Pkg.vhd”.

2) Compile the package vhdl file

3) Include under the library declarations

USE work.SONET_Pkg.all;



CSCI 660 16

Suggested pinout of the Framer

ser_datain

ser_clk

reset_n

spe_valid

spe_clk

spe_dataout[7:0]

d1_3_sof

d1_3_clk

d1_3_dataout

d4_12_sof

d4_12_clk

d4_12_dataout

BIP1_err

frame_state [1:0]



CSCI 660 17

Block diagram of the Framer Receiver direction

Frame_detectFraming state machine

Bit counterByte counter

Serial to parallel converter

ser_in

reset_b

clk

Clock generation

Overhead bytes RAM controller

(Generates signals for RAM)

8 bits data

counters

Byte clock

Overhead bytes RAM

SPE Data out processor(transports data, generates

SPE_Valid .. Etc.)

D1_3_clk

D4_12_clk

D1_3 bytes reader from RAM

Parallel to serial data

D4_12 bytes reader from RAM

Parallel to serial data

D1_3_data

D1_3_clk

D4_12_clk

D4_12_data

D1_3_data_val

D4_12_data_val

SPE_data

SPE_val

D1_12 data

FRAMER.vhd



CSCI 660 18

Block diagram of top.vhd

Framer.vhdgenerator.vhd

analyzer.vhd(Includes

LFSR for SPE,D1_3 bytes, D4_12 bytes

analysis)

sonet_pkg.vhd

Framer_top.vhd

Declare signals in framer_pkg.vhd

Drive the signals in generator

Monitor the signals in analyzer to see whatever OHs received matched the values in the generator



CSCI 660 19

Some recommendation for test benches Use global signals to pass information

between the generator to the data analyzer. These global signals can be used to control the pattern generators as the simulation progress.

Use some sort of timestamp to keep track of events. For example use frame counter (in the test bench) to keep track of data sent a particular frame and use that information during the self checking of the output data!



CSCI 660 20

Assignment InFrame = in frame EF = Errored Frame : 2 contiguous invalid framing pattern SEF = Severely Errored Frame : 4 contiguous invalid framing pattern OOF = out of Frame : 24 contiguous invalid framing pattern Extend SONET Framer to incorporate four states of the framer:

1) In-Frame state, 2) EF, 3)SEF, 4) OOF USE concept developed in slide 13 (lecture 4) to define these states

Extend the SONET Framer’s testbench to incorporate: Generate SONET valid SONET frames (i.e. proper A1 A2 Byte contents

of F6 28) for at least 3 frames Generate 4 contiguous invalid framing pattern (by changing different

bits inside the A1 or A2 byte) This will result in SONET Framer detecting EF and SEF States

Continue generating invalid framing pattern for a total of 24 frames This will result in SONET Framer going into OOF state

Add to the framer’s port list InFrame, EF, SEF and OOF. Each will be a std_logic. Assert these ports high whenever the framer is in the respective state.



CSCI 660 21

Assignment

After acquiring frame Convert serial data into parallel data Store the Over Head portion of data into a RAM 8 bit data should be written to the RAM at a time.



CSCI 660 22

Assignment Use the SONET scramble to scramble the data (except A1

and A1 bytes) Use PRBS pattern generator to insert in the 3 Data Com

bytes D1-D3 byte positions Take first 9 characters of your name and convert them into

ASCII (bit value). Insert those values in the D4-D12 byte positions.

The D1-D3 and D4-D12 data should come out on separate serial ports along with 192 kbps and 576 kbps clock. The firs byte should be indicated by a start of frame signal. (3 ports per Data com bytes should be output ports from your block, therefore total of 6 output ports)



CSCI 660 23

How do I get started (1)?

1) Look for the framing patternDesign a bit counter that rolls over every

8th cycle (i.e. it goes from 0 – 7 and then back to 0

Design a byte counter that counts from 0 – 809 and rolls over back to 0

The starting values of both the bit and byte counters should coincide with every occurrence of the framing pattern to ensure that the framing pattern comes in at the desired expected bit count value/byte count value



CSCI 660 24

How do I get started (2)? Develop a state machine that has the states:

In-frame state (go in this state if two consecutive valid frames are received)

Errored Frame (EF) state: go in this state if 2 contiguous errored frames received (i.e. 2 invalid framing patterns)

Severely Errored Frame (SEF) state: go in this state if 4 contiguous errored frames received (i.e. 4 invalid framing patterns) are received

Out of Frame (OOF) state: go in this state when out of reset state and if contiguous 24 errored frames (i.e. 24 invalid framing patterns)



CSCI 660 25

How do I get started (3)? Normal operation of data occurs when the device

goes from OOF to Inframe-state Store the Overhead bytes (OH) in the RAM after

they have been received serially and subsequently converted into parallel (8 bits).

At a later time of receiving the OH bytes read the data from the proper RAM location (read in 8 bits at a time). Convert 8 bits into serial form Transport the serialized bit out of the appropriate ports

(e.g. d1_d3_dataout, and d4_d12_dataout)

Transport spe_dataout(7:0) as soon as the data is converted from serial to parallel



CSCI 660 26

What are the basic components I need to get started?

Bit counter Byte counter Serial to parallel converter Parallel to serial converter Framing state machine that has the states

defined in 2 of “How do I get started?” Clock generation blocks Refer to 17 for more blocks needed in the

design.

Documents

CSCI 660 EEGN-CSCI 660 Introduction to VLSI Design Lecture 4 Khurram Kazi