• Datapath - performs data transfer and processing operations

The control unit sends:– Control signals– Control outputs

The control unit receives:– External control inputs– Status signals

• Control Unit - Determines the enabling and sequencing of the operations

2 types: Programmable Non-programmable

Programmable System Input consist of sequence of instructions Instruction are usually stored in memory (RAM or ROM) Address comes from PC (Program Counter)

Non-programmable (This chapter FOCUS on this) Control unit is NOT responsible for getting instructions from

memory or sequencing, hence NO PC Control unit determines the operation based on inputs and

status bit from the datapath.

The function of a state machine (or sequential circuit) can be represented by a state table or a state diagram.

A flowchart is a way of showing actions and control flow in an algorithm.

An Algorithmic State Machine (ASM) is simply a flowchart-like way to specify state diagrams for sequential logic and, optionally, actions performed in a datapath.

While flowcharts typically do not specify “time”, an ASM explicitly specifies a sequence of actions and their timing relationships.

A Flowchart is a convenient way to specify a sequence of procedural steps and decision paths for an algorithm.

ASM chart provides not only sequence of events, but it distinguished by the fact that it describes the timing relationship between states of the CU and the datapath actions in response to clock pulses.

4 basic elements:◦State box◦Scalar decision box◦Conditional output box◦Vector decision box

Consist of a rectangle with:◦ The symbolic name for

the state marked outside the upper left top

◦ Containing register transfer operations and outputs activated within or while leaving the state

◦ An optional state code, if assigned, outside the upper right top

Entry

Exit

Explanation: • The register transfer

indicates that the register R is to be reset to 0 on any clock pulse that occurs while the control is in state IDLE.

• RUN indicates that the ouput signal RUN is to be 1 during the time that the control in state IDLE.

Entry

Exit

Consist of a diamond with:◦One input path (entry point).◦One input condition, placed

in the center of the box, that is tested. (in this case START)

◦A TRUE exit path taken if the condition is true (logic 1).

◦A FALSE exit path taken if the condition is false (logic 0).

Entry

Exit 0 Exit 1

(Refers to 1 bit condition)

Consist of an oval with:◦One input path from a

decision box or decision boxes.

◦One output path◦Register transfers or

outputs that occur only if the conditional path to the box is taken.

Entry

Exit 0

Exit 1

Exit 2

Exit 2n - 1

Consist of a hexagon with:◦One Input Path

(entry point).◦A vector of input

conditions, placed in the center of the box, that is tested.

Up to 2n output paths. The path taken has a binary vector value that matches the vector input condition

Transfers and outputs in a state box are Moore type - dependent only on state

Transfers and outputs in a conditional output box are Mealy type - dependent on both state and inputs

Consist of ONE State box and all of the decision and conditional output box connected between the state box exit and entry paths to the same or other boxes.

Figure 8.2 : Morris Mano, pg 367

ANALYSIS: State IDLE, AVAIL = 1 START = 0, next state

is IDLE START = 1, next state,

A is cleared to all 0’s Depending on value of

Q(1:0), next state is MUL0, MUL1, MUL2 or MUL3.

Note : The entry path and the five exit paths for the ASM block is labeled at the boundaries of the ASM block

ANALYSIS: State IDLE, AVAIL = 1 START = 0, next state is to

Increase R and next state is IDLE

START = 1, next to clear R to all 0’s and next state is…

Depending on value of Q0, next state is MUL0 or MUL1.

0 1

Refer to Figure 8.2 Using PGT, the timing diagram below is obtained.

Fig. 8.3 : Morris Mano, pg 368

Fig 8.3 Analysis Clock cycle 1

◦ Present state = IDLE◦ Output AVAIL = 1◦ Input START = 0◦ NEXT clock cycle (beginning of clock cycle 2

PGT)◦ Content of Reg A unchanged, AVAIL =1

Fig 8.3 Analysis Clk cycle 2 (PGT)

Present state = IDLE START = 1 NEXT clock cycle

(beginning of clock cycle 3 PGT)

Reg A = is cleared to 0

Q(1:0) is examined = 01

So path MUL1 is taken

Fig 8.3 Analysis Clk cycle 3 (PGT)

Present state = MUL1 Reg A = 0

Outputs appear while in the state (in response to state and input values)

Register transfers occur at the clock while exiting the state – So, new value occur in the next state!