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Algorithms and Implementation Platforms for WirelessAlgorithms and Implementation Platforms for Wireless

CommunicationsCommunications

TLT-9706/ TKT-9636 Seminar Course

B SICS OF FIELD PROGR MM BLESICS OF FIELD PROGR MM BLE

G TE RR YS TE RR YS

Waqar Waqar HussainHussain

[email protected]@tut.fi

Department of Computer SystemsDepartment of Computer Systems

Tampere UniversityTampere University of Technologyof Technology

LLecture Contentsecture Contents

1. Why there was a need for FPGA ?

2. What is the Scope of FPGA usability ?

3. How to Implement a Digital System ?

4. FPGA Architecture

5. The Unit of Structure of FPGA

6. Hardware Description Languages

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7. Synthesis / Place and Route

8. Timing, Area and Power Analysis

9. Future of FPGA Technology


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Why there was a need for FPGA ?Why there was a need for FPGA ?• Before Programmable Logic?

Fixed hardware = Fixed usability

Limited flexibilit onl ossible b addin software su ort for

example processors

Upgrade or alteration in hardware logic was not guaranteed

An upgrade meant a completely new system

• World’s First Programmable Logic Device(PLD)

EP300: 320 Gates, 3-µm CMOS

10-MHz Performance, 20 I/O Pins

Desktop Programming

3

Why there was a need for FPGA ?Why there was a need for FPGA ?

The FPGA industry sprouted from programmable read-only memory (PROM) and

programmable logic devices (PLDs). PROMs and PLDs both had the option of

bein ro rammed in batches in a f actor or in the field field ro rammable

• World’s First FPGA with Embedded RAM in 1995• 100K Gates, 0.4 & 0.3 µm

• >10M Transistors

• 50-100 MHz Performance

• First PCI Inte ration

World’s-Fir st

FPGA with

Embedded RAM

• First IP Partner Program

4

Xilinx Co-Founders, Ross Freeman and

Bernard Vonderschmitt, invented the first

commercially available field programmable

gate array in 1985 – the XC2064


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Why there was a need for FPGA ?Why there was a need for FPGA ?

• With FPGAso Reprogrammable Logic reusability

o Lower Non-Recurring Engineering (NRE) Cost

o Good for Prototyping

o Less Time to Market

o Can act as a testing device for other digital circuits

o Economical to be used for small volumes of products

o Students can understand digital design concepts in abetter way by designing their custom logic

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What is the Scope of FPGAWhat is the Scope of FPGA

usability ?usability ?

• Home Appliances

•

• Control Systems and Automation

• Mechanical and Civil Engineering

• Test and Measurement Industry

• Medical Equipment

• Avionics and Aerospace Application

• Academia

6


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How to Implement a DigitalHow to Implement a Digital

System ?System ?

r m a n c e

SPHardware

P e r f

Flexibility

GPPDSP

HW/SWCO

ASP

SPHardware

7

C o s t s

Design effort

GPP

DSP

HW/SW

CO

ASP

FPGA ArchitectureFPGA Architecture

• An Example of FPGA Prototyping Board

8


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FPGAFPGA InternalInternal ArchitectureArchitecture• The CLB exchange data using local

and global interconnects

• Local Interconnects >> GlobalInterconnects

• Other than CLBs the interconnects arealso programmable

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Basic Unit of FPGA ConfigurableBasic Unit of FPGA Configurable

LogicLogic

The unit is

“ ” –

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“LE” - Altera

(Example:

Xilinx XC2000)


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Hardware Description LanguageHardware Description Language• Can we use C as HDL?

Operations performed in a sequential order

Hel human's thinkin rocess to develo an algorithm step by step

Resemble the operation of a basic computer model

• Characteristics of digital hardware Connections of parts

Concept of propagation delay and timing

Characteristics cannot be captured by traditional PLs

Require new languages: HDL

Modern HDLModern HDL

• Capture Characteristics of a Digital Circuit

Entity & Connectivity

Concurrency & Timing

• Cover Description

In Gate Level and RT Level

In structural view and behavioral viewo Behavioral View

Describe functionalities and I/O behavior

Treat the system as a black box

o Structural View

Describe the internal implementation (components and

interconnections)

Essentially block diagram


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Synthesis,Synthesis, PlacePlace andand RouteRoute• Accepts HDL description of a system (VHDL, Verilog)

• Quartus II (A Synthesis Tool) Flow Phases

1. Setup

2. Perform RTL Synthesis

3. Map basic gates into FPGA logic

4. Place the logic into specific location in chip

5. Route (connect) the logic elements together

6. Provide statistics and analysis results

7. Create a programming file and upload it into the FPGA

Synthesis,Synthesis, PlacePlace andand RouteRouteQuartusQuartus II design flow after simulated and verifiedII design flow after simulated and verified

designdesign

Generic gate-levelrepresentation

Places and routes thelogic into a device

Converts the post-fit

netlist into a FPGA

programming file

Analyzes and validatesthe timing performance ofall logic in a design.

Run on FPGA


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Synthesis,Synthesis, PlacePlace andand RouteRoute

RTL Synthesis StepRTL Synthesis Step

• Synthesis

user_logic.vhd

Creates basic gates and DFFs

from HDL

o Result is so called netlist

A full description of logical ports

and their connections

• Synthesis results can be

s yn t h

viewed with RTL Viewer Tool

netlist(in RTL viewer)

Synthesis,Synthesis, PlacePlace andand RouteRouteTechnologyTechnology MappingMapping

gate-level netlist

x0

m1 x

2

1

• Transforms the basic gates intotechnology specific components

• i.e. into logic elements (LE) with Altera FPGAs

• LE contains look-up table and same function with FPGA’slogic elements

x1

x2

x1

m2

m6

z

x0

m a p

LE

LE

LE


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Synthesis,Synthesis, PlacePlace andand RouteRoute

PlacementPlacement

• Select which physical LEimplement the user function

user function with FPGA’s logic elements

LE LE

• Selected LE should be close

to each other

to physical IO pins that they

use

• Other logic may complicatelacement

pl a c e

LE

FPGA

other functions17

Synthesis,Synthesis, PlacePlace andand RouteRouteRoutingRouting

• Connects used LEs

together

to input/output pins

FPGA

• FPGAs have programmablerouting switches

• Sometimes detours are needed

• Algorithmically complex operation

ay a e a w e w gger

systems

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Timing, Area and Power AnalysisTiming, Area and Power Analysis

• After placement and routing, Critical Path is determined

• Critical Path is the one which is offering longest propagationdelay on FPGA floor

t clk period

t p,dff t su,dff t p, comb

.

clk

Q D

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Timing, Area and Power AnalysisTiming, Area and Power AnalysisModelSimModelSim -- WaveformWaveform

high-freq

signal

Monitored

signals

Values at

cursor Cursor line

Analog view

of bus

bus

1-bit

signal

Time axis

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Timing, Area and Power AnalysisTiming, Area and Power Analysis

• It is important to analyze area utilization summary.

Design resources should not exceed FPGA resources

o Design can be synthesized optimally w.r.t area utilization if does

not fit by normal synthesis

• More exchange of data between memory and processing elementsmeans more switching between the transistor states therefore more

power dissipation

Two Important factors for obtaining power estimate

o Accurate si nal activit

o Accurate power models

Provided by the FPGA Vendor

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FutureFuture of FPGAof FPGA DevicesDevices

• FPGA device densities are increasing in millions of gates

• Altera’s latest device is Stratix-V

• Xilinx’s latest device is Virtex-7

• Higher density devices are expected with higher number of hard macros

FPGA are expected to stay in market for the next 50 years

• Research interests are growing more towards Coarse-grain

Reconfigurable Array (CGRA)

The unit of structure in FPGA is a LE whereas in CGRA, it is the ALU

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