TRNG I HC BCH KHOA H NI KHOA IN T - VIN THNG s: 1 K duyt Tng s trang: 1

THI MN: IN T S Ln thi: 1 Ngy thi: 22/12/2010 Thi gian lm bi: 90 pht(Khng s dng ti liu. Np thi cng vi bi lm)

Trng nhm Mn hc:

Trng B mn:

Cu 1: (2 im)

Hy thit k mch s vi u vo l s nh phn 4 bit ABCD v u ra l s nh phn 4 bt EFGH l s b hai ca s u vo.Cu 2: (3 im) Cho s mch s nh sau:

a. (1 im) Hy m t mch trn dng ngn ng VHDL. b. (0.5 im) Hy thay th 3 b dn knh (MUX) trn bng dng cc cng NAND 2 u vo vNAND 3 u vo.

c. (1.5 im) Hy thc hin cc bc phn tch mch in trn c c s dch chuyn trng thi.Cu 3: (3 im)

a. (2 im) Hy thc hin thit k mch in t dng JK Flip-flop c chc nng reset. Mch in gm mt u vo X v mt u ra Z vi cc chc nng hot ng nh sau: Z=1 khi mc logic trn u vo l dy bt c dng x=0101, Z=0 trong cc trng hp khc. b. (1 im) Hy vit chng trnh VHDL m t s dch chuyn trng thi va nhn c t cu a).Cu 4: (2 im) Hy thit k Datapath cho FSMD thc hin thut ton sau: min=0; sum=0; for (i=0;i xi ) min = xi ; end if; end for; output sum; output min; Ch : 1. 0 x, min, sum 255, 2. Cc lnh vit trn cng hng c thc hin song song, 3. Ch r cc thanh ghi trong datapath l bao nhiu bit.

J 0 0 1 1

K 0 1 0 1

Q (next) Q 0 1 Q

Q Q(next) 0 0 0 1 1 0 1 1

J 0 1 x x

K x x 1 0

TRNG I HC BCH KHOA H NI KHOA IN T - VIN THNG s: 2 K duyt Tng s trang: 1

THI MN: IN T S Ln thi: 1 Ngy thi: 22/12/2010 Thi gian lm bi: 90 pht(Khng s dng ti liu. Np thi cng vi bi lm)

Trng nhm Mn hc:

Trng B mn:

Cu 1 :(2 im)

Hy thit k mch s vi u vo l s nh phn 4 bit wxyz v u ra l s nh phn 4 bt abcd l s b hai ca s u vo.Cu 2: (3 im) Cho s mch s nh sau:

a. (1 im) Hy m t mch trn dng ngn ng VHDL. b. (0.5 im) Hy thay th 3 b dn knh (MUX) trn bng dng cc cng NAND 2 u vo vNAND 3 u vo.

c. (1.5 im) Hy thc hin cc bc phn tch mch in trn c c s dch chuyn trng thi.Cu 3: (3 im)

a. (2 im) Hy thc hin thit k mch in t dng JK Flip-flop c chc nng reset. Mch in gm mt u vo X v mt u ra Z vi cc chc nng hot ng nh sau: Z=1 khi mc logic trn u vo l dy bt c dng x=1010, Z=0 trong cc trng hp khc. b. (1 im) Hy vit chng trnh VHDL m t s dch chuyn trng thi va nhn c t cu a).Cu 4 :(2 im) Hy thit k Datapath cho FSMD thc hin thut ton sau: max=0; sum=0; for (i=0;i 10) then cnt=cnt + 1; sum=sum + x; end if; until x =0; output sum; output cnt; Ch : 1. 0 x 255, 0 sum 255. Cc lnh vit trn cng 1 hng c thc hin song song. 2. Ch r cc thanh ghi trong datapath l bao nhiu bit. Cho bit bng trng thi v bng kch ca JKFF nh sau:J 0 0 1 1 K 0 1 0 1 Q (next) Q 0 1 Q Q Q(next) 0 0 0 1 1 0 1 1 J 0 1 x x K x x 1 0

TRNG I HC BCH KHOA H NI KHOA IN T - VIN THNG s: 1 K duyt Tng s trang: 2

THI MN: IN T S Ln thi: 1 Ngy thi: 25/12/2009 Thi gian lm bi: 90 pht(Khng s dng ti liu. Np thi cng vi bi lm)

Trng nhm Mn hc:

Trng B mn:

Cu 1 (2 im) c. Thit k mc cng (gate level design) mt mch s gm c u vo l mt s nh phn 3 bt v u ra l s nh phn biu din s bt 1 c trong s nh phn u vo. d. Thc hin mch thit k cu a ch s dng cc b MUX 4-1 v cng NOT. Cu 2 (2 im) Mt mch dy gm 2 Flip-flop JK, 2 u vo X v Y v mt u ra Z. Cho cc phng trnh u vo ca cc Flip-flop v phng trnh u ra Z nh sau:J 1 = Q2 X + Q2 Y

J 2 = Q1 X

K 1 = Q2 XY K 2 = Q1 + XY

Z = Q1 XY +Q2 X Y

c. V s mch in d. Xc nh bng chuyn trng thi v s chuyn trng thi ca mch Cu 3 (3 im) a. M t DFF vi 1 tn hiu reset ng b tch cc mc thp v 1 tn hiu set ng b tch cc mc thp dng VHDL (1 im). b. Mt mch s vi mt u vo X v mt u ra Z hot ng nh sau: -Tn hiu vo l 0 hoc 1 xut hin ngu nhin -Z=1 nu gp dy bit u vo l 110 hoc 0101 -Z=0 trong cc trng hp khc Biu din hot ng ca mch trn bng s chuyn trng thi loi Moore v dng DFF thc hin (2 im) Cu 4 (3 im) Thit k FSMD thc hin thut ton tnh tng ca 10 s x ln hn 5 nh sau: cnt=0; sum=0; Repeat input x if (x > 5) then cnt=cnt + 1; sum=sum + x; end if; Until cnt=10; } output sum; Ch : 1. x v sum l cc s c gi tr cc i l 255. Cc lnh vit trn cng 1 hng c thc hin song song. 2. Ch r cc thanh ghi trong datapath l bao nhiu bit.

3. Ch cn biu din controller di dng FSM, khng cn phi thc hin mch controller. Cho bit bng trng thi v bng kch ca JKFF nh sau:J 0 0 1 1 K 0 1 0 1 Q (next) Q 0 1 Q Q Q(next) 0 0 0 1 1 0 1 1 J 0 1 x x K x x 1 0

Chc cc em sinh vin lm bi tt!

TRNG I HC BCH KHOA H NI KHOA IN T - VIN THNG s: 1 K duyt Tng s trang: 1

THI MN: IN T S Ln thi: 1 Ngy thi: 25/12/2009 Thi gian lm bi: 90 pht(Khng s dng ti liu. Np thi cng vi bi lm)

Trng nhm Mn hc:

Trng B mn:

Cu 1 (2 im) e. Thit k mc cng (gate level design) mt mch s gm c u vo l mt s nh phn 3 bt v u ra l s nh phn biu din s bt 1 c trong s nh phn u vo. f. Thc hin mch thit k cu a ch s dng cc b MUX 4-1 v cng NOT. Cu 2 (2 im) Mt mch dy gm 2 Flip-flop JK, 2 u vo X v Y v mt u ra Z. Cho cc phng trnh u vo ca cc Flip-flop v phng trnh u ra Z nh sau:J 1 = Q2 X + Q2 Y

J 2 = Q1 X

K 1 = Q2 XY K 2 = Q1 + XY

Z = Q1 XY +Q2 X Y

e. V s mch in f. Xc nh bng chuyn trng thi v s chuyn trng thi ca mch Cu 3 (2 im) a. M t DFF vi 1 tn hiu reset ng b tch cc mc thp v 1 tn hiu set ng b tch cc mc thp dng VHDL b. M t 1 thanh ghi 4 bit s dng DFF m t cu a bng VHDL (gi : s dng cu trc khai bo component v cu trc port map ca VHDL) Cu 4 (4 im) Thit k FSMD thc hin thut ton tnh tng ca 10 s x ln hn 5 nh sau: cnt=0; sum=0; Repeat input x if (x > 5) then cnt=cnt + 1; sum=sum + x; end if; Until cnt=10; }

output sum; Ch : 1. x v sum l cc s c gi tr cc i l 255. Cc lnh vit trn cng 1 hng c thc hin song song. 2. Ch r cc thanh ghi trong datapath l bao nhiu bit. 3. Biu din controller di dng FSM loi Moore v dng DFF thc hin. Cho bit bng trng thi v bng kch ca JKFF nh sau:J 0 0 1 1 K 0 1 0 1 Q (next) Q 0 1 Q Q Q(next) 0 0 0 1 1 0 1 1 J 0 1 x x K x x 1 0

Chc cc em sinh vin lm bi tt! TRNG I HC BCH KHOA H NI THI MN: IN T S KHOA IN T - VIN THNG Ln thi: 1 Ngy thi: 05/01/2010 Thi gian lm bi: 90 pht s: 2 Tng s trang: 1 K duyt Trng nhm Mn hc:(Khng s dng ti liu. Np thi cng vi bi lm)

Trng B mn:

Cu 1 (2 im) Thit k mt mch s gm c u vo l hai s nh phn A v B, mi s c biu din bi 2 bt v 2 u ra dng biu din s A ln hn, nh hn hoc bng B. (ghi ch: 2 u ra c gi tr bng 00 nu A = B, 01 nu A > B, 1x nu A < B) Cu 2 (3 im) Mt mch s vi mt u vo X v mt u ra Z hot ng nh sau: -Tn hiu vo l 0 hoc 1 xut hin ngu nhin -Z=1 nu gp dy bit u vo l 0101 -Z=0 trong cc trng hp khc Biu din hot ng ca mch trn bng s chuyn trng thi loi Mealy v dng JKFF thc hin. Cu 3 (2 im) Hy dng VHDL m t thit k cho s dch chuyn trng thi sau

Cu 4 (2 im)Mt mch dy gm 2 Flip-flop JK, 2 u vo X v Y v mt u ra Z. Cho cc phng trnh u vo ca cc Flip-flop v phng trnh u ra Z nh sau: Z = Q1 XY +Q2Y J 1 = Q2 X + Q2 K 1 = Q2 Y J 2 = Q1 XY K 2 = Q1 + XY a. V s mch in b. Xc nh bng chuyn trng thi v s chuyn trng thi ca mch

Cu 5 (1 im)Thit k Datapath cho FSMD thc hin thut ton m v tnh tng ca cc s ln hn 10 trong cc s x c a vo nh sau: cnt=0; sum=0;

Repeat input x if (x> 10) then cnt=cnt + 1; sum=sum + x; end if; until x =0; output sum; output cnt; Ch : 1. 0 x 255, 0 sum 255. Cc lnh vit trn cng 1 hng c thc hin song song. 2. Ch r cc thanh ghi trong datapath l bao nhiu bit. Cho bit bng trng thi v bng kch ca JKFF nh sau: x= dont care (khng quan tm)J 0 0 1 1 K 0 1 0 1 Q (next) Q 0 1 Q Q Q(next) 0 0 0 1 1 0 1 1 J 0 1 x x K x x 1 0

TRNG I HC BCH KHOA H NI KHOA IN T - VIN THNG s: 1 Tng s trang: 1 K duyt Trng nhm Mn hc:

THI MN: IN T S Ln thi: 1 Ngy thi: 05/01/2010 Thi gian lm bi: 90 pht(Khng s dng ti liu. Np thi cng vi bi lm)

Trng B mn:

Cu 1 (2 im) Thit k mt mch s gm c u vo l hai s nh phn A v B, mi s c biu din bi 2 bt v 2 u ra dng biu din s A c s bit trng thi 1 ln hn, nh hn hoc bng s bit 1 ca s B. (ghi ch: 2 u ra c gi tr bng 00 nu A c s bt 1 bng s bit 1 ca B, 01 nu A c s bt 1 ln hn s bit 1 ca B, 1x nu A c s bt 1 nh hn s bit 1 ca B) Cu 2 (3 im) Mt mch s vi mt u vo X v mt u ra Z hot ng nh sau: -Tn hiu vo l 0 hoc 1 xut hin ngu nhin -Z=1 nu gp dy bit u vo l 1011 -Z=0 trong cc trng hp khc Biu din hot ng ca mch trn bng s chuyn trng thi loi Moore v dng JKFF thc hin. Cu 3 (2 im) Hy dng VHDL m t thit k cho s dch chuyn trng thi sau

Cu 4 (2 im)Mt mch dy gm 2 Flip-flop JK, 2 u vo X v Y v mt u ra Z. Cho cc phng trnh u vo ca cc Flip-flop v phng trnh u ra Z nh sau: J 1 = Q2 X + Q2 Y K 1 = Q2 XY Z = Q1 XY + Q2 X J 2 = Q1 X K 2 = Q1 + XY a. V s mch in b. Xc nh bng chuyn trng thi v s chuyn trng thi ca mch

Cu 5 (1 im)Thit k Datapath cho FSMD thc hin thut ton m v tnh tng ca cc s ln hn 10 trong cc s x c a vo nh sau: cnt=0; sum=0; Repeat input x if (x> 10) then cnt=cnt + 1; sum=sum + x; end if; until x =0; output sum; output cnt; Ch : 1. 0 x 255, 0 sum 255. Cc lnh vit trn cng 1 hng c thc hin song song. 2. Ch r cc thanh ghi trong datapath l bao nhiu bit. Cho bit bng trng thi v bng kch ca JKFF nh sau: x= dont care (khng quan tm)J 0 0 1 1 K 0 1 0 1 Q (next) Q 0 1 Q Q Q(next) 0 0 0 1 1 0 1 1 J 0 1 x x K x x 1 0

TRNG I HC BCH KHOA H NI KHOA IN T - VIN THNG s: 2 K duyt Tng s trang: 2

THI MN: IN T S Ln thi: 1 Ngy thi: 15/6/2009 Thi gian lm bi: 90 pht(Khng s dng ti liu. Np thi cng vi bi lm)

Trng nhm Mn hc:

Trng B mn:

Cu 1 (2 im) a. Thit k b cng y 1 bit mc cng (gate level design) b. Thit k b cng 4 bit t b cng 1 bit thit k cu a. Cu 2 (2 im) c. Rt gn mch sau s dng ba Karnaugh:

A

B

C

D

d. Thc hin mch rt gn cu a ch s dng cng NAND 2 u vo. Cu 3 (3 im) Cho mch sau:

x1 x2

J1 K1

Q1 Q1

J2 K2

Q2 Q2

Zc. Phn tch mch v xc nh s chuyn trng thi FSM. d. M t cu trc mch trn bng VHDL (gi thit cc phn t trong mch c khai bo Entity cc file khc). Cu 4 (3 im) Thit k FSMD thc hin thut ton tnh n! sau: product=1 input n while (n > 1) { product=product * n n = n-1 } output product Ch : 1. n v product l cc s 8 bit 2. Controller phi c thit k s dng flip-flop D Cho bit bng trng thi v bng kch ca JKFF nh sau:J 0 0 1 1 K 0 1 0 1 Q (next) Q 0 1 Q Q Q(next) 0 0 0 1 1 0 1 1 J 0 1 x x K x x 1 0