Deliverable 5.2.2 Final Dissemination Report€¦ · D5.2.2 “Final Dissemination Report”, Apr 2016 2/14 Summary No and name D5.2.2 – Final Dissemination Report1 Status Released

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FP7-ICT-2011-8 – Collaborative Project (STREP)

PowerSWIPE (Grant agreement 318529)

Objective ICT-2011.3.1 – Very advanced nanoelectronic components: design,

engineering, technology and manufacturability

PowerSWIPE (Project no. 318529)

“POWER SoC With Integrated PassivEs”

Deliverable 5.2.2

“Final Dissemination Report” Dissemination level: PU

Responsible Beneficiary Tyndall National Institute, University College Cork

Due Date 31st March 2016

Submission Date 29th April 2016

D5.2.2 “Final Dissemination Report”, Apr 2016

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Summary

No and name D5.2.2 – Final Dissemination Report1 Status Released Due Month 42 Date 31-Mar-2016

Author(s) Nicolás Cordero

Editor Nicolás Cordero

DoW Report on the Dissemination and Communication activities carried out by the PowerSWIPE consortium

Dissemination Level

PU - Public

Nature Report

Document history

V Date Author Description

Draft 15-Apr-2016 N.C. Draft

1.0 25-Apr-2016 N.C. First release

1.1 28-Apr-2016 N.C. Input from partners

Related documents: Deliverable D5.2.1, “Mid-term Dissemination Report”

1 Disclaimer - The information in this document is provided as is and no guarantee or warranty is given that the information is fit for any particular purpose. The user thereof uses the information at its sole risk and liability.


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1. Table of Contents

1. Table of Contents ................................................................................................................. 3

2. Publishable Summary........................................................................................................... 4

3. Introduction ......................................................................................................................... 4

4. Description .......................................................................................................................... 5

4.1 Branding ........................................................................................................................... 5

4.2 Web site ........................................................................................................................... 6

4.3 LinkedIn Group ................................................................................................................. 7

4.4 Journal Editorship ............................................................................................................. 8

4.5 Training: Tutorials, Professional Development .................................................................. 8

4.6 Scientific (Peer Reviewed) Publications ............................................................................ 9

4.7 Conference presentations .............................................................................................. 11

4.8 Workshops and exhibitions ............................................................................................ 13

5. Conclusions ........................................................................................................................ 14


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2. Publishable Summary

The PowerSwipe project addresses a key roadblock for PowerSoC by, for the first time,

miniaturising and integrating state-of-the-art, high density trench capacitor substrate technology

with novel thin film magnetics on silicon to deliver a multi-component LC (inductor-capacitor)

interposer which will be combined, in a 3D heterogeneous stack, using eWLB technology, with the

μController chip.

The main dissemination objective during the first three months of the project was the development of a project Web site. For more details, please check Deliverable D5.1., or go to http://www.powerswipe.eu As part of the Web development, a project logo and a project banner were also designed.

To give a uniform and easily recognisable project appearance, standard templates for both reports and presentations were also set up. A LinkedIn group dealing with PowerSoc was also created, with both members and non-member of the PowerSwipe consortium taking part in rewarding discussions on the topic.

A range of papers were submitted/presented at relevant conferences: Compel’13, CIPS’14, APEC’14, APEC’15 and APEC’16. The consortium has also presented a number of Professional Seminars in conjunction with these conferences.

3. Introduction

Dissemination and communication are essential tools to spread the message, outcomes and

impact of the project to both the technical and non-technical audiences.

Dissemination activities within the project are facilitated through WP5 that aims at promoting

project results to scientific community, industry and general public. Three different dissemination

mechanism are used, namely the project website, the organisation of events and the

http://www.powerswipe.eu/


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dissemination through publicity actions. Depending on the nature of the audience in each action,

different aspects and information is conveyed achieving maximum outreach and effectiveness.

From month 3 of the project, PowerSwipe had a dedicated Web site. The Website is used for

dissemination of project objectives and results to the scientific and industrial communities and to

the public in general.

The consortium actively disseminates research results in the power electronics academic and

industrial community through journal and conference publications. Specifically, partners aim at

publishing in high impact factor scientific journals.

The PowerSWIPE consortium also aims at organising workshops/tutorials on Power Supply on Chip

(PwrSoC) and uses these workshops as a platform for disseminating project results to the scientific

community. We also participate at international conferences in power management IEEE APEC,

CIPS, COMPEL, etc.) and system integration and SOC for power.

4. Description

During the first half of the project, the Dissemination activities have focussed on:

Project branding

Project website

LinkedIn PwrSoC group

Conference presentations

Workshops and exhibitions

Training: Tutorials and Professional Development Seminars

4.1 Branding

PowerSWIPE designed a logo and banner to give a single easily recognisable project image. This

logo is used in all project deliverables and presentations.

Figure 1. Project logo and banner


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4.2 Web site

The address for the Project Website is: http://www.powerswipe.eu.

The PowerSwipe project consortium has registered the domain name www.powerswipe.eu for

exclusive use by the project. The consortium will retain this URL for the duration of the project and

for at least 18 months once the project ends (i.e. to end of 2017).

The Website is hosted at the Tyndall computer server. The Website also links to a private

document repository (Consortium embers only access) which is hosted by Infineon Austria.

The following figure shows a screenshot of the Home page.

Figure 2. Website Home page


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The Website contains the following pages: Home, About Us, Partners, Results, News, Events,

Contact Us and Downloads.

4.3 LinkedIn Group

The PowerSWIPE consortium has set up a LinkedIn group on Power Supply on Chip (PwrSoC).

Figure 3. Screenshot of LinkedIn “Power Supply on Chip” group

The membership of the group is open to any professionals working on PwrSoC and related areas

(both members of the PowerSWIPE consortium and to non-PowerSWIPE). It currently has 88

members.

The LinkedIn group provides an open forum for discussions on topics related to PwrSoC.

Furthermore it gives a quick link to news, updates, and information.


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4.4 Journal Editorship

IEEE Trans. Power Electronics, Sept. 2013. Special issue on PowerSoC, Guest editor: C. O’Mathuna

4.5 Training: Tutorials, Professional Development

Over 110 attendees took part in the Professional Development Seminar on Power Supply on Chip organised by the PowerSwipe Consortium during APEC’2014.

Figure 4. Announcement and lecture by Prof. Cobos during APEC’14

A second Professional Education Seminar took place during APEC’2015. Over 120 attendees took part in the seminar on “Power Supply on Chip Technology for High Frequency Integrated Voltage Regulation” organised by the PowerSWIPE consortium on March 16th in Charlotte, North Carolina, USA. The PowerSwipe consortium organised a two day ECPE PowerSoC workshop on “Micropower Electronics: Powering Low-Power Systems” which took place in Munich on June 16-17, 2015.

Figure 5. Flyer for ECPE Workshop (June 1015)


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4.6 Scientific (Peer Reviewed) Publications

Neveu, F.; Allard, B.; Martin, C.; “A review of state-of-the-art and proposal for high frequency inductive step-down DC–DC converter in advanced CMOS”, Analog Integrated Circuits and Signal Processing, Vol. 87, Issue 2, May 2016, pp. 201-11. DOI: 10.1007/s10470-015-0683-z Neveu, F.; Allard, B.; Martin, C.; Bevilacqua, P.; Voiron, F. “A 100 MHz 91.5% Peak Efficiency Integrated Buck Converter With a Three-MOSFET Cascode Bridge”, IEEE Transactions on Power Electronics, Vol. 31, Issue 6, June 2016, pp. 3985-8. DOI: 10.1109/TPEL.2015.2502058 Anthony, R.; Wang, N.; Casey, D.P.; Ó Mathúna, C.; Rohan, J.F. “MEMS based fabrication of high-frequency integrated inductors on Ni–Cu–Zn ferrite substrates”, Journal of Magnetism and Magnetic Materials, vol 406, 15 May 2016, pp. 89-94. DOI: doi:10.1016/j.jmmm.2015.12.099 Anthony, R.; Ó Mathúna, C.; Rohan, J.F. “Permalloy Thin films on palladium activated self-assembled monolayer for magnetics on silicon applications”, Procedia Physics, vol 75, 2015, pp. 1205-13. DOI: doi:10.1016/j.phpro.2015.12.122 Anthony, R.; Shanahan, B.J.; Waldron, F.; Ó Mathúna, C.; Rohan, J.F. “Anisotropic Ni–Fe–B films with varying alloy composition for high frequency magnetics on silicon applications”, Applied Surface Science, vol 357, part A, 1 December 2015, pp. 385-90. DOI: doi:10.1016/j.apsusc.2015.09.025 Cortes, J.; Svikovic, V.; Alou, P.; Oliver, J.; Cobos, J.A. “v1 concept: designing a voltage mode control as current mode with near time-optimal response for Buck-type converters”, IEEE Transactions on Power Electronics, Vol. 30, Issue 10, October 2015, pp. 5829-41. DOI: 10.1109/TPEL.2014.2368595 Anthony, R.; Wang, N.; Kulkarni, S.; Ó Mathúna, C. “Advances in Planar Coil Processing for Improved Microinductor Performance”, IEEE Transactions on Magnetics, Vol. 50, Issue 11, November 2014, Art. 8401804. DOI: 10.1109/TMAG.2014.2330361 Svikovic, V.; Cortes, J.; Alou, P.; Oliver, J.; Garcia, O.; Cobos, J.A. “Multiphase Current Controlled Buck Converter with Energy Recycling Output Impedance Correction Circuit (OICC)”, IEEE Transactions on Power Electronics, Vol. 30, Issue 9, pp. 5207-22. DOI: 10.1109/TPEL.2014.2362011 Cortes, J.; Svikovic, V.; Alou, P.; Oliver, J.; Cobos, J.A. “Improved transient response of controllers by synchronizing the modulator with the load step: application to V2Ic”, IEEE Transactions on Power Electronics, Vol. 30, Issue 3, pp. 1577-90. DOI: 10.1109/TPEL.2014.2314242


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Cortes, J.; Svikovic, V.; Alou, P.; Oliver, J.; Cobos, J.A. “Accurate Analysis of Subharmonic Oscillations of V2 and V2Ic Controls Applied to Buck Converter”, IEEE Transactions on Power Electronics, Vol. 30, Issue 2, pp.1005-18. DOI: 10.1109/TPEL.2014.2308015


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4.7 Conference presentations

COMPEL’13 (14th IEEE Workshop on Control and Modeling for Power Electronics), Salt Lake City, Utah, 23-26 June 2013.

Cortés, J.; Šviković, V.; Alou, P.; Oliver, J.A.; Cobos, J.A. “Design and analysis of ripple-based controllers for buck converters based on discrete modeling and Floquet theory”, IEEE 14th Workshop on Control and Modeling for Power Electronics (COMPEL), 2013, pp. 1-9. DOE: 10.1109/COMPEL.2013.6626474

CIPS’14 (8th International Conference on Integrated Power Electronics Systems), Nuremberg,

Germany, 25-27 February 2014. http://conference.vde.com/cips/2014/

Ó Mathúna, C.; Wang, N.; Kulkarni, S.; Anthony, R.; Cordero, N.; Oliver, J.; Alou, P.; Šviković, V.; Cobos, J.A.; Cortés, J.; Neveu, F.; Martin, C.; Allard, B.; Voiron, F.; Knott, B.; Sandner, C.; Maderbacher, G.; Pichler, J.; Agostinelli, M.; Anca, A.; Breig, M. “Power Supply With Integrated PassivEs – The EU FP7 Power Swipe Project” (Invited Paper), Proc. CIPS 2014, Nuremberg, 25-27 Feb 2014, pp. 1-7. ISBN 978-3-8007-3578-5

Neveu, F.; Martin, C.; Allard, B. “Review of high frequency, highly integrated inductive DC-DC converters”, Proc. CIPS 2014, Nuremberg, 25-27 Feb 2014, pp. 285-91. ISBN 978-3-8007-3578-5

Cortés, J.; Šviković, V.; Alou, P.; Oliver, J.A.; Cobos, J.A. “Impact of the control on the size of the output capacitor in the integration of Buck converters”, Proc. CIPS 2014, Nuremberg, 25-27 Feb 2014, pp.1-6. ISBN 978-3-8007-3578-5 Best Poster Award

APEC’14 (IEEE Applied Power Electronics Conference and Exposition), Forth Worth, TX (USA), 16-20 March 2014. http://www.apec-conf.org/

J. Cortés, V. Svikovic, P. Alou, J.A. Oliver and J.A. Cobos. “Comparison of the Behavior of Voltage Mode, V2 and V2Ic Control of a Buck Converter for a Very Fast and Robust Dynamic Response” Best Poster Award

INTERMAG 2014, Dresden (Germany), 4-8 May 2014

Anthony, R.; Wang, N.; Kulkarni, S. and Ó Mathúna, C. “Copper coil deposition process and effects of winding gaps on micro-inductor performance”, pp. 1019-21.

COMPEL14 ‘(IEEE 15th Workshop on Control and Modeling for Power Electronics), Santander, 22-25 June 2014

Svikovic, V.; Cortes, J.; Alou, P.; Oliver, J.; Cobos, J.A.; Maderbacher, G.; Sandner, C. “Energy-Based Switches Losses Model for the Optimization of PwrSoC Buck Converter”, DOI: 10.1109/COMPEL.2014.6877140

Cortes, J.; Svikovic, V.; Alou, P.; Oliver, J.; Cobos, J.A. “An Optimization Algorithm to Design Fast and Robust Analog Controls for Buck Converters”, DOI: 10.1109/COMPEL.2014.6877166

EPE’14-ECCE Europe (16th European Conference on Power Electronics and Applications), Lappeenranta (Finland), 26-28 August 2014

Cortes, J.; Svikovic, V.; Alou, P.; Oliver, J.; Cobos, J.A. “Analysis on the Effect of Modulation Delays on the Size of the Output Capacitor”, DOI: 10.1109/EPE.2014.6910947


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ECCE’2014 (IEEE Energy Conversion Congress and Expo), Pittsburgh, 14-18 September 2014

Šviković, V.; Cortés, J.; Alou, P.; Oliver, J.; Cobos, J.A. “Optimization and Analysis of PwrSoC Buck Converter with Integrated Passives for Automotive Application”, pp. 2164-71. DOI: 10.1109/ECCE.2014.6953690 Best Poster Award ECCE’14

PwrSOC 2014 (International Workshop on Power Supply on Chip), Boston (USA), 6-8 October 2014

C. Sandner, G. Maderbacher, A. Anca, et al. “Towards a PowerSoC Solution for Automotive Microcontroller Applications”

L. Fourneaud, M. Jatlaoui, F. Voiron. “Silicon integrated capacitance for power conversion applications”

V. Svikovic, J. Cortés, P. Alou, J.A. Oliver, J.A. Cobos. “CAD tool to Optimize the Design of a PowerSoC Converter: Powerswipe Design Case”

B. Allard, F. Neveu, C. Martin. “State of the art of high switching frequency inductive DC-DC converters in SoC context”

F. Neveu, B. Allard, C. Martin. “Power stage design and optimization for low power, high frequency, integrated DC-DC converter”

G. Maderbacher, A. Einwanger, C. Sandner, A. Anca, G. Beer, et al. “High Efficient Power Conversion from Car Batteries to Next Generation Microcontroller Systems”

3DIC’14 (IEEE International 3D Systems Integration Conference), Kinsale (Ireland), December 2014. https://www.3dic-conf.org/

Anthony, R.; Wang, N.; Kulkarni, S.; Ó Mathúna, C. “Advanced Processing for High Efficiency Inductors for 2.5D/3D Power Supply in Package” Best Poster Award 3DIC’14

IWIPP’15 (IEEE International Workshop on Integrated Power Packaging), Chicago (USA), 3-6 May 2015

Voiron, F. “Silicon High-Density Capacitors for Power Decoupling Applications” ICM 2015 (20th International Conference on Magnetism), Barcelona (Spain), 5-10 July 2015

Anthony, R. “Permalloy Thin Films on Palladium Activated Self-Assembled Monolayer for Magnetics on Silicon Applications”

EuMW (European Microwave Week), Paris, 6-11 September 2015

Voiron, F. “New Ultra Low ESR Mosaic PICS Capacitors for Power Conversion” ECCE 2015 (IEEE Energy Conversion Congress and Expo), Montreal (Canada), 20-24 September 2015

Pavlovic, Z., Kulkarni, S., Wang, N., O’Mathuna, C. “High Efficiency on-Silicon Coupled Inductors using Stacked Copper Windings”

MNE’15 (41st Micro and Nano Engineering conference), The Hague (Netherlands), 21-24 September 2015

Anthony, R.; Ó Mathúna, C.; Rohan, J. “Electrochemical Process for Fabrication of Laminated Micro-Inductors on Silicon”. DOI: 10.13140/RG.2.1.4405.8088


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APEC’16 (IEEE Applied Power Electronics Conference and Exposition), Long Beach, CA (USA), 20-24

March 2016. http://www.apec-conf.org/

Kulkarni, S.; Pavlovic, Z.; Kubendran, S.; Carretero, C.; Wang N.; Ó Mathúna, C. “Large-Signal Power Circuit Characterization of on-Silicon Coupled Inductors for High Frequency Integrated Voltage Regulation”

Tkachov, S., Agostinelli, M. “A Mixed-Signal Ripple-Based Controller for a 16V, 10MHz Integrated Buck Converter”

AACD’16: 25th Workshop on Advances in Analog Circuit Design, Villach, Austria, 26-28 April 2016. http://www.microelectronicsevents.com/aacd2016/

Allard, B.; Neveu, F.; Martin, C. “Heterogeneous Integration of High-Switching Frequency Inductive Converters”

4.8 Workshops and exhibitions

CNRS Workshop on “Integration in Power Electronics” (24th June 2013) “Power Supply on Chip – The Next Generation of Integrated Power Management”.

Poster @ Univ of Lyon Science & Technology Energy exhibition (http://jsf2013.univ-lyon1.fr/) (in French)

Poster at Infineon AMPS Symposium Graz, 13th - 14th May 2014

JCGE’15 (Jeunes Chercheurs en Génie Électrique), Cherbourg (France), 10-11 June 2015. F. Neveu presentation.

ICECS’14 (21st IEEE Int Conf on Electronic Circuits and Systems), Marseille (France), 7-10 December 2014. F. Neveu poster at WYMPhD Forum

PowerSwipe poster at European Nanoelectronics Forum, 1-2 December, Berlin


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5. Conclusions

The PowerSWIPE consortium has been very active on Communication and Dissemination activities,

including the project Website, the setting up of the LinkedIn group, technical publications and

seminars.

During the course of the project, the Website has attracts a large number of visitors (visitor

counter by nationality is built in the Home page). The Website includes a Feedback section,

however this had been disappointing as no query was ever received.

The Power Supply on Chip LinkedIn group has attracted a large number of members and has been

very useful tool for news, updates and to share information about the project in particular and the

PwrSoC area in general.

The consortium has already presented 30 papers at conferences and workshops, most of which

led to publications in conference Proceedings. Furthermore, the consortium had 10 papers

published in refereed journals.

Finally, the two Professional Development seminars at APEC and the ECPE Workshop were a big

success, and the material developed for this training course can now be used again at other events

or as a stand-alone training course in Europe.

Documents

Deliverable 5.2.2 Final Dissemination Report€¦ · D5.2.2 “Final Dissemination Report”, Apr 2016 2/14 Summary No and name D5.2.2 – Final Dissemination Report1 Status Released