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D E P A R T M E N T O F RapidSmith 2: A Framework for BEL-level CAD Exploration on Xilinx FPGAs FPGA’2015 Feb 22-24 Travis Haroldsen Brent Nelson Brad Hutchings

DEPARTMENT OF RapidSmith 2: A Framework for BEL-level CAD Exploration on Xilinx FPGAs FPGA’2015 Feb…

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F:frame_buf/VGA/r_regVS _rt:#LUT:D=A1 BXINV::#OFF CYINIT:CIN FXMUX::FXOR _BEL_PROP::G::PK_PACKTHRU GNDF:ProtoComp1.GNDF.1 FFY_SR_ATTR:#OFF YUSED:#OFF CYSELG::G COUTUSED::0 ? RapidSmith 1 Limitations 3 RapidSmith uses string attributes to describe slice-level functionality Little information about the types of BELs in a site Hinders BEL-level manipulations

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Page 1: DEPARTMENT OF RapidSmith 2: A Framework for BEL-level CAD Exploration on Xilinx FPGAs FPGA’2015 Feb…

D E P A R T M E N T O F

RapidSmith 2: A Framework for BEL-level CAD Exploration on Xilinx FPGAs

FPGA’2015 Feb 22-24

Travis HaroldsenBrent Nelson

Brad Hutchings

Page 2: DEPARTMENT OF RapidSmith 2: A Framework for BEL-level CAD Exploration on Xilinx FPGAs FPGA’2015 Feb…

RapidSmith 1 Framework for modifying Xilinx XDL designs Contain components and routing of Xilinx chips Supports large number of research topics

including Rapid design prototyping flows Reliability and fault-tolerant techniques PR frameworks Post-PAR debug FPGA security

2

Page 3: DEPARTMENT OF RapidSmith 2: A Framework for BEL-level CAD Exploration on Xilinx FPGAs FPGA’2015 Feb…

F:frame_buf/VGA/r_regVS<4>_rt:#LUT:D=A1

BXINV::#OFF

CYINIT:CIN

FXMUX::FXOR

_BEL_PROP::G::PK_PACKTHRU

GNDF:ProtoComp1.GNDF.1

FFY_SR_ATTR:#OFF

YUSED:#OFFCYSELG::G

COUTUSED::0?RapidSmith 1 Limitations

3

RapidSmith uses string attributes to describe slice-level functionality

Little information about the types of BELs in a site

Hinders BEL-level manipulations

Page 4: DEPARTMENT OF RapidSmith 2: A Framework for BEL-level CAD Exploration on Xilinx FPGAs FPGA’2015 Feb…

RapidSmith 2 Improvements Adds BEL types, properties, and interconnectivity

New BEL-level netlist Tools to convert between

XDL and BEL-level netlist Allows modifying the

packing of a design Provides functionality

for packing, placing, and routing a synthesized netlist onto Xilinx FPGAs

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