DEPpart3

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© R.LauwereinsImec 2001

Digitaldesign

Combina-torialcircuits

Sequentialcircuits

FSMDdesign

VHDL

Course contents

• Digital design• Combinatorial circuits: without statusSequential circuits: with status• FSMD design: hardwired processors• Language based HW design: VHDL

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Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL

Sequential Circuits

• The flip-flop as building block• Design of synchronous sequential circuits• Design of asynchronous sequential circuits• Basic RTL building blocks

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Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL

Sequential Circuits

The flip-flop as building block• Design of synchronous sequential circuits• Design of asynchronous sequential circuits• Basic RTL building blocks

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Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL

The flip-flop as building block

• Definitions: Combinatorial circuit: the output is function of the

current value of the inputs Sequential circuit: the output is function of the

current value of the inputs and of the current state (i.e. also function of the sequence of past inputs)

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Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL

The flip-flop as building block

• Definitions Asynchronous sequential circuits: outputs and state

change as soon as an input changes Synchronous sequential circuits: outputs and state

change only when a special input, the clock, gets a certain value

Clock period: duration between two consecutive 10 transitions of the clock

Clock frequency: 1 / (clock period) Duty cycle: (duration that the clock equals 1) /

(clock period) Rising edge: 01 transition of the clock Falling edge: 10 transition of the clock

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Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL

Sequential Circuits

• The flip-flop as building block SR Latch Gated SR Latch Gated D Latch Flip-flop sensitivity Flip-flop types

• Design of synchronous sequential circuits• Design of asynchronous sequential circuits• Basic RTL building blocks

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Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL

Sequential Circuits



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Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL

SR Latch

Set

Reset

Q’

Q

S

R

Q

Q’

Undefined

S R Q(next)

0 0 Q0 1 0

1 0 1

1 1 NA

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Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL

SR Latch

• Note that a Boolean signal now already consists of 5 values: 0: the logical signal “0” 1: the logical signal “1” x: don’t care Z: high impedant U: undefined

• The oscillation is called critical race• The oscillation only happens when the delay

of both gates is exactly equal• When the delays are not equal, the fastest

gates determines the end result: implementation and run-time dependent undefined

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Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL

SR Latch

Set

Reset

Q

Q’

S R Q(next)

1 1 Q1 0 0

0 1 1

0 0 NA

Set and Reset active low

S

R

Q

Q’

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Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL

Sequential Circuits



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Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL

Gated SR Latch

C S R Q(next)

0 0 0 Q0 0 1 Q

0 1 0 Q

0 1 1 Q

1 0 0 Q

1 0 1 0

1 1 0 1

1 1 1 NA

C=1: follow inputsC=0: latch outputs

Set

Reset

Q’

Q

Clock

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Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL

Sequential Circuits



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Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL

Gated D Latch

C D Q(next)

0 0 Q

0 1 Q

1 0 0

1 1 1

C=1: follow inputC=0: latch output

D

Q’

Q

Clock

DQ delay when C high: L-to-H delay: 2.4+1.4+1.4=5.2H-to-L delay: 1+2.4+1.4=4.8

CQ delay when D high: L-to-H delay: 2.4+1.4+1.4=5.2when D low: H-to-L delay: 2.4+1.4=3.8

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Digitaldesign


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FSMDdesign

VHDL

Gated D Latch

C D Q(next)

0 0 Q

0 1 Q

1 0 0

1 1 1


D

Q’

Q

Clock

D must not change “immediately before” H-to-L of theclock (during the setup time); reason: clock changesbetween the switching of D and of D’ hence Set andReset switch from H to L at the same time undefined(setup time = H-to-L of invertor)

S

R

D

C

S

D’

R

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Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL

Gated D Latch

C D Q(next)

0 0 Q

0 1 Q

1 0 0

1 1 1


D

Q’

Q

Clock

When D switches at least setup time before the clocktransition, S and R will not switch from H to L at thesame time OK (S is longer high than R, hence Q willcome high following the D input)

S

R

D

C

S

D’

R

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Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL

Gated D Latch

C D Q(next)

0 0 Q

0 1 Q

1 0 0

1 1 1


D

Q’

Q

Clock

Analogously, D may not switch “immediately after” H-to-Lof the clock (during the hold time)

S

R

5.2/3.8

D

C

Q

Q’

SymbolGiven values:5.2=C to QLH

3.8=C to QHL

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Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL

Sequential Circuits

• The flip-flop as building block SR Latch Gated SR Latch Gated D Latch Flip-flop sensitivity

Level-sensitive latchMaster-slave flip-flopEdge-triggered flip-flop

Flip-flop types


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Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL

Sequential Circuits



Flip-flop types


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Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL

Level sensitive latch

• All previous gated latches are level sensitive Transparent when clock is high Remembering the last value when clock is low

• Level sensitive latches give problems for shift registers for example The input signal may ripple through multiple stages

during one clock-high phase making it very hard to meet setup/hold time

requirements See next slide

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Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL

Level sensitive latch

X

Clk

4/3D

C

Q1

4/3D

C

Q2

4/3D

C

Q3

Y

Two solutions:• Master-slave• Edge-triggered

Clk

X

Q1

Q2

Q3

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Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL

Sequential Circuits



Flip-flop types


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Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL

Master-slave flip-flop

4/3D

C

Qs1

4/3D

C

Qm1

Master Slave

4/3D

C

Qs2

4/3D

C

Qm2

Master SlaveX Q1

Clk

Y

Clk

X

Qm1

Q1

Qm2

Y

The master clocks at the falling clock edgeThe slave clocks at the rising edge

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Digitaldesign


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FSMDdesign

VHDL

Sequential Circuits



Flip-flop types


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FSMDdesign

VHDL

Edge-triggered flip-flopSet Latch

Reset Latch

Output Latch

Clk

D

Reset

A

Set

B

Q

Q’

Clk

D

B

A

R

S

Q

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Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL

Sequential Circuits


SR flip-flopJK flip-flopD flip-flopT flip-flopAsynchronous set and reset


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FSMDdesign

VHDL

Sequential Circuits




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Digitaldesign


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FSMDdesign

VHDL

SR flip-flop

S

RClk

Q

Q’

Symbol

Triangle next to clockmeans positiveedge-triggered

Negative edge-triggered

S R Q(next)

0 0 Q0 1 0

1 0 1

1 1 NA

Characteristic table(for design of SR flip-flop)

Q Q(next) S R

0 0 0 x0 1 1 0

1 0 0 1

1 1 x 0

Excitation table(for design with SR flip-flop)Positive level triggered

Negative level triggered

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Digitaldesign


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FSMDdesign

VHDL

Sequential Circuits




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Digitaldesign


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FSMDdesign

VHDL

JK flip-flop

J

KClk

Q

Q’

Symbol

J K Q(next)

0 0 Q0 1 0

1 0 1

1 1 Q’

Characteristic table(for design of JK flip-flop)

Q Q(next) J K

0 0 0 x

0 1 1 x

1 0 x 1

1 1 x 0

Excitation table(for design with JK flip-flop)

Circuits that useJK flip-flops are cheaper

than those using SR flip-flops:more don’t cares

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Digitaldesign


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FSMDdesign

VHDL

Sequential Circuits




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Digitaldesign


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FSMDdesign

VHDL

D flip-flop

D

Clk

Q

Q’

Symbol Characteristic table(for design of D flip-flop)

D Q(next)

0 01 1

Excitation table(for design with D flip-flop)

Q Q(next) D

0 0 00 1 1

1 0 0

1 1 1

Designing with D flip-flopis easy

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Digitaldesign


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FSMDdesign

VHDL

Sequential Circuits




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Digitaldesign


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FSMDdesign

VHDL

T flip-flop

T

Clk

Q

Q’

Symbol Characteristic table(for design of T flip-flop)

T Q(next)

0 Q1 Q’

Excitation table(for design with T flip-flop)

Q Q(next) T

0 0 0

0 1 1

1 0 1

1 1 0

D

Clk

Q

Q’

T

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Digitaldesign


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FSMDdesign

VHDL

Sequential Circuits




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Digitaldesign


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FSMDdesign

VHDL

Asynchronous set and reset

Clk

D

Reset

A

Set

B

Q

Q’

Preset

Clear

D

Clk

PRSQ

Q’

CLR

Asynchronous set and reset areuseful to put the flip-flopinitially in a known state

(see lab sessions)

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Digitaldesign


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FSMDdesign

VHDL


• Why are the asynchronous preset and clear connected to both layers of SR-flip-flops? The first layer passes input modifications to the

second layer only at the rising clock edge The second layer reacts immediately, without

waiting for the rising clock edge => needed for asynchronous reaction

If they were only connected to the second layer, the first layer would not know in what state the second layer was put and could give a conflicting command to the second layer at the next rising clock edge, e.g. reset since D=0 and at the same time an asynchronous preset

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Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL


• Why are the asynchronous preset and clear active low? Because ‘wired-or’ of ‘open drain’ circuits is used to

avoid short circuits when there are multiple sources driving them:

Nopreset

preset

Nopreset

preset

R

Open drain

Implements an AND function (hence ‘wired-or’ ...) with unlimited

number of inputs:The bus is only ‘1’

when all inputs to the bus are equal to ‘1’

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Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL

Sequential Circuits

• The flip-flop as building blockDesign of synchronous sequential circuits• Design of asynchronous sequential circuits• Basic RTL building blocks

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Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL

Sequential Circuits

• The flip-flop as building block• Design of synchronous sequential circuits

Finite State Machine (FSM) State-based or Moore-type FSM Input-based or Mealy-type FSM Step 1: State diagram Step 2: State minimization Step 3: State encoding Step 4: Choice of the flip-flop type Step 5: Realization of the combinatorial logic Step 6: Timing analysis

• Design of asynchronous sequential circuits• Basic RTL building blocks

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Digitaldesign


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FSMDdesign

VHDL

Sequential Circuits




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Digitaldesign


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FSMDdesign

VHDL

Finite State Machine

• Design a modulo 4 “Counter”, that counts when the input “CE” (Count Enable) equals 1 and stops counting when the input “CE” equals 0.

• Step 1: translate to a Finite State Machine (FSM):

Count=0

CE=0 CE=0

CE=0CE=0

Count=1CE=1

Count=2

CE=1

Count=3

CE=1

CE=1

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Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL


Count=0

CE=0 CE=0

CE=0CE=0

Count=1CE=1

Count=2

CE=1

Count=3

CE=1

CE=1

Transition to the next state happens at each rising clock edge (a synchronous FSM is clocked!).At each rising clock edge, exactly one transition condition should be true: for each input combination, a transition should be specified in each of the states.

1. We are in state “Count=0”

2. CE input equals 0: we are waiting at the tip of the edge3. CE=1: wait at tip of other edge, but do not count yet!4. Rising clock edge: go to “Count=1”, still with CE=15. CE input becomes 0: wait at tip of other edge6. Rising clock edge: go to “Count=1”, with CE=0

Count=0

CE=0 CE=0

CE=0CE=0

Count=1CE=1

Count=2

CE=1

Count=3

CE=1

CE=1

Count=0

CE=0 CE=0

CE=0CE=0

Count=1CE=1

Count=2

CE=1

Count=3

CE=1

CE=1

Count=0

CE=0 CE=0

CE=0CE=0

Count=1CE=1

Count=2

CE=1

Count=3

CE=1

CE=1

Count=0

CE=0 CE=0

CE=0CE=0

Count=1CE=1

Count=2

CE=1

Count=3

CE=1

CE=1

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Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL


Q1Q0=00

CE=0 CE=0

CE=0CE=0

Q1Q0=01CE=1

Q1Q0=10

CE=1

Q1Q0=11

CE=1

CE=1

• Step 2: Minimise the number of states.It is already the minimum number.

• Step 3: Encode the states:

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Digitaldesign


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VHDL


• Step 4: Select the flip-flop type. We select the D type for its simplicity.

• Step 5: Realise the circuit. See next slides:

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Digitaldesign


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FSMDdesign

VHDL


• Translate the FSM in a next-state table:

Q1Q0=00

CE=0 CE=0

CE=0CE=0

Q1Q0=01CE=1

Q1Q0=10

CE=1

Q1Q0=11

CE=1

CE=1

Present state Next state

Q1Q0 Q1nQ0n

CE=0 CE=100 00 0101 01 1010 10 1111 11 00

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Digitaldesign


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FSMDdesign

VHDL


• Determine the excitation functions:Present state Next state

Q1Q0 Q1nQ0n

CE=0 CE=100 00 0101 01 1010 10 1111 11 00

0 0 1 1

0 1 0 1CE

Q1n=D1

Q0

Q1Q Q(next) D

0 0 00 1 1

1 0 0

1 1 1

Excitation tablefor D flip-flop

D to be appliedis identical to Qn

0 1 1 0

1 0 0 1CE

Q0n=D0

Q0

Q1

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Digitaldesign


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FSMDdesign

VHDL


• Implement:

0 0 1 1

0 1 0 1CE

Q1n=D1

Q0

Q1

0 1 1 0

1 0 0 1CE

Q0n=D0

Q0

Q1

CE Q1 Q0

Q1n

Q0n

D1

Q1

Q’

D0

Q0

Q’

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VHDL


• Step 6: Timing analysisCE Q1 Q0

Q1n

Q0n

D1

Q1

Q’

D0

Q0

Q’

Clk

CE

Q1

Q0

CE Q1 Q0

Q1n

Q0n

D1

Q1

Q’

D0

Q0

Q’

CE Q1 Q0

Q1n

Q0n

D1

Q1

Q’

D0

Q0

Q’

CE Q1 Q0

Q1n

Q0n

D1

Q1

Q’

D0

Q0

Q’

CE Q1 Q0

Q1n

Q0n

D1

Q1

Q’

D0

Q0

Q’

CE Q1 Q0

Q1n

Q0n

D1

Q1

Q’

D0

Q0

Q’

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VHDL

Sequential Circuits




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VHDL

State-based or Moore-type FSM

• Design a modulo 4 “Counter”, that counts when the “CE” input equals 1 and stops counting when “CE” equals 0. The output “Y” equals 1 when the count value equals 3.

• Step 1: translate to FSM:

Count=0Y=0

CE=0 CE=0

CE=0CE=0

Count=1Y=0

CE=1

Count=2Y=0

CE=1

Count=3Y=1

CE=1

CE=1

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Digitaldesign


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FSMDdesign

VHDL


• Be extremely careful about timing issues!! Assume that the Y output is used as a load-enable for a register and as the add/subtract line for an adder/subtractor: when arriving in state 3, Y becomes 1, immediately causing the adder/subtractor to switch to “subtract” mode, but NOT causing the register to load a new value!!! The loading will only occur at the next state transition (i.e. the next clock edge)

CounterCE

Add/Subtract

RegisterLE

A/S’

Clk Clocked

Combinatorial

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Digitaldesign


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FSMDdesign

VHDL


• State-based: the output is indicated for each state the output is only function of the current state, not

of the inputs applied Hence, the output value is indicated in the circle

representing the state

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Digitaldesign


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VHDL


Q1Q0=00Y=0

CE=0 CE=0

CE=0CE=0

Q1Q0=01Y=0

CE=1

Q1Q0=10Y=0

CE=1

Q1Q0=11Y=1

CE=1

CE=1

• Step 2: Minimise the number of states. This is already the minimum number.


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VHDL


• Translate the FSM in a next-state table:

Q1Q0=00Y=0

CE=0 CE=0

CE=0CE=0

Q1Q0=01Y=0

CE=1

Q1Q0=10Y=0

CE=1

Q1Q0=11Y=1

CE=1

CE=1

Present state Next state Outputs

Q1Q0 Q1nQ0n YCE=0 CE=1

00 00 01 001 01 10 010 10 11 011 11 00 1

Y isonly

dependenton thecurrentstate,not on

the inputs

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Digitaldesign


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FSMDdesign

VHDL


• Determine the excitation functions:

0 0 1 1

0 1 0 1CE

Q1n=D1

Q0

Q1

Q Q(next) D

0 0 00 1 1

1 0 0

1 1 1



0 1 1 0

1 0 0 1CE

Q0n=D0

Q0

Q1

Present state Next state Outputs

Q1Q0 Q1nQ0n Y

CE=0 CE=1

00 00 01 0

01 01 10 010 10 11 0

11 11 00 1

0 0

0 1

Y

Q1

Q0

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Digitaldesign


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FSMDdesign

VHDL


• Implement:

0 0 1 1

0 1 0 1CE

Q1n=D1

Q0

Q1

0 1 1 0

1 0 0 1CE

Q0n=D0

Q0

Q1

CE Q1 Q0

Q1n

Q0n

D1

Q1

Q’

D0

Q0

Q’

0 0

0 1

Y

Q1

Q0

Y

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Digitaldesign


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VHDL


• Step 6: Timing analysisCE Q1 Q0

Q1n

Q0n

D1

Q1

Q’

D0

Q0

Q’

Y

Clk

CEQ1

Q0

Y

CE Q1 Q0

Q1n

Q0n

D1

Q1

Q’

D0

Q0

Q’

Y

CE Q1 Q0

Q1n

Q0n

D1

Q1

Q’

D0

Q0

Q’

Y

CE Q1 Q0

Q1n

Q0n

D1

Q1

Q’

D0

Q0

Q’

Y

CE Q1 Q0

Q1n

Q0n

D1

Q1

Q’

D0

Q0

Q’

Y

CE Q1 Q0

Q1n

Q0n

D1

Q1

Q’

D0

Q0

Q’

Y

Danger for Glitch!

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Digitaldesign


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VHDL


• Is a glitch harmful? When the output with the glitch is connected to the

clock of some clocked circuit:

This clocked circuit will unintentionally clock: harmful

Hard to debug: glitch may disappear when probe is connected due to increased capacitance and hence also increased delay

When the output with the glitch is connected to a combinatorial circuit that eventually is the input of a register:

Not harmful, since the register looks at its input only at the clock edge

Dissipates unnecessary power

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Digitaldesign


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Sequential Circuits




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Digitaldesign


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VHDL

Input-based or Mealy-type FSM

• Design a modulo 4 “Counter”, that counts when the “CE” input equals 1 and stops counting when “CE” equals 0. The “Y” output value equals 1 when the count=3 while the input “CE” equals 1.

• Step 1: translate to FSM:

Count=0

CE=0/Y=0 CE=0/Y=0

CE=0/Y=0CE=0/Y=0

Count=1CE=1/Y=0

Count=2

CE=1/Y=0

Count=3

CE=1/Y=0

CE=1/Y=1

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Digitaldesign


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VHDL


Count=0

CE=0/Y=0 CE=0/Y=0

CE=0/Y=0CE=0/Y=0

Count=1CE=1/Y=0

Count=2

CE=1/Y=0

Count=3

CE=1/Y=0

CE=1/Y=1

Transition to the next state happensat each rising clock edge

1. We are in state “Count=2”

2. CE input equals 1: wait at tip of edge with Y=03. Rising clock edge: go to “Count=3”, still with CE=1: Y=14. C input becomes 0: wait at tip of other edge with Y=0;

combinatorial circuit driven by Y reacts, clocked don’t

5. Rising clock edge: Y=0 is clocked into output register

Count=0

CE=0/Y=0 CE=0/Y=0

CE=0/Y=0CE=0/Y=0

Count=1CE=1/Y=0

Count=2

CE=1/Y=0

Count=3

CE=1/Y=0

CE=1/Y=1

Count=0

CE=0/Y=0 CE=0/Y=0

CE=0/Y=0CE=0/Y=0

Count=1CE=1/Y=0

Count=2

CE=1/Y=0

Count=3

CE=1/Y=0

CE=1/Y=1

Count=0

CE=0/Y=0 CE=0/Y=0

CE=0/Y=0CE=0/Y=0

Count=1CE=1/Y=0

Count=2

CE=1/Y=0

Count=3

CE=1/Y=0

CE=1/Y=1

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VHDL


• Be extremely careful about timing issues!! Assume that the Y output is used as a load-enable for a register and as the add/subtract line for an adder/subtractor: when arriving in state 3 with CE=1, Y becomes 1 adder/subtractor switches to “subtract”, but register doesn’t load new value!!! When CE=0, Y becomes 0 adder/subtractor switches to “add”, and LE=0. When the next clock edge comes while CE=0, register will not load.

CounterCE

Add/Subtract

RegisterLE

A/S’

Clk Clocked

Combinatorial

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VHDL


• Input-based: the output is specified for each state and each

combination of inputs in that state the output is function of the current state, and of

the applied inputs Hence the output is specified next to each

transition

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Digitaldesign


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FSMDdesign

VHDL


Q1Q0=00

CE=0/Y=0 CE=0/Y=0

CE=0/Y=0CE=0/Y=0

Q1Q0=01CE=1/Y=0

Q1Q0=10

CE=1/Y=0

Q1Q0=11

CE=1/Y=0

CE=1/Y=1

• Step 2: Minimise the number of states. This is already the minimum number.


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VHDL


• Translate FSM to next-state table:

Q1Q0=00

CE=0/Y=0 CE=0/Y=0

CE=0/Y=0CE=0/Y=0

Q1Q0=01CE=1/Y=0

Q1Q0=10

CE=1/Y=0

Q1Q0=11

CE=1/Y=0

CE=1/Y=1

Present state Next state/Outputs

Q1Q0 Q1nQ0n/YCE=0 CE=1

00 00/0 01/001 01/0 10/010 10/0 11/011 11/0 00/1

Y doesnot onlydependon thecurrentstate,

but also onthe inputs

3/69


Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL


• Determine the excitation functions:

0 0 1 1

0 1 0 1CE

Q1n=D1

Q0

Q1

Q Q(next) D

0 0 00 1 1

1 0 0

1 1 1



0 1 1 0

1 0 0 1CE

Q0n=D0

Q0

Q1

Present state Next state/Outputs

Q1Q0 Q1nQ0n/YCE=0 CE=1

00 00/0 01/001 01/0 10/010 10/0 11/011 11/0 00/1

0 0 0 0

0 0 1 0CE

Y

Q0

Q1

3/70


Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL


• Implement:

0 0 1 1

0 1 0 1CE

Q1n=D1

Q0

Q1

0 1 1 0

1 0 0 1CE

Q0n=D0

Q0

Q1

CE Q1 Q0

Q1n

Q0n

D1

Q1

Q’

D0

Q0

Q’

0 0 0 0

0 0 1 0CE

Y

Q0

Q1

Y

3/71


Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL


• Step 6: Timing analysis

Clk

CEQ1

Q0

Y

CE Q1 Q0

Q1n

Q0n

D1

Q1

Q’

D0

Q0

Q’

Y

CE Q1 Q0

Q1n

Q0n

D1

Q1

Q’

D0

Q0

Q’

Y

CE Q1 Q0

Q1n

Q0n

D1

Q1

Q’

D0

Q0

Q’

Y

CE Q1 Q0

Q1n

Q0n

D1

Q1

Q’

D0

Q0

Q’

Y

Danger for Glitch!

CE Q1 Q0

Q1n

Q0n

D1

Q1

Q’

D0

Q0

Q’

Y

CE Q1 Q0

Q1n

Q0n

D1

Q1

Q’

D0

Q0

Q’

Y

CE Q1 Q0

Q1n

Q0n

D1

Q1

Q’

D0

Q0

Q’

Y

3/72


Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL

State-based model

D

Clk

Q

S*=F(S,I)

NextState

Combi-nato-rial

Logic

O=H(S)

OutputCombi-nato-rial

Logic

D

Clk

Q

D

Clk

Q

Clock Next State S*

CurrentState S

Outputs O

Inputs I

3/73


Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL

Input-based model

D

Clk

Q

S*=F(S,I)

NextState

Combi-nato-rial

Logic

O=H(S,I)

OutputCombi-nato-rial

Logic

D

Clk

Q

D

Clk

Q

Clock Next State S* CurrentState S

Outputs O

Inputs I

3/74


Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL

Sequential Circuits




3/75


Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL

Step 1: construction of the FSM

• The first step in the design of synchronous sequential circuits is the construction of the FSM starting from the description in natural language (ambiguous and incomplete)

• Example: Modulo-3 up/down counter Count enable (C):

C=1: countC=0: do not count

Direction (D):D=1: count downD=0: count up

Output (Y): Y=1 when (count equals 2 and we count up) or when (count equals 0 and we count down)

What is the meaning of “We count up”?Do we have to “count” (C=1) and “up” (D=0)or is it sufficient that the direction is “up”

(C=X and D=0)?Ambiguous; I choose for the first

3/76


Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL


• First step: is this a State-based or an Input-based design? It is Input-based, since the output depends on the

state and the input

• Second step: construct the FSM starting from the first state, for each combination of inputs from each state See next slide Note: when an output needs to remain high during

several consecutive states, it should be assigned a ‘high’ value in each of these states!! Each output should be assigned a value in each state!

3/77


Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL


u0

CD=0XY=0

CD=0XY=0

CD=0XY=0

u2

CD=10Y=0

CD=0XY=0

CD=10Y=1

CD=0XY=0

CD=0XY=0

CD=11Y=0

CD=11Y=1

d2

CD=11Y=1

CD=10Y=1

CD=11Y=0

d0

CD=11Y=0

u1

CD=10Y=0

CD=10Y=0

d1

CD=11Y=0

CD=10Y=0

3/78


Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL

Sequential Circuits




3/79


Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL

Step 2: minimise the number of states

• Goal: less states means less flip-flops• Principal: equivalent behavior of two FSMs• Two FSMs are equivalent when they produce

the same output sequence for the same input sequence

3/80


Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL


• Two states in an FSM may be replaced by 1 state when both states produce the same outputs for the same inputs and when both jump to equivalent next states for the same inputs

• Formally: states sj and sk are equivalent (sjsk) if and only if iI: h(sj,i)=h(sk,i): both states produce the same

output for each combination of inputsand iI: f(sj,i)f(sk,i): the next states are equivalent for

each input combination

3/81


Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL


• In practice: build the next state table out of the state diagram first

NEXT STATE / OUTPUTPRESENTSTATE CD=0X CD=10 CD=11

u0 u0/0 u1/0 d2/1u1 u1/0 u2/0 d0/0u2 u2/0 u0/1 d1/0d0 d0/0 u1/0 d2/1d1 d1/0 u2/0 d0/0d2 d2/0 u0/1 d1/0

3/82


Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL


• Construct the implication table: 1 square per combination of 2 states


u0 u0/0 u1/0 d2/1u1 u1/0 u2/0 d0/0u2 u2/0 u0/1 d1/0d0 d0/0 u1/0 d2/1d1 d1/0 u2/0 d0/0d2 d2/0 u0/1 d1/0u1

u2

d0

d1

d2

u0 u1 u2 d0 d1

3/83


Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL


• Delete all combinations that have different outputs for the same inputs


u0 u0/0 u1/0 d2/1u1 u1/0 u2/0 d0/0u2 u2/0 u0/1 d1/0d0 d0/0 u1/0 d2/1d1 d1/0 u2/0 d0/0d2 d2/0 u0/1 d1/0u1

u2

d0

d1

d2

u0 u1 u2 d0 d1

3/84


Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL


• Indicate for the remaining which next states have to be equivalent to make the current states equivalent


u0 u0/0 u1/0 d2/1u1 u1/0 u2/0 d0/0u2 u2/0 u0/1 d1/0d0 d0/0 u1/0 d2/1d1 d1/0 u2/0 d0/0d2 d2/0 u0/1 d1/0

u1

u2

d0

d1

d2

u0 u1 u2 d0 d1

OKOK

OK

OK

OK

OK

Minimum numberof states: 3 ie.

{u0,d0}=s0

{u1,d1}=s1

{u2,d2}=s2

3/85


Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL


• Construct the new next state tableNEXT STATE / OUTPUTPRESENT

STATE CD=0X CD=10 CD=11u0 u0/0 u1/0 d2/1u1 u1/0 u2/0 d0/0u2 u2/0 u0/1 d1/0d0 d0/0 u1/0 d2/1d1 d1/0 u2/0 d0/0d2 d2/0 u0/1 d1/0


{u0,d0}=s0

{u1,d1}=s1

{u2,d2}=s2


s0 s0/0 s1/0 s2/1s1 s1/0 s2/0 s0/0

s2 s2/0 s0/1 s1/0

3/86


Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL


• FYI: draw new state diagramNEXT STATE / OUTPUTPRESENT

STATE CD=0X CD=10 CD=11s0 s0/0 s1/0 s2/1s1 s1/0 s2/0 s0/0

s2 s2/0 s0/1 s1/0

s0

CD=0XY=0

s1

CD=10Y=0

CD=11Y=0

CD=0XY=0

s2

CD=10Y=0

CD=11Y=0

CD=0XY=0

CD=10Y=1

CD=11Y=1

This could have been constructed from the begin-ning, but better 1 state too much than too little

3/87


Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL


• This example did not show how you should manipulate the implication table

• Hence an imaginary example showing all problems:

NEXT STATE / OUTPUTPRESENTSTATE AB=00 AB=01 AB=10

s0 s4/1 s2/0 s1/1s1 s2/0 s5/1 s4/1

s2 s1/1 s0/0 s3/1

s3 s2/0 s5/1 s4/1

s4 s0/0 s5/1 s1/1s5 s2/0 s4/1 s2/1

3/88


Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL


• Construct the implication table: 1 square per combination of 2 states


s0 s4/1 s2/0 s1/1s1 s2/0 s5/1 s4/1

s2 s1/1 s0/0 s3/1

s3 s2/0 s5/1 s4/1

s4 s0/0 s5/1 s1/1s5 s2/0 s4/1 s2/1

s1

s2

s3

s4

s5

s0 s1 s2 s3 s4

3/89


Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL


• Delete all combinations with different outputs for same inputs


s0 s4/1 s2/0 s1/1s1 s2/0 s5/1 s4/1

s2 s1/1 s0/0 s3/1

s3 s2/0 s5/1 s4/1

s4 s0/0 s5/1 s1/1s5 s2/0 s4/1 s2/1

s1

s2

s3

s4

s5

s0 s1 s2 s3 s4

3/90


Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL


• Indicate for the remaining which next states have to be equivalent to make the current states equivalent


s0 s4/1 s2/0 s1/1s1 s2/0 s5/1 s4/1

s2 s1/1 s0/0 s3/1

s3 s2/0 s5/1 s4/1

s4 s0/0 s5/1 s1/1s5 s2/0 s4/1 s2/1

s1

s2

s3

s4

s5

s0 s1 s2 s3 s4

1-41-31-41-3

OK

1-41-3

0-2

OK

1-41-3

4-52-4

0-2

OK

1-41-3

4-52-4

0-20-21-4

OK

1-41-3

4-52-4

4-52-4

0-20-21-4

OK

1-41-3

4-52-4

4-52-4

0-2, 4-51-2

0-20-21-4

OK

3/91


Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL

1-41-3

4-52-4

4-52-4

0-2, 4-51-2

0-20-21-4

OK


• Delete those states that are equivalent when non-equivalent next states would have been equivalent


s0 s4/1 s2/0 s1/1s1 s2/0 s5/1 s4/1

s2 s1/1 s0/0 s3/1

s3 s2/0 s5/1 s4/1

s4 s0/0 s5/1 s1/1s5 s2/0 s4/1 s2/1

s1

s2

s3

s4

s5

s0 s1 s2 s3 s4

1-4: ?1-3:OK

4-52-4

4-52-4

0-2, 4-51-2

0-20-21-4

OK

1-4: ?1-3:OK

4-52-4

4-52-4

0-2, 4-51-2

0-2: ?0-21-4

OK

1-4: ?1-3:OK

4-52-4

4-52-4

0-2, 4-51-2

0-2: ?0-21-4

OK

1-4: ?1-3:OK

4-52-4

4-52-4

0-2, 4-51-2

0-2: ?0-2: ?1-4: ?

OK

1-4: ?1-3:OK

4-52-4

4-52-4

0-2, 4-51-2

0-2: ?0-2: ?1-4: ?

OK

1-4: ?1-3:OK

4-52-4

4-52-4

0-2, 4-51-2

0-2: ?0-2: ?1-4: ?

OK

3/92


Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL


• Delete again as long as states are deleted during an iteration


s0 s4/1 s2/0 s1/1s1 s2/0 s5/1 s4/1

s2 s1/1 s0/0 s3/1

s3 s2/0 s5/1 s4/1

s4 s0/0 s5/1 s1/1s5 s2/0 s4/1 s2/1

s1

s2

s3

s4

s5

s0 s1 s2 s3 s4

1-4: ?1-3:OK

4-52-4

4-52-4

0-2, 4-51-2

0-2: ?0-2: ?1-4: ?

OK

1-4: ?1-3:OK

4-52-4

4-52-4

0-2, 4-51-2

0-2: ?0-2: ?1-4: ?

OK

1-4: ?1-3:OK

4-52-4

4-52-4

0-2, 4-51-2

0-2: ?0-2: ?1-4: ?

OK

1-4: ?1-3:OK

4-52-4

4-52-4

0-2, 4-51-2

0-2: ?0-2: ?1-4: ?

OK Minimum numberof states: 3 ie.

{s0,s2}=u0

{s1,s3,s4}=u1

{s5}=u2

3/93


Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL


• Construct the new next state tableNEXT STATE / OUTPUTPRESENT

STATE AB=00 AB=01 AB=10s0 s4/1 s2/0 s1/1s1 s2/0 s5/1 s4/1

s2 s1/1 s0/0 s3/1

s3 s2/0 s5/1 s4/1

s4 s0/0 s5/1 s1/1s5 s2/0 s4/1 s2/1


{s0,s2}=u0

{s1,s3,s4}=u1

{s5}=u2


u0 u1/1 u0/0 u1/1u1 u0/0 u2/1 u1/1u2 u0/0 u1/1 u0/1

3/94


Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL

Sequential Circuits




3/95


Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL

Step 3: State encoding

• n states require at least log2n flip-flops.

• There are n! possible encodings (n choices for the first state, n-1 for the second, etc.)

No. s0 s1 s2 s3 No. s0 s1 s2 s3

1 00 01 10 11 13 10 00 01 112 00 01 11 10 14 10 00 11 013 00 10 01 11 15 10 01 00 11

4 00 10 11 01 16 10 01 11 00

5 00 11 01 10 17 10 11 00 01

6 00 11 10 01 18 10 11 01 007 01 00 10 11 19 11 00 01 10

8 01 00 11 10 20 11 00 10 01

9 01 10 00 11 21 11 01 00 10

10 01 10 11 00 22 11 01 10 0011 01 11 00 10 23 11 10 00 01

12 01 11 10 00 24 11 10 01 00

3/96


Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL

Step 3: State encoding

• Does the chosen encoding matters? Yes. Each choice leads to a different combinatorial

circuit with different cost and delay.

• Often chosen encodings: Straightforward Minimum-bit-change One-hot

3/97


Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL

Step 3: State encoding: Straightforward

• Straightforward encoding uses the binary representation of the state number as code (s0000, s5101, …)

• Straightforward encoding is mostly used when the state number has a physical meaning E.g. a counter whose count value is sent to a

display

• Straightforward encoding is dangerous for glitches and leads to non-minimal area and power consumption: multiple bits have to change at each state transition (multiple bit-changes seldomly happen concurrently; each bit-change requires some logic to implement it; each bit-change consumes power)

3/98


Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL

Step 3: State encoding: Straightforward


s0 s0/0 s1/0 s2/1s1 s1/0 s2/0 s0/0

s2 s2/0 s0/1 s1/0


00 00/0 01/0 10/1

01 01/0 10/0 00/0

10 10/0 00/1 01/0

3/99


Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL

Step 3: State encoding:Minimum-bit-change

• For minimum-bit-change encoding we assign the codes such that the total number of bit-changes for all state transitions is minimal

• Minimum-bit-change encoding is mostly used when area and power need to be minimized (CMOS)

00 01

1011

1

1

22

00 01

1110

1

1

11

Straightforward Minimum-bit-change

Gray codecounter

3/100


Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL

Step 3: State encoding:Minimum-bit-change

0 1

2

All transitions are equally likelyPreferrably only 1 bit difference between each pair of transitions

This can only be realised between two of the three pairs

Possibleencoding:

s0=00s1=10s2=11


s0 s0/0 s1/0 s2/1s1 s1/0 s2/0 s0/0

s2 s2/0 s0/1 s1/0


00 00/0 10/0 11/1

10 10/0 11/0 00/0

11 11/0 00/1 10/0

3/101


Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL

Step 3: State encoding:One-hot

• Each state has 1 flip-flop, hence no encoding; Q of 1 FF =1, Q of others=0

• Flip-flop cost = O(n) i.o. O(logn), hence only useful for small number of states: controller

• Very easy to realise: short design time (time-to-market, e.g. exam…)

• Very small combinatorial circuits to drive the inputs of the flip-flops: cheap combinatorial part, more expensive flip-flop part An FPGA possesses per half CLB a small

combinatorial circuit and 1 flip-flop: one-hot encoding is ideal for FPGA implementations (except counters: too many states)

3/102


Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL


One-hot encodings0=001s1=010s2=100


s0 s0/0 s1/0 s2/1s1 s1/0 s2/0 s0/0

s2 s2/0 s0/1 s1/0


001 001/0 010/0 100/1

010 010/0 100/0 001/0

100 100/0 001/1 010/0

3/103


Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL


CD=10Y=1

s0

CD=0XY=0

s1

CD=10Y=0

CD=11Y=0

CD=0XY=0

s2

CD=10Y=0

CD=11Y=0

CD=0XY=0

CD=11Y=1

CD

Y

s0

CD=0XY=0

s1

CD=10Y=0

CD=11Y=0

CD=0XY=0

s2

CD=10Y=0

CD=11Y=0

CD=0XY=0

s0

CD=0XY=0

s1

CD=10Y=0

CD=11Y=0

CD=0XY=0

s2

CD=10Y=0

CD=11Y=0

CD=0XY=0

s0

CD=0XY=0

s1

CD=10Y=0

CD=11Y=0

CD=0XY=0

s2

CD=10Y=0

CD=11Y=0

CD=0XY=0

s0

CD=0XY=0

s1

CD=10Y=0

CD=11Y=0

CD=0XY=0

s2

CD=10Y=0

CD=11Y=0

CD=0XY=0

s0

CD=0XY=0

s1

CD=10Y=0

CD=11Y=0

CD=0XY=0

s2

CD=10Y=0

CD=11Y=0

CD=0XY=0

Q0

DQ1

DQ2

DP C C

s0

CD=0XY=0

s1

CD=10Y=0

CD=11Y=0

CD=0XY=0

s2

CD=10Y=0

CD=11Y=0

CD=0XY=0

s0

CD=0XY=0

s1

CD=10Y=0

CD=11Y=0

CD=0XY=0

s2

CD=10Y=0

CD=11Y=0

CD=0XY=0

s0

CD=0XY=0

s1

CD=10Y=0

CD=11Y=0

CD=0XY=0

s2

CD=10Y=0

CD=11Y=0

CD=0XY=0

s0

CD=0XY=0

s1

CD=10Y=0

CD=11Y=0

CD=0XY=0

s2

CD=10Y=0

CD=11Y=0

CD=0XY=0

s0

CD=0XY=0

s1

CD=10Y=0

CD=11Y=0

CD=0XY=0

s2

CD=10Y=0

CD=11Y=0

CD=0XY=0

s0

CD=0XY=0

s1

CD=10Y=0

CD=11Y=0

CD=0XY=0

s2

CD=10Y=0

CD=11Y=0

CD=0XY=0

s0

CD=0XY=0

s1

CD=10Y=0

CD=11Y=0

CD=0XY=0

s2

CD=10Y=0

CD=11Y=0

CD=0XY=0

s0

CD=0XY=0

s1

CD=10Y=0

CD=11Y=0

CD=0XY=0

s2

CD=10Y=0

CD=11Y=0

CD=0XY=0

CD=11Y=1

CD=10Y=1

3/104


Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL


• Implementation rule for One-hot with D flip-flop: Each arriving transition at a state needs an AND

gate

3/105


Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL


CD=10Y=1

s0

CD=0XY=0

s1

CD=10Y=0

CD=11Y=0

CD=0XY=0

s2

CD=10Y=0

CD=11Y=0

CD=0XY=0

CD=11Y=1

Q0

S RQ1

S RQ2

S R

CD

Y

CD=10Y=1

s0

CD=0XY=0

s1

CD=10Y=0

CD=11Y=0

CD=0XY=0

s2

CD=10Y=0

CD=11Y=0

CD=0XY=0

CD=11Y=1

CD=10Y=1

s0

CD=0XY=0

s1

CD=10Y=0

CD=11Y=0

CD=0XY=0

s2

CD=10Y=0

CD=11Y=0

CD=0XY=0

CD=11Y=1

P C C

CD=10Y=1

s0

CD=0XY=0

s1

CD=10Y=0

CD=11Y=0

CD=0XY=0

s2

CD=10Y=0

CD=11Y=0

CD=0XY=0

CD=11Y=1

CD=10Y=1

s0

CD=0XY=0

s1

CD=10Y=0

CD=11Y=0

CD=0XY=0

s2

CD=10Y=0

CD=11Y=0

CD=0XY=0

CD=11Y=1

CD=10Y=1

s0

CD=0XY=0

s1

CD=10Y=0

CD=11Y=0

CD=0XY=0

s2

CD=10Y=0

CD=11Y=0

CD=0XY=0

CD=11Y=1

CD=10Y=1

s0

CD=0XY=0

s1

CD=10Y=0

CD=11Y=0

CD=0XY=0

s2

CD=10Y=0

CD=11Y=0

CD=0XY=0

CD=11Y=1

CD=10Y=1

s0

CD=0XY=0

s1

CD=10Y=0

CD=11Y=0

CD=0XY=0

s2

CD=10Y=0

CD=11Y=0

CD=0XY=0

CD=11Y=1

CD=10Y=1

s0

CD=0XY=0

s1

CD=10Y=0

CD=11Y=0

CD=0XY=0

s2

CD=10Y=0

CD=11Y=0

CD=0XY=0

CD=11Y=1

CD=10Y=1

s0

CD=0XY=0

s1

CD=10Y=0

CD=11Y=0

CD=0XY=0

s2

CD=10Y=0

CD=11Y=0

CD=0XY=0

CD=11Y=1

CD=10Y=1

s0

CD=0XY=0

s1

CD=10Y=0

CD=11Y=0

CD=0XY=0

s2

CD=10Y=0

CD=11Y=0

CD=0XY=0

CD=11Y=1

3/106


Digitaldesign


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FSMDdesign

VHDL


• Implementation rule for One-hot with SR flip-flop: Each arriving transition starting at another state

requires an AND gate at the S input Each departing transition to another state requires

an AND gate at the R input

3/107


Digitaldesign


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FSMDdesign

VHDL

Sequential Circuits




3/108


Digitaldesign


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FSMDdesign

VHDL

Step 4: Choice of the flip-flop type

• JK flip-flop Most expensive flip-flop Most difficult design Largest number of don’t cares: probably cheapest

(and fastest) combinatorial control logic Used when a different signal sets resp. resets the

flip-flop

• SR flip-flop Cheap flip-flop Difficult design Many don’t cares: probably cheap (and fast) control

logic Used when a different signal sets resp. resets the

flip-flop

3/109


Digitaldesign


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FSMDdesign

VHDL


• D flip-flop Cheap flip-flop Most easy design No don’t cares: probably most expensive (and

slowest) combinatorial control logic Used when the same signal sets resp. resets the

flip-flop, i.e. when the value of a signal has to be remembered temporarily

• T flip-flop Cheap flip-flop Easy design No don’t cares: probably most espensive (and

slowest) combinatorial control logic Used for counters and frequency dividers: fast

toggling

3/110


Digitaldesign


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FSMDdesign

VHDL


• No fixed selection rule exists When we want the cheapest circuit, all variants

have to be tried out When the fastest design time is needed, D flip-flops

are the best choice FPGAs only possess D flip-flops

3/111


Digitaldesign


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VHDL

Sequential Circuits




3/112


Digitaldesign


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FSMDdesign

VHDL

Step 5: Realization of the combinatorial logic: D flip-flop

• Determine the excitation functions

Q Q(next) D

0 0 00 1 1

1 0 0

1 1 1



0 0 x 0

0 0 x 0

Y

Q0

Q1

1 0 x 0

0 0 x 1C

D

0 0 x 1

0 0 x 1

Q1n=D1

Q0

Q1

1 0 x 0

0 1 x 0C

D

0 1 x 0

0 1 x 0

Q0n=D0

Q0

Q1

0 0 x 1

1 0 x 0C

D


00 00/0 01/0 10/1

01 01/0 10/0 00/0

10 10/0 00/1 01/0

3/113


Digitaldesign


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VHDL

Step 5: Realization of the combinatorial logic: D flip-flop

0 0 x 0

0 0 x 0

Y

Q0

Q1

1 0 x 0

0 0 x 1C

D

0 0 x 1

0 0 x 1

Q1n=D1

Q0

Q1

1 0 x 0

0 1 x 0C

D

0 1 x 0

0 1 x 0

Q0n=D0

Q0

Q1

0 0 x 1

1 0 x 0C

D

Q1

DQ0

D

CD

YCost: 35

1.5 CLB

Clr Clr

3/114


Digitaldesign


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FSMDdesign

VHDL

Step 5: Realization of the combinatorial logic: T flip-flop


Q Q(next) T

0 0 0

0 1 11 0 11 1 0

Excitation tablefor T flip-flop

0 0 x 0

0 0 x 0

Y

Q0

Q1

1 0 x 0

0 0 x 1C

D

0 0 x 0

0 0 x 0

T1

Q0

Q1

1 0 x 1

0 1 x 1C

D

0 0 x 0

0 0 x 0

T0

Q0

Q1

0 1 x 1

1 1 x 0C

D


00 00/0 01/0 10/1

01 01/0 10/0 00/0

10 10/0 00/1 01/0

3/115


Digitaldesign


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VHDL

0 0 x 0

0 0 x 0

T0

Q0

Q1

0 1 x 1

1 1 x 0C

D

0 0 x 0

0 0 x 0

T1

Q0

Q1

1 0 x 1

0 1 x 1C

D

Step 5: Realization of the combinatorial logic: T flip-flop

0 0 x 0

0 0 x 0

Y

Q0

Q1

1 0 x 0

0 0 x 1C

D

Q1

TQ0

T

CD

YCost: 32

Clr Clr

3/116


Digitaldesign


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FSMDdesign

VHDL

Step 5: Realization of the combinatorial logic: SR flip-flop


Excitation tablefor SR flip-flop


00 00/0 01/0 10/1

01 01/0 10/0 00/0

10 10/0 00/1 01/0

Q Q(next) S R

0 0 0 x

0 1 1 0

1 0 0 1

1 1 x 0

S1

Q0

Q1

C

D

R1

Q0

Q1

C

D


00 00/0 01/0 10/101 01/0 10/0 00/010 10/0 00/1 01/0

Q Q(next) S R

0 0 0 x

0 1 1 0

1 0 0 1

1 1 x 0

0

0

x

x


00 00/0 01/0 10/101 01/0 10/0 00/010 10/0 00/1 01/0

Q Q(next) S R

0 0 0 x

0 1 1 0

1 0 0 1

1 1 x 0

0 0

0 0

x x

x x


00 00/0 01/0 10/101 01/0 10/0 00/010 10/0 00/1 01/0

Q Q(next) S R

0 0 0 x

0 1 1 0

1 0 0 1

1 1 x 0

0 0 x

0 0 x

x x 0

x x 0


00 00/0 01/0 10/101 01/0 10/0 00/010 10/0 00/1 01/0

Q Q(next) S R

0 0 0 x

0 1 1 0

1 0 0 1

1 1 x 0

0 0 x

0 0 x

0

x x 0

x x 0

x


00 00/0 01/0 10/101 01/0 10/0 00/010 10/0 00/1 01/0

Q Q(next) S R

0 0 0 x

0 1 1 0

1 0 0 1

1 1 x 0

0 0 x

0 0 x

0 1

x x 0

x x 0

x 0


00 00/0 01/0 10/101 01/0 10/0 00/010 10/0 00/1 01/0

Q Q(next) S R

0 0 0 x

0 1 1 0

1 0 0 1

1 1 x 0

0 0 x

0 0 x

0 1 0

x x 0

x x 0

x 0 1


00 00/0 01/0 10/101 01/0 10/0 00/010 10/0 00/1 01/0

Q Q(next) S R

0 0 0 x

0 1 1 0

1 0 0 1

1 1 x 0

0 0 x

0 0 x

1 0 0

0 1 0

x x 0

x x 0

0 x 1

x 0 1

0 0 x x

0 0 x x

1 0 x 0

0 1 x 0

x x x 0

x x x 0

0 x x 1

x 0 x 1

3/117


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VHDL



Excitation tablefor SR flip-flop


00 00/0 01/0 10/1

01 01/0 10/0 00/0

10 10/0 00/1 01/0

Q Q(next) S R

0 0 0 x0 1 1 0

1 0 0 1

1 1 x 0

S0

Q0

Q1

C

D

R0

Q0

Q1

C

D


00 00/0 01/0 10/101 01/0 10/0 00/010 10/0 00/1 01/0

0 x 0

0 x 0

x 0 x

x 0 x


00 00/0 01/0 10/101 01/0 10/0 00/010 10/0 00/1 01/0

0 x 0

0 x 0

1 0 0

x 0 x

x 0 x

0 1 x


00 00/0 01/0 10/101 01/0 10/0 00/010 10/0 00/1 01/0

0 x 0

0 x 0

0 0 1

1 0 0

x 0 x

x 0 x

x 1 0

0 1 x

0 x x 0

0 x x 0

0 0 x 1

1 0 x 0

x 0 x x

x 0 x x

x 1 x 0

0 1 x x

0 0 x 0

0 0 x 0

Y

Q0

Q1

1 0 x 0

0 0 x 1C

D


00 00/0 01/0 10/101 01/0 10/0 00/010 10/0 00/1 01/0

3/118


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VHDL


S1

Q0

Q1

C

D

R1

Q0

Q1

C

D

0 0 x x

0 0 x x

1 0 x 0

0 1 x 0

x x x 0

x x x 0

0 x x 1

x 0 x 1

Q1

S RQ0

S R

CD

CC

3/119


Digitaldesign


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VHDL


S0

Q0

Q1

C

D

R0

Q0

Q1

C

D

Q1

S RQ0

S R

CD

CC

0 x x 0

0 x x 0

0 0 x 1

1 0 x 0

x 0 x x

x 0 x x

x 1 x 0

0 1 x x

3/120


Digitaldesign


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VHDL


S0

Q0

Q1

C

D

R0

Q0

Q1

C

D

Q1

S RQ0

S R

CD

CC

0 x x 0

0 x x 0

0 0 x 1

1 0 x 0

x 0 x x

x 0 x x

x 1 x 0

0 1 x x

0 0 x 0

0 0 x 0

Y

Q0

Q1

1 0 x 0

0 0 x 1C

D

Y Cost: 32

3/121


Digitaldesign


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VHDL

Step 5: Realization of the combinatorial logic: JK flip-flop


Excitation tablefor JK flip-flop


00 00/0 01/0 10/1

01 01/0 10/0 00/0

10 10/0 00/1 01/0

Q Q(next) J K

0 0 0 x

0 1 1 x

1 0 x 1

1 1 x 0

J1

Q0

Q1

C

D

K1

Q0

Q1

C

D


00 00/0 01/0 10/101 01/0 10/0 00/010 10/0 00/1 01/0

Q Q(next) J K

0 0 0 x

0 1 1 x

1 0 x 1

1 1 x 0

0

0

x

x

0 0

0 0

x x

x x


00 00/0 01/0 10/101 01/0 10/0 00/010 10/0 00/1 01/0

Q Q(next) J K

0 0 0 x

0 1 1 x

1 0 x 1

1 1 x 0

0 0 x

0 0 x

x x 0

x x 0


00 00/0 01/0 10/101 01/0 10/0 00/010 10/0 00/1 01/0

Q Q(next) J K

0 0 0 x

0 1 1 x

1 0 x 1

1 1 x 0

0 0 x

0 0 x

0 1 x

x x 0

x x 0

x x 1


00 00/0 01/0 10/101 01/0 10/0 00/010 10/0 00/1 01/0

Q Q(next) J K

0 0 0 x

0 1 1 x

1 0 x 1

1 1 x 0

0 0 x

0 0 x

1 0 x

0 1 x

x x 0

x x 0

x x 1

x x 1


00 00/0 01/0 10/101 01/0 10/0 00/010 10/0 00/1 01/0

0 0 x x

0 0 x x

1 0 x x

0 1 x x

x x x 0

x x x 0

x x x 1

x x x 1


00 00/0 01/0 10/101 01/0 10/0 00/010 10/0 00/1 01/0

3/122


Digitaldesign


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VHDL



Excitation tablefor JK flip-flop


00 00/0 01/0 10/1

01 01/0 10/0 00/0

10 10/0 00/1 01/0

Q Q(next) J K

0 0 0 x

0 1 1 x

1 0 x 1

1 1 x 0

J0

Q0

Q1

C

D

K0

Q0

Q1

C

D


00 00/0 01/0 10/101 01/0 10/0 00/010 10/0 00/1 01/0

0 x 0

0 x 0

x 0 x

x 0 x

0 x 0

0 x 0

1 x 0

x 0 x

x 0 x

x 1 x


00 00/0 01/0 10/101 01/0 10/0 00/010 10/0 00/1 01/0

0 x 0

0 x 0

0 x 1

1 x 0

x 0 x

x 0 x

x 1 x

x 1 x


00 00/0 01/0 10/101 01/0 10/0 00/010 10/0 00/1 01/0

0 x x 0

0 x x 0

0 x x 1

1 x x 0

x 0 x x

x 0 x x

x 1 x x

x 1 x x


00 00/0 01/0 10/101 01/0 10/0 00/010 10/0 00/1 01/0

0 0 x 0

0 0 x 0

Y

Q0

Q1

1 0 x 0

0 0 x 1C

D

3/123


Digitaldesign


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VHDL


J1

Q0

Q1

C

D

K1

Q0

Q1

C

D

Q1

J KQ0

J K

CD

CC

0 0 x x

0 0 x x

1 0 x x

0 1 x x

x x x 0

x x x 0

x x x 1

x x x 1

3/124


Digitaldesign


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VHDL


J0

Q0

Q1

C

D

K0

Q0

Q1

C

D

Q1

J KQ0

J K

CD

CC

0 x x 0

0 x x 0

0 x x 1

1 x x 0

x 0 x x

x 0 x x

x 1 x x

x 1 x x

0 0 x 0

0 0 x 0

Y

Q0

Q1

1 0 x 0

0 0 x 1C

D

Y Cost: 26

3/125


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Sequential Circuits




3/126


Digitaldesign


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FSMDdesign

VHDL

Step 6: Timing analysis

• Determine maximum clock frequency Max. clock frequency = 1/(delay of critical path) Critical path is the path with the longest

combinatorial delay between two clock edges Example:

Q1

DQ0

D

CD

Y

Clr ClrQ1

DQ0

D

CD

Y

Clr Clr

3/127


Digitaldesign


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FSMDdesign

VHDL

Step 6: Timing analysis• Delay of critical path (assume zero

connection delay): clockQ0 + invertor + 4-input AND + 3-input OR +

setup Dclock = 5.2 + 1.0 + (2.2+1.0) + (1.8+1.0) + 1.0 = 13.2

ns (assuming that our relative times can be considered to be nanoseconds)

fmax = 76 MHz (same assumption)

Q1

DQ0

D

CD

Y

Clr Clr

3/128


Digitaldesign


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FSMDdesign

VHDL

Step 6: Timing analysis

• After designing the combinatorial circuits for next state and output, all traditional design steps follow: Technology mapping Placement and routing Timing simulation

• Timing simulation is even more important for sequential circuits than for combinatorial circuits Determine the maximum clock frequency to check

whether setup and hold times are satisfied Avoid, if necessary because of connected circuits,

glitches when a state transition involves multiple bit-flips

3/129


Digitaldesign


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VHDL

Sequential Circuits

• The flip-flop as building block• Design of synchronous sequential circuitsDesign of asynchronous sequential circuits• Basic RTL building blocks

3/130


Digitaldesign


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VHDL

Sequential Circuits

• The flip-flop as building block• Design of synchronous sequential circuits• Design of asynchronous sequential circuits

Definitions and Fundamental Mode Restriction Design

• Basic RTL building blocks

3/131


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Sequential Circuits




3/132


Digitaldesign


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VHDL

Asynchronous Sequential Circuits

• Definitions: Sequential circuit: the output is function of the

current value of the inputs and of the current state (i.e. also function of the sequence of past inputs)

Asynchronous sequential circuits: outputs and state change as soon as an input changes

• Fundamental mode restriction: only one input may change at a time; the next input

change may only occur when all effects to the previous input change died out

• Goal: design of small asynchronous circuits, e.g. interfaces between two synchronous islands with not-correlated clocks or clocks with unpredictable clock skew

3/133


Digitaldesign


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Sequential Circuits




3/134


Digitaldesign


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VHDL

Example circuit: requirements

• Design a circuit with two inputs (I and E) and one output Q. If E is high, a rising edge on I causes Q to go high. Q stays high until E goes low. While E is low, Q is low.

3/135


Digitaldesign


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VHDL

Design flow

State table

State transition diagram

Primitive flow table

Minimized flow table

State assignment

Elimination of critical races

Hazard free combinatorial design

Avoidance of input skew

3/136


Digitaldesign


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VHDL

Design flow

State table




State assignment




3/137


Digitaldesign


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VHDL

State table

• List all states: each possible combination of inputs and outputs is a state

Q I E State

0 0 0 a0 0 1 b0 1 0 c0 1 1 d1 0 0 impossible1 0 1 e1 1 0 impossible

1 1 1 f

3/138


Digitaldesign


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VHDL

Design flow

State table




State assignment




3/139


Digitaldesign


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VHDL


Q I E State


1 1 1 fa/0

00

e/0

01

IE

f/0

11

b/0

01

d/0

11

c/0

10

11

01

01

00

11

10

10

10 00 01

1100

Q I E State


1 1 1 f

Q I E State


1 1 1 f

Q I E State


1 1 1 f

Q I E State


1 1 1 f

Q I E State


1 1 1 f

Q I E State


1 1 1 f

Q I E State


1 1 1 f

Q I E State


1 1 1 f

Q I E State


1 1 1 f

Q I E State


1 1 1 f

Q I E State


1 1 1 f

Q I E State


1 1 1 f

Q I E State


1 1 1 f

Q I E State


1 1 1 f

Q I E State


1 1 1 f

Q I E State


1 1 1 f

Q I E State


1 1 1 f

Q I E State


1 1 1 f

We opted for aMoore or state

based design; wecould as well have

chosen a Mealyapproach, with

output pertransition

3/140


Digitaldesign


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VHDL

Design flow

State table




State assignment




3/141


Digitaldesign


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VHDL


Q I E State


1 1 1 f

Q I E State


1 1 1 f

Q I E State


1 1 1 f

Q I E State


1 1 1 f

Q I E State


1 1 1 f

Q I E State


1 1 1 f

Q I E State


1 1 1 f

Q I E State


1 1 1 f

Q I E State


1 1 1 f

Q I E State


1 1 1 f

Q I E State


1 1 1 f

Q I E State


1 1 1 f

Q I E State


1 1 1 f

Q I E State


1 1 1 f

Q I E State


1 1 1 f

Q I E State


1 1 1 f

Q I E State


1 1 1 f

Q I E State


1 1 1 f

Q I E State


1 1 1 f

SIE00 01 11 10 Q

a a x 0bcdef

SIE00 01 11 10 Q

a a x 0b b x 0cdef

SIE00 01 11 10 Q

a a x 0b b x 0c x c 0def

SIE00 01 11 10 Q

a a x 0b b x 0c x c 0d x d 0ef

SIE00 01 11 10 Q

a a x 0b b x 0c x c 0d x d 0e e x 1f

SIE00 01 11 10 Q

a a x 0b b x 0c x c 0d x d 0e e x 1f x f 1

SIE00 01 11 10 Q

a a b x 0b b x 0c x c 0d x d 0e e x 1f x f 1

SIE00 01 11 10 Q

a a b x c 0b b x 0c x c 0d x d 0e e x 1f x f 1

SIE00 01 11 10 Q

a a b x c 0b a b x 0c x c 0d x d 0e e x 1f x f 1

SIE00 01 11 10 Q

a a b x c 0b a b f x 0c x c 0d x d 0e e x 1f x f 1

SIE00 01 11 10 Q

a a b x c 0b a b f x 0c a x c 0d x d 0e e x 1f x f 1

SIE00 01 11 10 Q

a a b x c 0b a b f x 0c a x d c 0d x d 0e e x 1f x f 1

SIE00 01 11 10 Q

a a b x c 0b a b f x 0c a x d c 0d x d c 0e e x 1f x f 1

SIE00 01 11 10 Q

a a b x c 0b a b f x 0c a x d c 0d x b d c 0e e x 1f x f 1

SIE00 01 11 10 Q

a a b x c 0b a b f x 0c a x d c 0d x b d c 0e a e x 1f x f 1

SIE00 01 11 10 Q

a a b x c 0b a b f x 0c a x d c 0d x b d c 0e a e f x 1f x f 1

SIE00 01 11 10 Q

a a b x c 0b a b f x 0c a x d c 0d x b d c 0e a e f x 1f x f c 1

SIE00 01 11 10 Q

a a b x c 0b a b f x 0c a x d c 0d x b d c 0e a e f x 1f x e f c 1

3/142


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Design flow

State table




State assignment




3/143


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VHDL


• Rule: merge compatible states: states with same next states and outputs or don’t cares

• ‘Compatibility’ is not associative!(a compatible b) AND (a compatible c) does NOT induce (b compatible c)

• Note that minimizing the number of states of synchronous circuits requires equivalence instead of compatibility. States with same outputs and equivalent next

states ‘Equivalence’ is associative!

3/144


Digitaldesign


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VHDL


SIE00 01 11 10 Q


Are a and b compatible?SIE00 01 11 10 Q


SIE00 01 11 10 Q

f c 0c x d c 0d x d c 0e e f x 1f x e f c 1

YES, hence merge them

3/145


Digitaldesign


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VHDL


Are c and d compatible?S

IE00 01 11 10 Q


YES, hence merge themS

IE00 01 11 10 Q


SIE00 01 11 10 Q

f 0 0e e f x 1f x e f 1

3/146


Digitaldesign


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VHDL


Are e and f compatible?

YES, hence merge them

SIE00 01 11 10 Q

f 0 0e e f x 1f x e f 1

SIE00 01 11 10 Q

f 0 0e e f x 1f x e f 1

SIE00 01 11 10 Q

0 0 1

This minimized flow tableis called the

Transition Table

3/147


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Design flow

State table




State assignment




3/148


Digitaldesign


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VHDL

State assignment

SIE00 01 11 10 Q

0 0 1

Assume we make followingstraightforward

state assignment:: 00: 01: 11

SIE00 01 11 10 Q

00 00 00 11 01 001 00 00 01 01 011 00 11 11 01 1

3/149


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VHDL

State assignment

SIE00 01 11 10 Q

00 00 00 11 01 001 00 00 01 01 011 00 11 11 01 1

0 0 0 x

0 0 1 xE

S0n

S0

S1

1 1 1 x

1 1 1 xI

0 0 0 x

0 0 1 xE

S1n

S0

S1

1 0 1 x

0 0 0 xI 0 0

x 1

S0

S1

3/150


Digitaldesign


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VHDL

State assignment

0 0 0 x

0 0 1 xE

S0n

S0

S1

1 1 1 x

1 1 1 xI

0 0 0 x

0 0 1 xE

S1n

S0

S1

1 0 1 x

0 0 0 xI 0 0

x 1

S0

S1

I E S1 S0

Q

3/151


Digitaldesign


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VHDL

State assignment

I E S1 S0

Q

SIE00 01 11 10 Q

00 00 00 11 01 001 00 00 01 01 011 00 11 11 01 1

Let’s animate behav from state S=00 with inputs IE=01->11Step 1: Stable state S=00 with inputs IE=01Step 2: Inputs change to IE=11

I E S1 S0

Q

I E S1 S0

Q

SIE00 01 11 10 Q

00 00 00 11 01 001 00 00 01 01 011 00 11 11 01 1

SIE00 01 11 10 Q

00 00 00 11 01 001 00 00 01 01 011 00 11 11 01 1

I E S1 S0

Q

SIE00 01 11 10 Q

00 00 00 11 01 001 00 00 01 01 011 00 11 11 01 1

Step 3: after 2-input gate delay, OR-gate switches,making S0=1No Step 4: we are stuck in stable state S=01 becauseboth state bits did not change at the same timeThe fact that 2 or more state variables have to change,when 1 input-bit changes is called a RACE CONDITIONWhen this leads to the wrong final state,it’s called a CRITICAL RACE

3/152


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Design flow

State table




State assignment




3/153


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VHDL


• Solution: make the state assignment such that never 2 or more state variables need to change following a single input change

SIE00 01 11 10 Q

0 0 1

SIE00 01 11 10 Q

0 0 1

SIE00 01 11 10 Q

0 0 1

SIE00 01 11 10 Q

0 0 1

No encoding can be found satisfying the above rule!

00 01

11

3/154


Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL


• Do the state assignment as good as you can. Use additional states to solve the problems that remain

SIE00 01 11 10 Q

00 00 00 11 01 001 00 00 01 01 011 00 11 11 01 1

Highlight remaining problems

Route these transitions via an additional state, whichdiffers in only one state variable

SIE00 01 11 10 Q

00 00 00 11 01 001 00 00 01 01 011 00 11 11 01 1

SIE00 01 11 10 Q

00 00 00 10 01 001 00 00 01 01 011 10 11 11 01 110 00 x 11 x x

Don’t care because bothnew transitions require

an output change: itis not important whetherthis already happens inthe intermediate state

3/155


Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL


SIE00 01 11 10 Q

00 00 00 10 01 001 00 00 01 01 011 10 11 11 01 110 00 x 11 x x

0 0 0 0

0 0 1 xE

S0n

S0

S1

0 1 1 1

1 1 1 xI

0 0 1 0

0 0 1 xE

S1n

S0

S1

1 0 1 1

0 0 0 xI 0 0

x 1

S0

S1

3/156


Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL


0 0 0 0

0 0 1 xE

S0n

S0

S1

0 1 1 1

1 1 1 xI

0 0 1 0

0 0 1 xE

S1n

S0

S1

1 0 1 1

0 0 0 xI 0 0

x 1

S0

S1

I E S1 S0

Q

3/157


Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL


SIE00 01 11 10 Q

00 00 00 10 01 001 00 00 01 01 011 10 11 11 01 110 00 x 11 x x

What happens at power-up?

The circuit could as well start in state S=10 with aninput of IE=01

It then depends on the actual values of the don’t careswhat is going to happen; it could even remain stablein that state...

It would hence be wise to remove the don’t cares andreplace them with an evolution to a stable state withthe same inputs

SIE00 01 11 10 Q

00 00 00 10 01 001 00 00 01 01 011 10 11 11 01 110 00 00 11 01 x

Race, but not critical

3/158


Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL

Design flow

State table




State assignment




3/159


Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL


• The combinatorial circuits of an asynchronous design should be designed in a hazard free way Static hazard: a status variable that is supposed not

to change, briefly changes; this could lead to a wrong final state

Dynamic hazard: a status variable that is supposed to change just once, changes three times; this could lead to a wrong final state

• Synchronous designs do not need to be hazard free, since state variables are only taken into account on a clock edge

• Our design was hazard free, and hence should not be changed

3/160


Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL

Design flow

State table




State assignment




3/161


Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL


• Assume that input I is skewed on the bottom AND gate with respect to the other inputs

I E S1 S0

Q

Delay

SIE00 01 11 10 Q

00 00 00 10 01 001 00 00 01 01 011 10 11 11 01 110 00 11 11 01 1

Start in state S=01 with IE=11

I becomes 0: S should go to 00

SIE00 01 11 10 Q

00 00 00 10 01 001 00 00 01 01 011 10 11 11 01 110 00 11 11 01 1

I E S1 S0

Q

I E S1 S0

Q

SIE00 01 11 10 Q

00 00 00 10 01 001 00 00 01 01 011 10 11 11 01 110 00 11 11 01 1

I E S1 S0

Q

I E S1 S0

Q

I E S1 S0

Q

I E S1 S0

Q

I E S1 S0

Q

I E S1 S0

Q

Now the delayed version of Igoes to zero

State however does not changeanymore and ends in theincorrect S=11

State variables may change only after all inputchanges are applied to all gates!

I E S1 S0

Q

I E S1 S0

Q

I E S1 S0

Q

I E S1 S0

Q

3/162


Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL

Sequential Circuits

• The flip-flop as building block• Design of synchronous sequential circuits• Design of asynchronous sequential circuitsBasic RTL building blocks

3/163


Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL

Sequential Circuits


Registers Shift registers Counters

Synchronous countersAsynchronous counters

Register files LIFO queue (push down stack) FIFO queue

3/164


Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL

Sequential Circuits





3/165


Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL

Registers

• Register

D Q D Q D Q D Q

Clk

I3 I2 I1 I0

Q3 Q2 Q1 Q0

Register

I3 I2 I1 I0

Q3Q2 Q1 Q0

Symbol

3/166


Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL

Registers

• Asynchronously presettable and clearable Register

D Q D Q D Q D Q

Clk

I3 I2 I1 I0

Q3 Q2 Q1 Q0

Preset

Clear

Register

I3 I2 I1 I0

Q3Q2 Q1 Q0

SymbolPreset

Clear

3/167


Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL

D Q D Q D Q D Q

Clk

I3 I2 I1 I0

Q3 Q2 Q1 Q0

1 0S

Load

1 0S

1 0S

1 0S

Registers

• Loadable register (without gated clock)

• Loads only when “Load=1”• High power dissipation: multiple gates switch whenever the clock changes• No clock skew problems since each flip-flop is clocked by the master clock

3/168


Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL

Register

I3 I2 I1 I0

Q3Q2 Q1 Q0

SymbolLoad

Registers

• Loadable register (without gated clock)

3/169


Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL

D Q D Q D Q D Q

Clk

I3 I2 I1 I0

Q3 Q2 Q1 Q0

Registers

• Loadable register (with gated clock)

• Clocks only when “CE=1”• Low power dissipation: gates only switch when a newvalue is loaded• Gated clocks (derived clocks) are sensitive to clockskew

CE

3/170


Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL

Registers

• Loadable register (with gated clock)

Register

I3 I2 I1 I0

Q3Q2 Q1 Q0

SymbolCE

3/171


Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL

Registers

• Clock skew problem for gated clocks: Not all clocks of all registers

change concurrently Expected behavior:

New I3..0 applied

At next clock edge:Clk*11, Clk*21 Q*3..0A3..0, A*3..0I3..0

Real behavior:

New I3..0 applied

At next clock edge:Clk*11 A*3..0I3..0, Clk*21Q*3..0A*3..0

Risk for setup violation

Register 1

I3 I2 I1 I0

Register 2

Q3Q2 Q1 Q0

CEA3..0

3/172


Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL

Registers

D0 Q0 D1 Q1

I A Q

Clk

CE

Clk

I

A

CE

GatedClk

Q

D0 Q0 D1 Q1

I A Q

Clk

CE

D0 Q0 D1 Q1

I A Q

Clk

CE

D0 Q0 D1 Q1

I A Q

Clk

CE

Possible setup or hold violation for 2nd flip-flop

D0 Q0 D1 Q1

I A Q

Clk

CE

3/173


Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL

Registers

• What causes clock skew? Gated clocks Different relative routing delay

On PCB and within chip: different wire length

In FPGA: different number of routing switches

• Delay depends on many things: temperature, power supply voltage, fan-out, IC

batch under no circumstance clock skew may cause

problems!!! worst case analysis (e.g. min-delay for data path and max-delay for clock path and vice versa)

3/174


Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL

Sequential Circuits





3/175


Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL

Shift registers

• Serial-in/parallel-out shift register (SIPO)

D Q D Q D Q D Q

Clk

IL

Q3 Q2 Q1 Q0

1 0S

SE

1 0S

1 0S

1 0S

Example of utilization:Receive register (Rx) serial portDelay line for FIR and IIR filters

3/176


Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL

Shift registers

• Serial-in/parallel-out shift register (SIPO)

Shift Register

Q3Q2 Q1 Q0

SymbolSE

IL

3/177


Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL

Shift registers

• Parallel-in/serial-out shift register (PISO)

D Q D Q D Q D Q

Clk

IL

Q0

1 0S

Sh/Ld

1 0S

1 0S

1 0S

Example of utilization: Transmit register (Tx) serial port

I3 I2 I1 I0

CE

3/178


Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL

Shift registers

• Parallel-in/serial-out shift register (PISO)

ShiftRegister

I3 I2 I1 I0

Q0

SymbolIL

CESh/Ld’

3/179


Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL

Sequential Circuits





3/180


Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL

Synchronous counters

• Synchronous up-counter

D Q D Q

Clk Q1 Q0

Clear

D Q

Q2Outputcarry

HAHAHA

E

Synchronous because all flip-flops are clocked by thesame signal

3/181


Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL


ClkQ1 Q0Q2

Outputcarry

D Q D QD Q

HAHAHA

E

Clear

ClkClear

EQ0

Q1

Q2

D Q D QD Q

HAHAHA

D Q D QD Q

HAHAHA

D Q D QD Q

HAHAHA

D Q D QD Q

HAHAHA

D Q D QD Q

HAHAHA

D Q D QD Q

HAHAHA

D Q D QD Q

HAHAHA

Glitch!

D Q D QD Q

HAHAHA

D Q D QD Q

HAHAHA

D Q D QD Q

HAHAHA

D Q D QD Q

HAHAHA

D Q D QD Q

HAHAHA

D Q D QD Q

HAHAHA

3/182


Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL


• Synchronous up/down-counter

D Q D Q

Clk Q1 Q0

Clear

D Q

Q2Outputcarry

E

HASHASHAS

D

CiCo

Half adder/subtractor

3/183


Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL


• Design of the Half adder/subtractor

HAS

Dci

Qi

Di

co

Behavior:When ci=0 then Di=Qi (no counting)When ci=1 this section should toggleC0 has to be 1 when the next section

has to toggle. When should this happen?

Up-count000110110001…

Next section togglesat 10 of this section

Down-count001110010011…

Next section togglesat 01 of this section

3/184


Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL



Up-count000110110001…

Next sectiontoggles at 10of this section

Down-count001110010011…




Up-count000110110001…


Down-count001110010011…


c i Dir Qi Di c i+1

0 0 0 0 0

0 0 1 1 0

0 1 0 0 0

0 1 1 1 0

1 0 0 1 0

1 0 1 0 1

1 1 0 1 1

1 1 1 0 0



Up-count000110110001…


Down-count001110010011…


c i Dir Qi Di c i+1

0 0 0 0 0

0 0 1 1 0

0 1 0 0 0

0 1 1 1 0

1 0 0 1 0

1 0 1 0 1

1 1 0 1 1

1 1 1 0 0



Up-count000110110001…


Down-count001110010011…


c i Dir Qi Di c i+1

0 0 0 0 0

0 0 1 1 0

0 1 0 0 0

0 1 1 1 0

1 0 0 1 0

1 0 1 0 1

1 1 0 1 1

1 1 1 0 0



3/185


Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL



c i Dir Qi Di c i+1

0 0 0 0 00 0 1 1 0

0 1 0 0 0

0 1 1 1 0

1 0 0 1 0

1 0 1 0 1

1 1 0 1 1

1 1 1 0 0

0 1 1 0

1 0 0 1ci

DirQi

Di

0 0 0 0

0 1 0 1ci

DirQi

ci+1

ci

DirQi

Di ci+1

3/186


Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL


• Parallel loadable up/down-counter

Clk Q1

Clear

D Q

Q2Outputcarry

E

HASHASHAS

D

CiCo

01

D Q

01

Q0

D Q

01

I2 I1 I0

Load

3/187


Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL


• BCD up-counter

Up-counter

I3 I2 I1 I0

Q3Q2 Q1 Q0ELoad

0 0 0 0

Compares with constant:When count equals ‘1001’ (i.e. 9), ‘0000’ is loaded at next clock edge

3/188


Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL


• BCD up/down-counter

Up/down-counter

I3 I2 I1 I0

Q3Q2 Q1 Q0ELoad

Mux

0 0 0 01 0 0 1

1 0

D

3/189


Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL

Sequential Circuits





3/190


Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL

Asynchronous counters

T Q T Q T Q T Q

Clk Q3 Q2 Q1 Q0

Clear

E

Q’Q’Q’Q’

Clk

Q0

Q1

Q2

Q3

T Q T Q T Q T Q

Clk Q3 Q2 Q1 Q0

Clear

E

Q’Q’Q’Q’

T Q T Q T Q T Q

Clk Q3 Q2 Q1 Q0

Clear

E

Q’Q’Q’Q’

T Q T Q T Q T Q

Clk Q3 Q2 Q1 Q0

Clear

E

Q’Q’Q’Q’

T Q T Q T Q T Q

Clk Q3 Q2 Q1 Q0

Clear

E

Q’Q’Q’Q’

T Q T Q T Q T Q

Clk Q3 Q2 Q1 Q0

Clear

E

Q’Q’Q’Q’

T Q T Q T Q T Q

Clk Q3 Q2 Q1 Q0

Clear

E

Q’Q’Q’Q’

T Q T Q T Q T Q

Clk Q3 Q2 Q1 Q0

Clear

E

Q’Q’Q’Q’

T Q T Q T Q T Q

Clk Q3 Q2 Q1 Q0

Clear

E

Q’Q’Q’Q’

T Q T Q T Q T Q

Clk Q3 Q2 Q1 Q0

Clear

E

Q’Q’Q’Q’

T Q T Q T Q T Q

Clk Q3 Q2 Q1 Q0

Clear

E

Q’Q’Q’Q’

T Q T Q T Q T Q

Clk Q3 Q2 Q1 Q0

Clear

E

Q’Q’Q’Q’

T Q T Q T Q T Q

Clk Q3 Q2 Q1 Q0

Clear

E

Q’Q’Q’Q’

T Q T Q T Q T Q

Clk Q3 Q2 Q1 Q0

Clear

E

Q’Q’Q’Q’

T Q T Q T Q T Q

Clk Q3 Q2 Q1 Q0

Clear

E

Q’Q’Q’Q’

T Q T Q T Q T Q

Clk Q3 Q2 Q1 Q0

Clear

E

Q’Q’Q’Q’

T Q T Q T Q T Q

Clk Q3 Q2 Q1 Q0

Clear

E

Q’Q’Q’Q’

T Q T Q T Q T Q

Clk Q3 Q2 Q1 Q0

Clear

E

Q’Q’Q’Q’

T Q T Q T Q T Q

Clk Q3 Q2 Q1 Q0

Clear

E

Q’Q’Q’Q’

3/191


Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL

Sequential Circuits





3/192


Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL

Register files

D QWE

Din

ClkRE

Dout

Register File Cell (RFC)This implementation dissipates much power due to theactive memorization of data, but does not suffer fromclock skew problems.

Combining ‘WE’ with ‘Clk’ into a gated clock, we canreduce the power dissipation

D QDout

WE

Din

ClkRE

Note that in both cases,‘writing’ is clocked, but‘reading’ is not clocked!Needed for critical-path

computation...

3/193


Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL

Register files

RFC RFC RFC RFC

RFC RFC RFC RFC

RFC RFC RFC RFC

RFC RFC RFC RFC

0

1

2

3

0

1

2

3

I0I1I2I3

O0O1O2O3

2-to-4writedec

2-to-4readdec

WA1

WA0

WE

RA1

RA0

RE

3/194


Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL

Sequential Circuits





3/195


Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL

LIFO queue - stack

Top

Top-1

Top-2

Top-3

Top-4

Top-5

Top-6

Top-7

empty

empty

empty

empty

empty

empty

empty

empty

1. Reset45

empty

empty

empty

empty

empty

empty

empty

2. Push 45

12

45

empty

empty

empty

empty

empty

empty

3. Push 124. Push 23

23

12

45

empty

empty

empty

empty

empty

5. Pop -> 23

12

45

empty

empty

empty

empty

empty

empty

6. Push 10

10

12

45

empty

empty

empty

empty

empty

3/196


Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL

LIFO queue - stack

Enable Push/pop’ Operations

0 0 No change0 1 No change

1 0 Pop

1 1 Push

Using left/right’ shift register

ResetL/R’Enable

IL IR

O0O7

and counter for indicationempty/full

Count Empty Full

0000 1 00001 0 0

0010 0 0

0011 0 0

0100 0 0

0101 0 0

0110 0 0

0111 0 0

1000 0 1

3/197


Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL

LIFO queue - stack

ResetL/R’Enable

IL IR

O0O7

ResetL/R’Enable

IL IR

O0O7

ResetUp/down’Enable Q3..0

0

0

Enable

Reset’

Push/pop’

In0

In7

Out0

Out7

Empty

Full

3/198


Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL

LIFO queue - stack

Alternative implementation: for large stacks

0

1

2

3

Write Ptr

Read Ptr

empty

empty

23

45 2

1

3. Push 23

Does not shift!

empty

12

23

45 3

2

4. Push 12

2. Push 45

empty

empty

empty

45 1

0

At ‘Push’ both ptrs

count up

5. Pop -> 12

empty

empty

23

45 2

1At ‘Pop’

both ptrs

count down

6. Push 17

empty

17

23

45 3

2

1. Reset

empty

empty

empty

empty 0

3

0=empty

7. Push 52

52

17

23

45 0

3

0=full

3/199


Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL

LIFO queue - stack

RU/D’E

Up/downcounterWrite ptr

SU/D’E

Up/downcounterRead ptr

2-to-1MUX

1Kx8RAM

A

CS

R/W’

D

10

1

0S

8

Watch timing of the enable: when RAM is not clockedbe careful not to read/write twice since the counterscount further

Reset’

Push/Pop’

Enable

Full/empty

Datain/out

Note:SET

3/200


Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL

Sequential Circuits





3/201


Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL

FIFO queue

Top

Top-1

Top-2

Top-3

Top-4

Top-5

Top-6

Top-7

empty

empty

empty

empty

empty

empty

empty

empty

1. Reset45

empty

empty

empty

empty

empty

empty

empty

2. Write 4523

45

empty

empty

empty

empty

empty

empty

3. Write 23

12

23

45

empty

empty

empty

empty

empty

4. Write 12

12

23

empty

empty

empty

empty

empty

empty

5. Read -> 45

57

12

23

empty

empty

empty

empty

empty

6. Write 57

3/202


Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL

FIFO queue

Reset

Enable

IL

O0O7

Reset

Enable

IL

O0O7

SetUp/down’Enable Q3..0

Enable

Reset’Read/write’

In0

In7Uit0

Uit7

Empty

Full

7

0

7

0 S2..0

S2..0

Readpointer

3/203


Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL

FIFO queue

Alternative implementation: for large FIFO’s

0

1

2

3

Write Ptr

Read Ptr

empty

empty

empty

empty 0

0

1. Reset2. Write 45

empty

empty

empty

45 1

0

Only write pointer incr.

at write

empty

empty

23

45 2

0

3. Write 23

Does not shift!

empty

12

23

45 3

0

4. Write 12

empty

12

23

empty 3

1

5. Read -> 45

Only read pointer incr.

at read

6. Write 57

57

12

23

empty 0

1

Wrap-around

7. Write 16

57

12

23

16 1

1

Read and write pointer equal: empty

or full

3/204


Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL

FIFO queue

• Previous implementation indicates empty/full but does not distinguish between both

• Solution: assume queue depth equals 2n

read and write pointer are hence n-bit up-counters select however an (n+1)-bit up-counter:

n-LSB of read and write equal: empty/fullMSB equal: emptyMSB different: fullapply only the n-LSB as address for RAM-

queue• For the stack, we also did not differentiate

between empty and full; how can it be solved there?

3/205


Digitaldesign


Sequentialcircuits

FSMDdesign

VHDL

FIFO queue

RE

11-bit UpcounterWrite ptr

RE

11-bit UpcounterRead ptr

2-to-1MUX

1Kx8RAM

A

CS

R/W’

D

10

0

1S

8

Reset’Read/Write’

Enable

Empty

Datain/out

=?

FullMSB

10-LSB

Documents

DEPpart3