DESIGN AND SIMULATION OF INTEGRATEDEMI FILTER

Jens Werner∗, Jennifer Schutt†, Guido Notermans†

∗Jade University of Applied Science Wilhelmshaven/Oldenburg/Elsfleth,Friedrich-Paffrath-Str. 101, D-26389 Wilhelmshaven, Email: jens.werner@jade-hs.de

†NXP Semiconductors Germany GmbH, Stresemannallee 101, D-22529 HamburgEmail: jennifer.schuett@nxp.com, guido.notermans@nxp.com

KEYWORDS

EM simulation, planar coils, method of moments, lumpedmodel, common mode filter, USB 2.0, ESD protection, EMI

ABSTRACT

The design and simulation of an integrated common modefilter (CMF) for differential data lines, like the USB 2.0interface, is presented in this paper. The device is manufac-tured in a bipolar semiconductor process for the integration ofdiodes protecting sensitive CMOS circuits against damage byElectrostatic Discharge (ESD). The filter is formed by planarcoupled coils that are processed in copper/polyimide layersapplied on top of silicon die. The design process is using 2.5Dsimulation techniques based on method of moments. Further-more a lumped model is derived that allows exact and efficienttransient simulations in SPICE [1] based simulators. The filterdesign itself shows strong common mode rejection in the GSMspectrum. The small size (1.34 mm x 0.95 mm) of the devicemakes it well suited for integration in modern mobile phoneapplications, to suppress electromagnetic interference (EMI)between a USB transmitter and a GSM receiver. Measurementdata demonstrates the EMI protection in the GSM downlinkspectrum. The dynamic resistance of the ESD diodes is derivedin transmission line puls (TLP) measurements.

INTRODUCTION

Even though the specification of the USB 3.0 standard hasbeen released in 2008, the adoption rate in the smartphoneworld is very low and USB 2.0 is still the dominant wirebased interface for data exchange and for charging of mobilephones. With a natural data rate of 480 Mbit/s in high-speedmode, a certain spectral power density can be detected around960 MHz due to harmonic content of the digital signals. This isdepicted in Fig. 1: Multiple spurious signals close by the largerspur at 960 MHz appear as common mode component on aUSB cable. The data on USB lines is NRZI (non-return-to-zero) encoded and bit stuffing is applied to ensure that data andclock are synchroneous at the USB receiver. This allows datatransmission without seperate clock lines. The nature of theencoded data stream creates additional spectral components

below 960 MHz. In the standard GSM-900 system, 124 down-link channels are located between 935 MHz and 960 MHz.The extended system (E-GSM) adds additional channels atthe lower end between 925 MHz and 935 MHz. The receivedsignal strength can be close to the minimum sensitivity level of-102 dBm [2], e.g. in a rural area (with large distance betweenthe transmitting base station and a mobile phone) or inside abuilding with shielding walls. Any additional noise from theinternal USB interface that falls into the 200 kHz spectrum ofa specific GSM downlink channel, will directly degrade thesensitivity. Since the GSM antenna (as potential EMI victim) isoperating in an asymmetric mode and the high-speed data lines(as potential EMI source) are driven differentially, there is aninherent isolation. In real phone applications, the differentialbehaviour suffers partly from certain layout compromises(unequal line length, parasitic capacitances, etc.), partly fromtiming imperfections of the two single ended output drivercircuits for D+ and D- signal lines (e.g. due to spread insemiconductor manufacturing). This results in a conversionfrom differential mode (DM) to common mode (CM) [3], [4]and provides the coupling path from USB to GSM antenna.For certain phone designs, this might already occur inside thephone (e.g. with long flexfoil cable between system on chip(SoC) and USB connector) or externally when a USB cable isplugged into the phone (see also Fig. 15). In order to increasethe attenuation on this EMI path, a common mode filter canbe placed on the USB data lines. The presented filter includesESD protection diodes, which provide additional protectionagainst damage from electrostatic discharge on the data lines,including the ID pin of USB on-the-go (OTG) ports [5].

In the development and manufacturing process of mo-bile phones many restrictions influence the physical shape,geometry and placement of components (e.g. main printedcircuit board (PCB), battery, antennas, connectors and internalflexfoil interconnections). Those constraints are driven byaspects like size and cost reduction, EMI performance, antennacharacteristics and usability. Fig. 2 shows three examplaryconfigurations, which differ in PCB geometry and placementof antenna module and USB port. The designs in Fig. 2 a) andb) allow for a very short routing between SoC and USB portand furthermore a maximized decoupling from the opposing

Proceedings 30th European Conference on Modelling and Simulation ©ECMS Thorsten Claus, Frank Herrmann, Michael Manitz, Oliver Rose (Editors) ISBN: 978-0-9932440-2-5 / ISBN: 978-0-9932440-3-2 (CD)

-20 dB

480 MHz 960 MHz0 MHz

-80 dB

-30 dB

-40 dB

-50 dB

-60 dB

-70 dB

Fig. 1. Exemplary common mode (CM) spectrum on USB 2.0 data lines(measured during persistent reading from USB memory in high-speed mode,FFT-based spectrum by digital oscilloscope).

M

M

M

B B

BB = Battery

A = AntennaAAA

S

S

SU

U

U U = USB port

F = Flex-foil

F

S = System on Chip

M = Main PCB

a) b) c)

Fig. 2. Typical design variants found in mobile phones.

GSM antenna module. However, this position of the USB portmight be inconvenient for the user: E.g. during the use of acar mount or docking station for battery charging and datasynchronization via USB the placement at the bottom side isfavorable (Fig. 2 c). An actual phone design that is using thisarchitecture is depicted in Fig. 3. The long signal tracks ofthe flex-foil interconnection provide an internal coupling pathinto the GSM antenna structures. The close proximity of theUSB port itself can exacerbate the coupling in particular whenthe quality of external cable plugs and the internal port hasbeen deteriorated due to numerous insertion/removal cycles. Inorder to increase the isolation on this coupling path, a commonmode filter can be used.

DESIGN AND SIMULATION

Circuit

The filter device is composed of two coupled planar coilsand additional diode structures. Fig. 4 depicts the simplifiedschematic diagram, showing the fundamental elements andpin names of the USB connector. The design work flow isusing electromagnetic (EM) simulation tools, based on themethod of moments [6], [7], in order to consider the effectson the desired frequency response by distributed and parasiticstructures. The ESD protection for the data lines is providedby diodes arranged in rail clamp structure; this reduces thecapacitive load for the high-speed signals. Typical junctioncapacitance of reverse operated diode clamp is 1.5 pF. The

Fig. 3. Example of actual phone design with flexfoil USB connection.

concept of semiconductor controlled rectifiers (SCR) is appliedto achieve a very low dynamic resistance [8], [9].

GND

IDD–D+

← system chip connector →

Fig. 4. Schematic diagram of common mode filter with ESD protection.

The coils are characterized by their series inductanceLs ≈ 60 nH and series resistance Rs ≈ 6 Ω. The couplingfactor k ≈ 0.85 provides sufficient DM passband to handlethe spectrum of USB 2.0 signals. Inductance, coupling factorand diode capacitance shape the CM frequency response,that is designed to yield strong suppression in the 900 MHzGSM band. Nevertheless, it does not affect the single endedtransmission as used for low-speed and full-speed signaling(USB 1.0/1.1).

Once the design was finalized, a more detailed lumpedelement equivalent circuit has been created for the purposeof signal integrity studies. This passive circuit model israther compact, yet allows high accuracy for efficient transientsimulations like eye diagrams. Compared with S-parametersthe lumped model can reflect the device behaviour exactly atDC and low frequencies. The basic cell is shown in Fig. 5.In combination with few additional components, it is usedfour times to simulate the distributed characteristic of the realdevice for frequencies from 0 Hz beyond 2 GHz.

MUTIND

P5

P4

P3

P2

P1

C2gC1g

C1

C2

Mutual1

L1

L2

R1s

R1p

R2p

R2s

C=Cgnd2 fFC=Cgnd1 fF

C=(Cs/4) fF

C=(Cs/4) fF

L=(Lcoil_a/4) nH

L=(Lcoil_a/4) nH

R=Rcoil/4

R=Rs/4

R=Rs/4

R=Rcoil/4

4x

Fig. 5. Schematic diagram of basic element for lumped model.

Implementation

The ESD diode structures are manufactured in a bipolarsemiconductor process with two aluminium layers. The diesize is 1.34 mm x 0.95 mm. Layers of polyimid and copperare processed on top of the silicon die in order to implementthe two coupled coils with acceptable series resistance. In afinal processing step solder balls are added. In Fig. 6 thesesolder balls face up, and the upper copper layer is clearlyrecognizable. The lower copper layer is hardly distinguishablein this photograph. The cross sectional views in Fig. 7 andFig. 8 provide a better view on the two layers. The former istaken from the EM simulation tool [6] and reveals a cross-section, that allows to identify both copper layers and theelectrical connection between the coils and pads for the solderballs. The latter was taken by a scanning electron microscope(SEM). The transversal dimension of a single coil winding isabout 8 µm by 8 µm.

Fig. 6. Photograph of silicon die, showing solder balls, copper layers andunderlying aluminium layer on top of semiconductor substrate.

Fig. 7. Cross sectional view from EM simulation tool: Copper layers inred/green, aluminium layer in light blue, solder balls are not visible.

Fig. 8. Cross sectional view from SEM: Upper and lower copper coil layer(a), larger view showing interconnect from aluminium lower copper layer (b)

RESULTSESD protection

The ideal ESD protection is a switch with an infinite on-resistance in normal operation and zero on-resistance duringan ESD event. A semiconductor controlled rectifier (SCR) isnear-ideal in the sense that it exhibits a very high resistancefor low positive voltages and switches to a highly-conductivestate after triggering. Fig. 9 a) shows a typical SCR I-V graph.Once a certain voltage (trigger voltage Vt1) is exceeded, theSCR triggers and the voltage drops to a very low value, theholding voltage Vh, which is typically 1.5 V . . . 2 V. During thetransition from Vt1 to Vh, the SCR exhibits briefly a negativedynamic resistance. An equivalent circuit diagram is shown inFig. 9 b). Beyond Vh, the voltage rises again with increasing

Fig. 9. SCR I-V graph (left); SCR equivalent circuit diagram (right).

current in accordance with the ohmic resistance Rdyn of thedevice. An SCR typically has a very low dynamic resistance

Fig. 10. Cross-section of an SCR showing the integrated return diode.

in this range, in the order of a few tenths of an Ohm. Thus,the power dissipation in an SCR is very low during an ESDevent, resulting in very high current capability in case of anESD pulse, up to 80 mA / µm width of the SCR.

For reverse polarity ESD pulses, the ESD current is handledby the diode from D+ respectively D- to GND (Fig. 4) . Theoverall concept is a Low-Voltage-Triggered SCR (LVTSCR),[10], [11], in which the low-voltage triggering is not achievedby means of an avalanche diode. A cross-section of the deviceis shown in Fig. 10. For positive signal voltages the SCR isformed by the p+ in the n-epi, the pwell (pw) and finally then+ to ground (gnd).

Both, the low clamping voltage and the low dynamicresistance of the SCR contribute to an excellent protectionof the SoC in the following way:

1) The low clamping voltage reduces the risk of over-voltage on the SoC input / output (IO) pins, which mightotherwise damage the sensitive gate oxides, which inadvanced CMOS devices can be destroyed at voltagesbelow 5 V.

2) The low dynamic resistance shunts most of the ESDcurrent to ground. The residual current into the SoCdecreases, as the SCR dynamic resistance gets lower.By a proper choice of the protection, the SoC currentcapability and the impedance in between, the residualcurrent into the SoC can be limited to values preventingthermal damage to the SoC [12].

The current capability of all components can be quantifiedaccording to a number of international standards (e.g. HBM[13]). The system ESD performance can be established usingan IEC 61000-4-2 test [14]. Such tests yield a pass/fail result,which is useful for production-type testing but does not givemuch support for the development process. During develop-ment, the Transmission Line Pulse (TLP [15]–[17]) is widelyused. A TLP system applies square current pulses, usuallyof 100 ns duration, to the device under test (DUT) whichallow accurate determination of the voltage and current duringthe pulse. The TLP pulses provide an ESD-like discharge(regarding the pulse duration) and are known to correlate verywell with HBM and IEC pulses [18], [19]. Fig. 11 shows atypical TLP pulse of about 0.4 A of current and the resultingvoltage pulse. The voltage pulse shows, that when a currentpulse is applied, the voltage briefly (< 0.5 ns) rises to thetrigger voltage Vt1 and then drops sharply to the holdingvoltage Vh.

Fig. 11. Typical 100 ns TLP current (left) and voltage pulse (right).

Because the TLP employs pulses in the ESD time frame, itis possible to measure the I-V curve under typical ESD con-ditions, regarding pulse width (100 ns) and rise time (10 ns).A full TLP I-V curve is measured by applying a successionof pulses with increasing current until a pre-determined max-imum current is reached or the device fails. The time intervalbetween two consecutive pulses is typically about 1 s, whichis much larger than the cool-down time of the device (whichis in the order of ns). Thus, cumulative heating effects areavoided. As shown in Fig. 11 a), each current pulse exhibits aflat plateau of about 100 ns after the initial transient during therise time of the pulse. An HPPI 3010C TLP system - combinedwith a 3011C pulse width extender - was used to apply the TLPpulses. Voltage and current within each pulse were measuredon-wafer by means of RF Kelvin probes connected to a 4 GHzTektronix TDS7404B digital oscilloscope (at 10 GS/s). Eachcurrent and voltage measurement represents the average ofthe signal at the plateau between 75-85 ns during the pulsewidth. The force signal is applied into 50 Ohms to the DUTand the voltage sense signal is picked up via a 5 kOhm seriesresistor. The current is measured by means of a TektronixCT1 current probe, connected via an attenuator of 26 dB. Bysuccessively increasing the amplitude of each current pulse, acomplete I-V curve can be measured. Failure of the devicecan be detected by monitoring the DC leakage current at+5 V between two consecutive pulses, using a Keithley 2636SMU. Fig. 12 shows an example of a TLP I-V curve for anSCR as implemented in this common mode filter. The curveappears continuous, because the data points are connected bya solid line and the individual pulse measurements are notindicated, but in fact it represents a succession of individualpulses. The leakage measurements are not shown, becausethe device did not fail within the pulse current range of -12 A to +12 A as depicted in Fig. 12. Using this I-V curve,it is straightforward to measure device parameters, such asthe dynamic resistance Rdyn. Such a measurement cannotbe performed using DC measurements, because the muchlonger pulse durations would lead to extreme power dissipationand thus to premature failure unrelated to the actual ESDperformance. The TLP measurement results in Fig. 12 coverboth polarities: For pulses with negative polarity the grounddiode gets conductive once the voltage exceeds the forwardvoltage (Vcl < −1V). The dynamic resistance during the TLP

-12

-8

-4

0

4

8

12

'Vcl

'Icl

Icl(A)

Vcl(V)

Vt1Vh

R dyn-§

0.2

2

R dyn+§

0.2

7

0 2 4 6 8-2-4

'Icl

'Vcl

Fig. 12. I-V graph of the integrated SCR, measured with 100 ns TLP.

pulse can be read from the slope in Fig. 12 as Rdyn− ≈ 0.22Ω.For positive polarity the SCR is triggered at Vt1 = Vcl ≈ 8 V.After this snap-back, the SCR provides a dynamic resistanceof Rdyn+ ≈ 0.27 Ω.

Mixed mode scattering parametersScattering parameters are measured using a four port vector

network analyzer (VNA) and converted into mixed mode S-parameters Sdd21 (solid lines) and Scc21 (dashed lines) asshown in Fig. 13 [20], [21]. Besides the measured data (bluecurves), the graph includes simulation results based on the EMmodel (red curves) and the lumped model (green curves).

For low frequencies all six curves show an insertion lossof S21 ≈ -0.5 dB due to the series resistance of the coils.The -3 dB cut-off frequency for the differential mode is above1 GHz, for the common mode below 200 MHz. The resonantbehaviour of inductive and capacitive elements in the filterdesign results in a significant common mode rejection overthe full GSM-900 uplink (880 MHz to 915 MHz) and downlinkbands (925 MHz to 960 MHz).

1E7 1E8 1E91E6 4E9

-27

-24

-21

-18

-15

-12

-9

-6

-3

-30

0

freq in Hz

forw

ard

trans

mis

sion

in d

B

2.5D EM modelmeasured datalumped model

(1)

(2)

Fig. 13. Measured mixed-mode S-parameter:(1) = Sdd21 ; (2) = Scc21.

Signal integrityThe eye diagram is used to asses the signal integrity in the

time domain. The USB specification defines various limits forthe eye diagram to be measured at different test points in a

system. The most severe, i.e. the widest eye opening, is givenby template 1 as specified in [22]. The eye diagram as depictedin Fig. 14 was measured with the filter device mounted in acomplete application circuit, proving that insertion loss andcut-off frequency in differential mode are compliant withUSB 2.0 requirements.

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

time in ns

diffe

ren

tia

l sig

na

l in

V

0.0

0.1

0.2

0.3

0.4

-0.4

-0.3

-0.2

-0.1

-0.5

0.5

Fig. 14. Measured eye diagram according to template 1, test point TP2 [22].

Impact on USB EMI emissionAs discussed above, several coupling paths from the USB

interface to the GSM antenna module might exist in a mobilephone (Fig. 15). Investigations based on commercially avail-able phones can be difficult as documentation of hardwareand software is hardly available. Thus, a Beagleboard runningthe Linux operating system is used. The SoC incorporates anAM335x Cortex A8 ARM processor. This SoC is similar tothose used in modern smartphones and provides two integratedUSB 2.0 OTG host controllers. One of them is connected to afemale type A USB connector, which is used during testing.

1) Test setup: Since the application board is operatedwith opensource software, full access to the low level USBfunctions is available. This is essential for good reproducibilityof persistent USB transmissions. Here “persistent” means thatdata is read continuously from an external USB memoryas fast as possible, without additional delay from highersoftware layers, circumventing any caching that would reduceor avoid the physical USB transmission. The data itself is stilltransmitted in packets. This behaviour creates a non-stationaryfrequency spectrum. In order to observe this spectrum with aswept spectrum analyzer, the maximum hold detector was usedover ten consecutive sweeps.

To mimic an arbitrary coupling path between the USB datalines and an asymmetric (antenna) structure a single windingcurrent probe is used: The inner conductor of a coaxial cableis twined around the paired data lines and soldered to the outerconductor [23]. In a real phone, this coaxial cable would beconnected to the RF frontend of the GSM module; here, anEMI test receiver measures the spectrum in the GSM downlinkchannels (compare Fig. 15 and 16). In this experiment, onlythe single coupling path between an external USB cable andthe asymmetric probe is evaluated (Fig. 16).

Fig. 15. Potential EMI interference paths from USB interface to GSM antennamodule in a mobile phone.

Fig. 16. Laboratory test setup to measure impact of EMI filter duringpersistent USB traffic and emulate condition in mobile phones.

Fig. 17 depicts the filter PCB with the common mode filter(detail 1) in blue frame) in front of a USB memory device.During testing, this PCB is replaced by an identical one, butwithout a filter device. Here the filter footprint is bypassedby wires (detail 2) in orange frame) in order to establish athrough connection. Any impact of the filter PCB itself, suchas reflections at the male and female ports, is therefore keptthe same. Finally the spectrum in the GSM downlink band ismeasured with and without the filter device.

Fig. 17. The filter PCB is attached to a USB memory stick. Detail 1: CMFis mounted. Detail 2: CMF is replaced by through connection.

2) Results: The observed spectrum is given in Fig. 18:The orange graph is measured without and the blue graphwith the common mode filter in place. Both graphs showa strong signal at 960 MHz (Marker A) which is linkedto the harmonic spectrum of the inherent clock signal for480 MBit/s USB data signals (see also Fig. 1). This noise

can be particularly detrimental to absolute radio-frequencychannel numbers (ARFCN) 123 (fc = 959.6 MHz) and 124(fc = 959.8 MHz).

f in MHz956 957 958 959 960

rela

tive

ampl

itude

in d

B

0

-5

-10

-15

-20

-25

-30

-35

-40

-45

AD

C

B

Fig. 18. Detailed view on GSM downlink spectrum measured with (lower,blue graph) and without (upper, orange graph) common mode filter duringpersistent read access on USB memory (maximum hold detector over 10sweeps).

Furthermore multiple narrowband interferers (Marker B)can be identified, spaced by 0.67 MHz offset. Given the200 kHz channel spacing in GSM, almost every third downlinkchannel would be impaired by these spurs. By adding theCMF into the USB transmission path, all of these spurs arereduced by approximatly 20 dB. This corresponds well withthe measured S-parameter Scc21 (Fig. 13). Furthermore thisproves that the coupling path between USB cable and couplingprobe is dominated by common mode. Likewise the noisespectrum (Marker C) is reduced, although the reduction by20 dB is masked due to sensitivity limitations of the chosentest setup (impact of maximum hold detector and insertionloss of coupling probe). The spur denoted by marker D isnot affected by the CMF. It is identified as non-USB related,direct EMI injection from the Beagleboard into the couplingprobe: even without any USB transmission and disconnectedUSB memory this spurious emmission can be measured.

CONCLUSIONThe design process for a common mode filter with inte-

grated ESD protection for the USB 2.0 interface is presentedin this paper. The EM simulation, based on 2.5D tools,has demonstrated its strength in simulating planar structuresin semiconductor devices. Simulated and measured mixed-mode scattering parameters show very good conformance. Theachieved frequency response allows to suppress common modesignals in the GSM-900 downlink spectrum as demonstratedby an experimental test setup. The ESD protection is realizedby advanced SCR structures that protect sensitive CMOS SoCsdue to their low clamping voltage and low dynamic resistance.

REFERENCES[1] L. W. Nagel, “What’s in a name?” IEEE Solid-State Circuits Magazine,

vol. 3, no. 2, pp. 8–13, Spring 2011.[2] 3rd Generation Partnership Project; Technical Specification Group

GSM/EDGE Radio Access Network; Radio transmission and reception,“3GPP TS 05.05 V8.20.0,” 1999.

[3] F. De Paulis, L. Raimondo, D. Di Febo, and A. Orlandi, “RoutingStrategies for Improving Common Mode Filter Performances in HighSpeed Digital Differential Interconnects,” in Signal Propagation onInterconnects (SPI), 2011 15th IEEE Workshop on, May 2011, pp. 3–6.

[4] Yu-Jen Cheng, Hao-Hsiang Chuang, Chung-Kuan Cheng, and Tzong-Lin Wu, “Novel Differential-Mode Equalizer With Broadband Common-Mode Filtering for Gb/s Differential-Signal Transmission,” IEEE Trans-actions on Components, Packaging and Manufacturing Technology,vol. 3, no. 9, pp. 1578–1587, 2013.

[5] “On-The-Go and Embedded Host Supplement to the USB 2.0 Specifi-cation, Revision 2.0,” May 2009.

[6] Keysight. (2015) ADS - Advanced Design System. [2016-03-14].[Online]. Available: http://www.keysight.com/find/eesof-ads

[7] R. F. Harrington, Field Computation by Moment Methods. TheMacmillan Company, 1968.

[8] A. Amerasekera and C. Duvvury, ESD in Silicon Integrated Circuits,2nd ed. New York, John Wiley & Sons, 2002.

[9] J. Di Sarro and E. Rosenbaum, “A Scalable SCR Compact Modelfor ESD Circuit Simulation,” Electron Devices, IEEE Transactions on,vol. 57, no. 12, pp. 3275–3286, Dec 2010.

[10] A. Chatterjee and T. Polgreen, “A low voltage triggering SCR for on-chip ESD protection at output and input pads,” IEEE Elec. Dev. Lett.,vol. 21, no. 12, 1991.

[11] G. Notermans, F. Kuper, and J.-M. Luchies, “Using an SCR as ESDprotection without latch-up danger,” vol. 37, no. 10, pp. 1457–1460,1997.

[12] “System level ESD: Part II: Implementation of effective ESD robustdesigns.” JEDEC Publication JEP162, 2013.

[13] “Electrostatic Discharge Sensitivity Testing - Human Body Model (HB-M) - Component Level.” ESDA/JEDEC JS-001, 2014.

[14] “Electromagnetic Compatibility (EMC) - Part 4-2: Testing and measure-ment techniques - Electrostatic discharge immunity test.” IEC 61000-4-2, 2008.

[15] T. J. Maloney and N. Khurana, “Transmission Line Pulsing Techniquesfor Circuit Modeling of ESD Phenomena,” in EOS/ESD SymposiumProceedings, 1985, pp. 49–54.

[16] H. Hyatt, J. Harris, A. Alonzo, and P. Bellew, “TLP Measurements forVerification of ESD Protection Device Response,” Electronics PackagingManufacturing, IEEE Transactions on, vol. 24, no. 2, pp. 90–98, Apr2001.

[17] S. Voldman, R. Ashton, J. Barth, D. Bennett, J. Bernier, M. Chaine,J. Daughton, E. Grund, M. Farris, H. Gieser, L. Henry, M. Hopkins,H. Hyatt, M. Natarajan, P. Juliano, T. Maloney, B. McCaffrey, L. Ting,and E. Worley, “Standardization of the Transmission Line Pulse (TLP)Methodology for Electrostatic Discharge (ESD),” in Electrical Over-stress/Electrostatic Discharge Symposium, 2003. EOS/ESD ’03., Sept2003, pp. 1–10.

[18] G. Notermans, P. D. Jong, and F. Kuper, “Pitfalls when correlating TLP,HBM and MM testing,” in Electrical Overstress/Electrostatic DischargeSymposium Proceedings, 1998, Oct 1998, pp. 170–176.

[19] G. Notermans, S. Bychikhin, D. Pogany, D. Johnsson, and D. Mak-simovic, “HMMTLP correlation for system-efficient ESD design,” inMicroelectronics Reliability, vol. 52, 2012, pp. 1012–1019.

[20] D. Bockelman and W. Eisenstadt, “Combined Differential and Common-Mode Scattering Parameters: Theory and Simulation.” Microwave Theo-ry and Techniques, IEEE Transactions on, vol. 43, no. 7, pp. 1530–1539,Jul 1995.

[21] M. K. Allan Huynh and S. Gong. (2010) Mixed-Mode S-Parameters and Conversion Techniques, AdvancedMicrowave Circuits and Systems. [2015-05-28]. [Online]. Avail-able: http://www.intechopen.com/books/advanced-microwave-circuits-and-systems/mixed-mode-s-parameters-and-conversion-techniques

[22] “Universal serial bus specification, Revision 2.0,” Apr. 2000.[23] D. Morgan, A Handbook for EMC Testing and Measurement (IET

Electrical Measurement Series), 1st ed. Institution of Engineering andTechnology, 1994.

Jens Werner was born in Cologne, Germany in1969. He received the Dipl.-Ing. and Dr.-Ing. de-grees in electrical engineering from the TechnicalUniversity of Braunschweig, Braunschweig, in 1996and 2002, respectively. In 1996 he was workingwith Aerodata AG as a Flight Inspection Engineerworking on calibration of airborne antennas. From1996 to 2001, he was a Research Assistant at theInstitute of Electromagnetic Compatibility, Techni-cal University of Braunschweig. His main researchinterests were measurement techniques and repre-

sentation of guided and radiated electromagnetic fields. In 2001 he joined theInnovation Centre of Philips Semiconductors Germany GmbH in Hamburg,(since 2006 NXP Semiconductors). In March 2014, he became a Professorat Jade University of Applied Sciences, Wilhelmshaven, Germany. He isresponsible, amongst others, for the laboratory for RF, Wireless and EMC.

Jennifer Schutt was born in Heide, Germany in1981. She received a degree (Dipl.-Ing.) in electricalengineering from Technical University of Hamburg(TUHH) in 2009. Since then she is with NXP Semi-conductors, Hamburg, developing EMI-Filter andESD protection devices. Main field of expertise isin device modelling, EM simulation, device physicsand project management. Currently she is workingon common-mode-filter designs with integrated ESDprotection for ultra-fast differential data lines. In thefield of EM simulation, she organizes regular cross

team RF-expert meetings for NXP engineers located in Hamburg.

Guido Notermans is senior principal ESD withNXP Semiconductors in Hamburg. He graduated inexperimental physics at Utrecht University in 1980and received his PhD in plasma physics in 1984. Hesubsequently joined Philips Semiconductors wherehe developed III-V semiconductor lasers until 1990,first at the Philips Research Labs in Eindhoven.From 1995 he worked as senior ESD principalfor Philips Semiconductors. In 1999 he moved toBerlin where he joined Infineon Fiber Optics asR&D manager for electro-optical devices. In 2005

he moved to Philips Semiconductors Zurich where he returned to the fieldof ESD. Philips Semiconductors was spun off to become NXP in 2006. In2013, Guido moved to Hamburg and is developing stand-alone (off-chip) ESDprotection in the BU Standard Products.