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RFID SysTech’07 Design Methodology of a Voltage Multiplier for Full Passive Long Range UHF RFID Alexander Vaz, Aritz Ubarretxena, Daniel Pardo, Iñaki Sancho, Roc Berenguer

Design Methodology of a Voltage Multiplier for Full ... · 3. Voltage Multiplier Design D. Guidelines 1. Determine the optimum diode size 2. Select V OUT ÆN ÆV min 3. Detect which

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Page 1: Design Methodology of a Voltage Multiplier for Full ... · 3. Voltage Multiplier Design D. Guidelines 1. Determine the optimum diode size 2. Select V OUT ÆN ÆV min 3. Detect which

RFID SysTech’07

Design Methodology of a Voltage Multiplier for Full

Passive Long Range UHF RFIDAlexander Vaz, Aritz Ubarretxena, Daniel Pardo,

Iñaki Sancho, Roc Berenguer

Page 2: Design Methodology of a Voltage Multiplier for Full ... · 3. Voltage Multiplier Design D. Guidelines 1. Determine the optimum diode size 2. Select V OUT ÆN ÆV min 3. Detect which

Outline1. Introduction2. System constraints3. Voltage Multiplier Design

A. Improving the efficiencyB. Performing the input impedanceC. Output VoltageD. Steps to follow

4. Examples5. Conclusions

Page 3: Design Methodology of a Voltage Multiplier for Full ... · 3. Voltage Multiplier Design D. Guidelines 1. Determine the optimum diode size 2. Select V OUT ÆN ÆV min 3. Detect which

RFID SysTech’07

1. Introduction

Page 4: Design Methodology of a Voltage Multiplier for Full ... · 3. Voltage Multiplier Design D. Guidelines 1. Determine the optimum diode size 2. Select V OUT ÆN ÆV min 3. Detect which

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1. IntroductionBlocks Diagram

Page 5: Design Methodology of a Voltage Multiplier for Full ... · 3. Voltage Multiplier Design D. Guidelines 1. Determine the optimum diode size 2. Select V OUT ÆN ÆV min 3. Detect which

RFID SysTech’07

2. System Constraints

Page 6: Design Methodology of a Voltage Multiplier for Full ... · 3. Voltage Multiplier Design D. Guidelines 1. Determine the optimum diode size 2. Select V OUT ÆN ÆV min 3. Detect which

2. System Constraints3 limitations for the communication range:

• Reader Tag–Minimum input power–Minimum input voltage

• Tag Reader–Probability of error

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Page 7: Design Methodology of a Voltage Multiplier for Full ... · 3. Voltage Multiplier Design D. Guidelines 1. Determine the optimum diode size 2. Select V OUT ÆN ÆV min 3. Detect which

2. System ConstraintsMinimum input power

( ) [1] 14

422

2

DIGANAA

AV PPXR

XP +≥+ η ( )( )DIGANAA

eirpP PPXR

GXPr

++≤ 222

22

44πηλ

Incident power > Tag Power consumption

PRFin

[1] G. De Vita and G. Iannaccone, “Design Criteria for the RF section of UHF and Microwave passive RFID transponders”IEEE Trans. Microw. Theroy Tech., vol. 53, no.9, pp. 2985-2989, Sep. 2005

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Page 8: Design Methodology of a Voltage Multiplier for Full ... · 3. Voltage Multiplier Design D. Guidelines 1. Determine the optimum diode size 2. Select V OUT ÆN ÆV min 3. Detect which

2. System ConstraintsMinimum input voltage

• Matching Network is required– Maximum power transference increase efficiency

– Increment of the voltage (V2 > V1)

min47.0

VGRPQ

r AeirpmnV π

λ≤

mnxQVV

7.01

2 ≅

AAV RPV =1

[2]

[2] D. Pardo, A. Vaz, A. García-Alonso, R. Berenguer. “Design criteria for full passive long range UHF RFID sensor for human body temperature monitoring”. IEEE RFID 2007. Mar. 2007.

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Page 9: Design Methodology of a Voltage Multiplier for Full ... · 3. Voltage Multiplier Design D. Guidelines 1. Determine the optimum diode size 2. Select V OUT ÆN ÆV min 3. Detect which

2. System ConstraintsProbability of error

• To achieve appropriate communication Pe < 10-3

BPSK constellation

( ) ( )( ) ( )[1] 10

2sin

21cos2sin

21 3−≤

⎭⎬⎫

⎩⎨⎧

⎟⎠⎞

⎜⎝⎛

⎟⎠⎞

⎜⎝⎛ −

=σθ

σϕθ AerfAerfPe

[1] G. De Vita and G. Iannaccone, “Design Criteria for the RF section of UHF and Microwave passive RFID transponders”IEEE Trans. Microw. Theroy Tech., vol. 53, no.9, pp. 2985-2989, Sep. 2005

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Page 10: Design Methodology of a Voltage Multiplier for Full ... · 3. Voltage Multiplier Design D. Guidelines 1. Determine the optimum diode size 2. Select V OUT ÆN ÆV min 3. Detect which

RFID SysTech’07

3. Voltage Multiplier Design

Page 11: Design Methodology of a Voltage Multiplier for Full ... · 3. Voltage Multiplier Design D. Guidelines 1. Determine the optimum diode size 2. Select V OUT ÆN ÆV min 3. Detect which

Variable Guide

Vfwr ↓ Schottky diodesZero threshold transistors

VIN ↑ Matching network with ↑ QMN

N ~ Depends on the fixed VOUT (the technology used)

KN ↑ Depends on diode area, N, CS and CP

3. Voltage Multiplier DesignDickson’s Topology

VOUT = KNN (VIN-Vfwr)

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Page 12: Design Methodology of a Voltage Multiplier for Full ... · 3. Voltage Multiplier Design D. Guidelines 1. Determine the optimum diode size 2. Select V OUT ÆN ÆV min 3. Detect which

3. Voltage Multiplier DesignDetect which one, rp or rv, is more restrictive

A. If rp < rv ↑ Efficiency (η)

( )( )DIGANAA

eirpP PPXR

GXPr

++≤ 222

22

44πηλ

min47.0

VGRPQ

r AeirpmnV π

λ=

B. If rp > rv ↑ Qmn↓ Vmin

Perform ZIN

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Page 13: Design Methodology of a Voltage Multiplier for Full ... · 3. Voltage Multiplier Design D. Guidelines 1. Determine the optimum diode size 2. Select V OUT ÆN ÆV min 3. Detect which

3. Voltage Multiplier DesignA. Improving the efficiency (rp < rv)

1) Optimum Diode Area

For 868MHzOptimum Area: 8-10pm2

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Page 14: Design Methodology of a Voltage Multiplier for Full ... · 3. Voltage Multiplier Design D. Guidelines 1. Determine the optimum diode size 2. Select V OUT ÆN ÆV min 3. Detect which

3. Voltage Multiplier DesignA. Improving the efficiency (rp < rv)

2) Variation of the number of stages, CS and CP values

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Page 15: Design Methodology of a Voltage Multiplier for Full ... · 3. Voltage Multiplier Design D. Guidelines 1. Determine the optimum diode size 2. Select V OUT ÆN ÆV min 3. Detect which

3. Voltage Multiplier DesignB. Performing the input impedance (rp> rv)

( )APAV RRPV −≅ 7.02

( )12 += QRR ICP

IC

IC

RXQ =

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Page 16: Design Methodology of a Voltage Multiplier for Full ... · 3. Voltage Multiplier Design D. Guidelines 1. Determine the optimum diode size 2. Select V OUT ÆN ÆV min 3. Detect which

3. Voltage Multiplier DesignB. Performing the input impedance (rp> rv)

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Page 17: Design Methodology of a Voltage Multiplier for Full ... · 3. Voltage Multiplier Design D. Guidelines 1. Determine the optimum diode size 2. Select V OUT ÆN ÆV min 3. Detect which

3. Voltage Multiplier DesignC. Output Voltage (VOUT)

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Page 18: Design Methodology of a Voltage Multiplier for Full ... · 3. Voltage Multiplier Design D. Guidelines 1. Determine the optimum diode size 2. Select V OUT ÆN ÆV min 3. Detect which

3. Voltage Multiplier DesignSummary

η Q RIC VOUT↑N ↓↓ ↓ ↓ ↑↑↑CS ↑ ↑↑ ↓↓ CSopt

↑CP ~↑ ~↓ ~↑ ~↑

Minimum Number of StagesHigh CS

High CP (not decisive)

↑ηMinimum Number of Stages

High CSLow CP (not decisive)

Optimum ZIN

CS and CP > 400fFHigh N

Optimum CSHigh CP (not decisive)

↑ VOUT

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Page 19: Design Methodology of a Voltage Multiplier for Full ... · 3. Voltage Multiplier Design D. Guidelines 1. Determine the optimum diode size 2. Select V OUT ÆN ÆV min 3. Detect which

3. Voltage Multiplier DesignD. Guidelines

1. Determine the optimum diode size2. Select VOUT N Vmin

3. Detect which one, rv or rp, is more restrictive4. Determine CS or CP according to point 35. Calculate the input impedance6. Calculate the matching network

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Page 20: Design Methodology of a Voltage Multiplier for Full ... · 3. Voltage Multiplier Design D. Guidelines 1. Determine the optimum diode size 2. Select V OUT ÆN ÆV min 3. Detect which

RFID SysTech’07

4. Examples

Page 21: Design Methodology of a Voltage Multiplier for Full ... · 3. Voltage Multiplier Design D. Guidelines 1. Determine the optimum diode size 2. Select V OUT ÆN ÆV min 3. Detect which

4. ExamplesDifferent VM have been fabricated

•Number of stages: 4, 6 and 8

•High Q

•High Efficiency

•Optimized for the chip

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Page 22: Design Methodology of a Voltage Multiplier for Full ... · 3. Voltage Multiplier Design D. Guidelines 1. Determine the optimum diode size 2. Select V OUT ÆN ÆV min 3. Detect which

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Supply Capacitor

ASKVMLM POR

Reg 1.8 Reg1.2

4. Examples

Page 23: Design Methodology of a Voltage Multiplier for Full ... · 3. Voltage Multiplier Design D. Guidelines 1. Determine the optimum diode size 2. Select V OUT ÆN ÆV min 3. Detect which

RFID SysTech’07

5. Conclusions

Page 24: Design Methodology of a Voltage Multiplier for Full ... · 3. Voltage Multiplier Design D. Guidelines 1. Determine the optimum diode size 2. Select V OUT ÆN ÆV min 3. Detect which

5. ConclusionsIn order to obtain higher reading distances of the tag VM is criticalA design for the VM has been presented:– Know the real limitation of the RFID system

• Higher Q• Higher Efficiency• Trade off between both

– Design the VM following the guidelines

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Page 25: Design Methodology of a Voltage Multiplier for Full ... · 3. Voltage Multiplier Design D. Guidelines 1. Determine the optimum diode size 2. Select V OUT ÆN ÆV min 3. Detect which

RFID SysTech’07

Design Methodology of a Voltage Multiplier for Full

Passive Long Range UHF RFIDAlexander Vaz, Aritz Ubarretxena, Daniel Pardo,

Iñaki Sancho, Roc Berenguer