On-Chip High-Voltage Generation in MNOS Integrated Circuits Using an Improved Voltage Multiplier Technique

8/8/2019 On-Chip High-Voltage Generation in MNOS Integrated Circuits Using an Improved Voltage Multiplier Technique

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3 7 4 IEEE JOURNAL OF SOLID-STATECIRCUITS,VOL. SC-11, NO. 3, JUNE 1976

speed of such PLAs would exceed the speed of bipolar PLAscommonly on the market, but at the same time have a higherdensity and draw much less current .

ACKNOWLEDGMENT

The authors would like to thank W. Kaschte for designingthe

[1]

[2]

[3]

[4]

[5]

[6]

[7]

PLAs and Dr. Spli ttgerber for making them.

REFERENCES

W. Carr and J. Mize, MOS/LSI Design and Application. NewYork: McGraw-Hill, 1972, pp. 229-259.U. Priel and P. Holland, Application of a high speed program-mable logic array, Comput. Des., pp. 94-96, Dec. 1973.K. Sickert, Ein programmierbaies Logikar ray in dynamischerCMOS-Technik, presented at the workshop on ProgrammableIntegrated Circuits, Berchtesgaden, Germany, Oct. 8-10, 1975.H. Fleisher and L. I. Maissel, An introduction to array logic:IBMJ. Res. Develop., vol. 19, pp. 98-109, Mar. 1975.H. Sakamoto arid L. Forbes, Grounded load complementary FETcircuits: Sceptre analysis; IEEE J. Solid-State Circuits (Corresp.),vo l . SC-8, pp. 282284, Aug. 1973.K. Horninger, A high-speed ESFI SOS programmable logic arraywith an MNOS version; IEEE J. Solid-State Circuits, vol. SC-10,pp. 331-336, Oct. 1975.

M. Pomper and J. Tihanyi, Ion implanted ESFI MOS deviceswith shor t switching times, IEEE J. Solid-State CWcuits, vol.SC-9, pp. 250-256, Oct. 1974.

MOS technology,

Ernst Hebenstreit was born in Magyarovar,Hungary, in 1928. He received the Dipl. Ing.degree from the Technische Universitat Wien,Vienna, Austria in 1953.Since 1954 he has been with the Siemens AG,

Munich, Germany, working in different researchand development laborator ies. His areas of ac-tivity have been: microwave techniques, carrierfrequency telegraphy, digital techniques, andcomputer systems. Dur ing the last few years he

has been working on LSI circuits in SOS and

Karlheirrrich Hominger was born in Graz,Austria, on November 7, 1944. He receivedthe DipL Ing. and Dr. Techn. degrees from theTechnische Hochschule Wlen, Vienna, Austriain 1970 and 1975, respectively.Since 1970 he has been with the Siemens Re-

search Laboratories, Munich, Germany. He hasbeen working in the field of MOS memor ies anddigital integrated circuits.

Mr. Horninger is a member of the VerbandDeutscher Elektrotechniker (VDE) and Nach-richtentechnische Gesellschaft (NTG).

On-Chip High-Voltage Generation in

Integrated Circuits Using an ImprovedMultiplier Technique

JOHN F. DICKSON

Abstract-An improvedoped for generat ing +40

voltage multiplier technique has been devel-V internally in p-channel MNOS integrated

circu its to enrtble them to be operated f rom standard +5- and : 12-Vsupply rails. With this technique, the multiplication efficiency and cur-rent driving capabti lty are both independent of the number of multi-plier stages. A mathematical model and simple equivalent circuit havebeen developed for the multiplier and the predicted performance agreeswell with measured results.A multipl ier has already been incorporated into a TTL compatible

nonvolatil e quad-latch, in which it occup ies a chip area of 600 ~m X240 pm. It is operated with a clock frequency of 1MHzand can sup-

Manuscript received December 9, 1975; revised February 18, 1976.This paper is based on par t of a presentation ent itled A non-volati leMNOS quad-latch, which was presented at the First European Solid-State Circuits Conference, Canterbury, England, September 2-5, 1975.The author iswith the Allen Clark Research Centre, The Plessey Com-

pany Ltd., CasweJl, Towcester, Northants., England.

MNOS

Voltage

ply a maximum load cur rent of about 10 NA. The output impedance is3.2 Mfl.

INTRODUCTION

ALTHOUGH MNOS technology is now well established forfabricating nonvolatile memory circuits, the relativelyhigh potentials necessary to write or erase information,

typically 30-40 V, are an obvious disadvantage. In many ap-plications, the need to generate these voltages has preventedthe use of MNOS devices being economically viable, especiallywhen only a few bits of nonvolatile data are required. Toovercome this problem, a method of on-chip high-voltage gen-eration using a new voltage multiplier technique has been de-veloped, enabling MNOS circuits to be operated with standard


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DICKSON: ON-CHIP HIGH-VOLTAGEGENERATION 375

77!7 h 9 7 .47 A

Fig. 1. Basic Cockcroft-Walton voltage multiplier. Usually imple-mented with discrete components such that C >> C$

supplies and interfaces. The technique has already been dem-onstrated to be practical in a nonvolatile quad-latch circuit andis currently being designed as standard in a range of nonvola-tile memory products.

MULTIPLIER TECHNIQUE

In principle, voltages higher than that of the power supplycan be generated in an integrated circuit using a Cockcroft-Walton multiplier similar to that shown in Fig. 1. Its opera-

tion is well known and will not be described in detail here,except to note that since the coupling capacitors are connectedserially, the following comments apply.1) Efficient multiplication will occur only if the coupling

capacitors, C, are much greater than the stray capacitors, CS.2) The output impedance increases rapidly with the number

of multiplying stages.Historically, the Cockcroft-Walton multiplier [1] has been

used to generate voltages greater than. those which could beeasily handled by electromagnetic transformers. This is pos-sible since the maximum voltage across any of the couplingcapacitors is only equal to the input drive voltage, irrespectiveof the number of multiplying stages. In this type of applica-

tion, however, the circuit is implemented with discrete compo-nents, so that the coupling capacitors can be made sufficientlylarge for efficient multiplication and adequate drive capability.This type of multiplier does not, however, lend itself to inte-

gration in monolithic form since in practice, on-chip capaci-tors are limited to a few picofarads with relatively high valuesof stray capacitance to substrate. A generalized analysis of theCockcroft-Walton multiplier taking stray capacitance into ac-count is extremely complex and will not be given here, but itis found that in practice it is difficult to generate voltages sig-nificantly greater than twice the supply voltage, irrespective ofthe number of multiplying stages. In fact, if the number ofstages is increased beyond a critical number (typically, 3 or 4),

determined by the ratio of C and CS, the output voltage ac-tually decreases due to voltage drops in the diode chain.In order to overcome these limitations, the voltage multiplier

circuit shown in Fig. 2 was devised. It operates in a similarmanner to the classicrd Cockcroft-Walton multiplier and canbe shown to be an equivalent circuit. However, the nodes ofdiode chain are coupled to the inputs via capacitors in parallelinstead of in series, so that the capacitors have to withstandthe full voltages developed along the chain. This is not a prob-lem here, provided that the integrated circuit process limits arenot exceeded. As will be shown, the advantages of this config-

Fig. 2. Improved voltage multiplier configuration. In monolithic form,C > C~> O.lC, typical ly.

F

~~

VI v V.1 VN OUT

Fig. 3. Voltage waveforms in N-stage multiplier showing voltage rela-tionship between successive nodes of the diode chain.

uration are that efficient multiplication can be achieved withrelatively high values of stray capacitance, and that the currentdrive capability is independent of the number of multiplierstages.The operation of the circuit is illustrated in Fig. 3, in which

the typical voltage waveforms in an IV-stage multiplier areshown. As can be seen, the two clocks @and T are in anti-phase with amplitude V@,and are capacitively coupled to al-ternate nodes along the diode chain. The multiplier operatesin a manner similar to a bucket-brigade delay line, by pumpingpackets of charge along the diode chain as the coupling capaci-tors are successively charged and discharged during each halfof the clock cycle. Unlike the bucket-brigade delay line, how-

ever, the voltages in the diode chain are not reset after eachpumping cycle so that the average node potentials increaseprogressively from the input to the output of the diode chain.This operation is also similar in principle to the well-knownbootstrap technique often used in MOS integrated circuits[2] in that a bootstrap circuit incorporates a voltage doubler.Here, however, the coupling capacitor is connected to the in-put clock, unlike bootstrap circuits in which it is connected tothe output. As can be seen in Fig. 3, the difference betweenthe voltages of the nth and (n + l)th nodes at the end of eachpumping cycle is given by


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376 IE EE J O URNAL O F S OLID -S TATE CIRC UITS , J U NE 1 97 6

vn+l - v n= v ; - v ~ - v ~ (1)

where K$ is the voltage swing at each node due to capacitivecoupling from the clock, VD is the forward bias diode voltage,and VL is the voltage by which the capacitors are charged anddischarged when the multiplier is supplying an output current,10uT .For a clock coupling capacitance, C, and stray capacitance

CS, at each node, capacitance division gives

() v ~ .u= ~+(lsAlso, since the total charge pumped by each diode per clockcycle is (C + CS) VL, the current supplied by the multiplier ata clock frequency, f ,is given by

~~~= = f ( c +Cs) VL .

Substituting for V$ and VL in (1) we get

v

()IOU= vo - D- (C+ Cs )f

n+l-vn= C+CS

so that for IVstages,

[( ) IOUTvN-v~N=~ & v @- VD- (C+cs )f 1 (2)where VIN is the input voltage. In a practical multiplier, anadditional isolating diode is required at the output to preventclock breakthrough so that the peak output voltage, VOUT,is given by

[( ) IOUTvouT - v~N = N C+ c s v @- D- ( C+ c s ) f1- v ~ .

Rearranging, we get

vou,=~,N+~[(&)ov,vD]NIOUT

- D- ( C+ c s ) f (3)

There is also a ripple voltage, VR , at the multiplier outputdue to the load resistance, RL, discharging the output ca-pacitance, Cou=. Usually, C~uT is sufficiently large for VRto be small compared to VOUT, s o that

IOUT . v~u=E~=

fCouT fRL COUT (4)

In practical multipliers there will also be an additionalripple component due to capacitive coupling from the clocksthrough the diodes. In the case of nonoverlapping clockphases, there will be significant breakthrough from only onephase through the isolating diode. With overlapping clocks,however, there will also be breakthrough from the other clockphase occurring when the isolating diode is conducting. Themagnitude of the breakthrough from either phase is given by

vow= h -IOUTRS

Fig. 4. Equivalent circuit of N-stage multiplier.

BT=(CO:+CJ i_ CD- v; f o rCOUT>> CD@JT

where CD is the capacitance across each diode, so that for non-overlapping clock phases,

IOUTv ~ = + 2 Af c o~ T c ou T

and for overlapping clock phases,

zouT + 2C D v$VR=

fCOuT COUT

(4a)

(4b)

From (3), it can be seen that voltage multiplication occurs,provided that

()c IOUTC+cs v@- D- ( C+ c s ) f 0 (5)It is important to note that this expression is independent offV, so that there is, in principle, no limit to the number ofstages in a multiplier of this type. Furthermore, provided that(5) is satisfied, the current drive capability of the multiplier isalso independent of the number of multiplier stages.Also from (3), we can write

VOUT = V. - IOUT Rs (6)

where

VO=VIN-VD+N[(&) VOVD] 0)

and

NS=(c+cs)f

(8)

L. and Rs are the open-circuit output voltage and outputseries resistance of the multiplier, respectively, so that (6)leads to an extremely simple equivalent circuit of the multi-plier output, as shown in Fig. 4.In deriving this model for the voltage multiplier, it has so far

been assumed that the capacitors are completely charged anddischarged with a diode cutoff voltage, VD. In practice this isnot the case due to the nonlinear voltage-current character-istics and internal series resistance, RD, of the diodes. Thisresults in a residual voltage in addition to VD remaining across


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DICKSON: ON-CHIP HIGH-VOLTAGEGENERATION 377

Osc,l!.tor Clock d,,versVss0

& y +1

output

l,rn,te,

DOJiEJFLL v,,

M.lt,pl ,er ch. ,n

Fig. 5. Practical implementation of multiplier using MOS technology.

the diodes at the end of each cycle, causing the multiplier out-put series resistance, Rs, to increase in a nonlinear mannerwith load current. However, by making RD sufficiently smallsuch that

RD(C+ C~) f


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3 78

t=o + t (1 millisecond /div)

I10vol t s / d ivlv~~

Fig. 8. Rise time of MOS voltage multiplier driving 1 nF output loadcapacitance. Theoret ical valu~ of multiplier ou~ut resistance, R5,is typically 3.2 Ms2.

TABLE IMULTI P LI E R OUT PUT AND R I PP LE VOLTAGE SAS A FUNCTI ON O F LOAD

CURRENT

r

Load Cum-at Output V oltage P - P Ripple Voltage

IOUT (PA) VOUT( volts) VR (volts)

Predicted I Measured Predicted I Measured

3 .9 44.3 3 9 .1 0 .2 9 0.2839 .5 37 .5 0 .3 1 0 .3 0

H 35 .7 33 .3 0 .32 0 .3 28 .2 30 .6 27 .2 0 .34 0.34

be achieved by using a value of 5 V for the threshold voltagein (1 1). This gives

VOu~ =7.36 (VDD -1 V)- 391-3.18 X 106 Mfl IouT.

(12)

Since the clock drivers in Fig. 5 produce overlapping clockphases, the ripple voltage is given by (4b). In this case the cal-culated value of CD (the gate-source capacitance of the diodeconnected MOS transistors) is O.1 pF, giving

1vR. (

IOUT

.)+2X10-13X; AS

COuT 106 Hz

i.e.,

1

(

IOUTv~=

)+2.54X 10-12 As .

CouT 106 Hz(13)

In Table I, below, a comparison is made between the mea-sured values of output and ripple voltage for various load cur-

IE EE J OURNAL O F SOLID -S TATE C IRCUITS , J UNE 1 9 76

ren ts , a nd th os e p red icted by (12) and (13), respectively. Thesupply voltage, VDD, is chosen to be 14 V to ensure that themul tipl ier is operating in the linear region of i ts characteris tics,and the output capacitance, CouT, is approximately 10 pF.As can be seen, there is a good agreement between the pre-dicted and measured results.

CONCLUSIONS

The voltage multiplier technique has been demonstrated tobe practical, and measured results agree well with the theo-retical model. Although developed especially for generatinghigh supply voltages in MNOS integrated circuits, the tech-nique is equally applicable for many other applications. Inparticular, it may be possible to implement a fully monolithicde-de up-converter chip using bipolar technology, utilizing thebetter frequency performance to operate at much higher cur-rent levels.

ACKNOWLEDGMENT

The author wishes to thank D. Bostock for technical discus-sions and practical help in the development of the multipliertechnique. Thanks are also due to the Directors of the PlesseyCompany Limited for permission to publish this paper.

REFERENCES

[1] J. D. Cockcroft and E. T. Walton, Production of high velocitypositive ions, Proc. Roy. Sot., A, vo l. 1 3 6 , pp. 619-630, 1932.

[2] W. N. Carr and J. P. Mize, MOS/LSI design and applications,Texas Instruments Electronics Series. New York: McGraw-Hill ,1972, P. 123.

group are the designcoupled devices.

John F. Dickson was born in Liverpool, En-gland, on June 12, 1944. He received the B.SC.Honours degree from the University College ofNorth Wales, Bangor, Wales, in 1965.Since then he has worked for the Plessey

Company Ltd. at the Allen Clark ResearchCentre, Caswell, Towcester, Northants., En-gland. During this time he has worked mainlyon the design of MOS and optoelect ron ic inte-grated ci rcui ts, and now heads the MOS designgroup. At present, the main activities of the

of nonvolatile MNOS memory circuits and charge-

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On-Chip High-Voltage Generation in MNOS Integrated Circuits Using an Improved Voltage Multiplier Technique