Developing Bipolar Transistors for Sub-mm-Wave Amplifiers and Next-Generation (300 GHz) Digital Circuits

rodwell@ece.ucsb.edu 805-893-3244, 805-893-5705 fax

CollaboratorsZ. Griffith, E. Lind, V. Paidi, N. Parthasarathy, C. Sheldon, U. SingisettiECE Dept., University of California, Santa BarbaraProf. A. Gossard, Dr. A. Jackson, Mr. J. EnglishMaterials Dept., University of California, Santa BarbaraM. Urteaga, R. Pierson , P. RowellRockwell Scientific CompanyX. M. Fang, D. Lubyshev, Y. Wu, J. M. Fastenau, W.K. Liu International Quantum Epitaxy, Inc.Lorene Samoska, Andy FungJet Propulsion Laboratories S. Lee, N. Nguyen, and C. NguyenGlobal Communication Semiconductors

Plenary, Device Research Conference, State College, PA, June 26, 2006

SponsorsJ. Zolper, S. Pappert, M. RoskerDARPA (TFAST, ABCS, SMART)I. Mack, D. Purdy, M. YoderOffice of Naval Research

Mark Rodwell University of California, Santa Barbara

Our Specific Focus :

So, how can we build next-generation ICs ?

- 600 GHz amplifiers.

- 300 GHz digital clock rate.

Present III-V transistors have enabled

- 300 GHz amplifiers.

- 150 GHz clock rate digital ICs.

More Generally :

What do we mean by THz transistors ?

What are they for ?

How do we make them ?

Can we build THz transistors ?

What are the frequency limitsof bipolar integrated circuits ?

High-Resolution Microwave ADCs and DACs

THz Transistors: What Are They For ?

340 GHz & 600 GHz imaging systems

mm-wave radio: 40+ Gb/s on 250 GHz carrier

320 Gb/s fiber optics & adaptive equalizers for 40 Gb/s ...

Why develop transistors for mm-wave & sub-mm-wave applications ? → compact ICs supporting complex high-frequency systems.

THz Transistors: What does this mean ?A 1 THz current-gain cutoff frequency (f) alone has little value

a transistor with 1000 GHz f and 100 GHz fmax

cannot amplify a 101 GHz signal.

RF-ICs & MIMICs need high power-gain cutoff frequency (fmax )impedance matching is hard if f is low.

100+ GHz digital also needslow (Cdepletion V / I ) and low (I*Rparasitic /V ) .

So, how do we make a transistor with>1 THz f

>1 THz fmax

<50 fs CV / I charging delays ?

Key Performance Parameters for MMICs / RF-IC's

0

5

10

15

20

25

30

10 100 1000

MS

G/M

AG

, dB

Frequency, GHz

Common base

Common Collector

Common emitter

U

MIMIC / RF-ICs need gain ---hence fmax

Power amplifiers need breakdown voltage & power density

Low-Noise amplifiers need moderate associated gain and low noise

)(21min, igSmiHEMT RRRg

ffF

maxminmaxmax 81 IVVP

fmax

Key Performance Parameters for Fast Logic

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depl,

Design HBTs for fast logic, not for high ft & fmax

HBT Scaling Laws

HBT Scaling Roadmaps

Bipolar Transistor Scaling Laws

key device parameter required changecollector depletion layer thickness decrease 2:1base thickness decrease 1.414:1emitter junction width decrease 4:1collector junction width decrease 4:1emitter resistance per unit emitter area decrease 4:1current density increase 4:1base contact resistivity (if contacts lie above collector junction)

decrease 4:1

base contact resistivity (if contacts do not lie above collector junction)

unchanged

Goal: double transistor bandwidth when used in any circuit → keep constant all resistances, voltages, currents → reduce 2:1 all capacitances and all transport delays

Epitaxial scaling: layer thicknessesLithographic scaling: junction dimensionsResistance scaling: contact resistance and thermal resistance

InP HBT Scaling Roadmaps

Key scaling challengesemitter & base contact resistivitycurrent density→ device heatingcollector-base junction width scaling & Yield !

key figures of merit

for logic speed

Present Status of Fast III-V Transistors

)( ),/( ),/( ),/(

hence , :digital

gain, associated ,F :amplifiers noise low

mW/ gain, associated PAE,

:amplifierspower

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0

100

200

300

400

500

600

700

800

0 100 200 300 400 500 600 700 800

RSCUIUC_SHBTNTTFujitsu HEMTSFUUIUC_DHBTUCSB 500 nmNGSTPohangHRLIBM SiGeVitesseUCSB 250 nm

f max

(GH

z)

ft (GHz)

500 GHz400 GHz300 GHz200 GHz maxff

Updated July 5 2006

250 nm

Red = manufacturable technology for 10,000- transistor ICs

500 nm

E. Lind et al, this conference

Scaling Generations

emitter 500 nm width 16 m2 contact

base 300 width, 20 m2 contact

collector 150 nm thick, 5 mA/m2 current density5 Vbreakdown

f 400 GHzfmax 500 GHz

power amplifiers 250 GHz digital clock rate 160 GHz(static dividers)

2005: InP DHBTs @ 500 nm Scaling Generation

emitter 500 250 nm width 16 9 m2 contact

base 300 150 width, 20 10 m2 contact

collector 150 100 nm thick, 5 10 mA/m2 current density5 3.5 Vbreakdown

f 400 500 GHzfmax 500 700 GHz

power amplifiers 250 350 GHz digital clock rate 160 230 GHz(static dividers)

2006: 250 nm Scaling Generation, 1.414:1 faster

emitter 500 250 125 nm width 16 9 4 m2 contact

base 300 150 75 width, 20 10 5 m2 contact

collector 150 100 75 nm thick, 5 10 20 mA/m2 current density5 3.5 3 V breakdown

f 400 500 700 GHzfmax 500 700 1000 GHz

power amplifiers 250 350 500 GHz digital clock rate 160 230 330 GHz(static dividers)

125 nm Scaling Generation→ almost-THz HBT

emitter 500 250 125 63 nm width 16 9 4 2.5 m2 contact

base 300 150 75 70 nm width, 20 10 5 5 m2 contact

collector 150 100 75 53 nm thick, 5 10 20 35 mA/m2 current density5 3.5 3 2.5 V breakdown

f 400 500 700 1000 GHzfmax 500 700 1000 1500 GHz

power amplifiers 250 350 500 750 GHz digital clock rate 160 230 330 450 GHz(static dividers)

65 nm Scaling Generation→beyond 1-THz HBT

Scaling Challenges

Reducing Contact ResistivityPd or Pt solid-phase-reaction contacts

extrinsic base

intrinsic base

drift collector

N+ sub collector

S.I. InP substrate

pedestal

current-block layer

regrown emitter

emitter contact

base contact

Regrowth for wider emitter contacts

basedrift collector

sub-collector

We

Te

Wrap-around emitter contact

nm 200at m-1

21

2

e

eex

e

bulkcontact

eex

WAR

WLR

ErAs in-situ MBE emitter contactsgrown in-situ by MBE no oxides, no contaminants Lattice matched few defect states no Fermi level pinningThermodynamically stable little intermixing

Zimmerman, Gossard & Brown

Q. G. Sheng, J. Appl. Phys. (1993)A Guivarc’h, J. Appl. Phys. (1994)

*A. Guivarc’h, Electron. Lett.(1989)**C.J.Palmstrøm Appl. Phys. Lett. (1990)

TEM : Lysczek, Robinson, & Mohney, Penn State Sample: Urteaga, RSC

E. F. Chor et al , JAP 2000

Emitter-Base Degeneracy → 1.5 m2 Effective Junction Resistance

10-3

10-2

10-1

100

101

102

-0.3 -0.2 -0.1 0 0.1 0.2

J(m

A/u

m^2

)

Vbe

-

Fermi-Dirac

Equivalent series resistance approximation

Boltzmann

fnEcE

Degeneracy contributes ~ 1-2 -m2 to observed emitter resistivity (?).

Solutions: higher mass emitter ?superlattice emitter ?

*2

2

132

2*

2

2

/1 ,InPfor m 5.1

)()/ln()/(

model resistance series eApproximat

d]unpublishe , Lundstrom& [Liang

)/)((4

)(

integral Dirac- Fermimodel, ballistic :ApproachBetter

mmA/ 22 :envelope ofBack

junction base-emitter in degeneracynear mmA/ 10

eeqeq

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m

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thanks to Bill Frensley for BandProf !

Temperature Rise Within Transistor & Substrate

re temperatujunction Increased1:2 decreases spacingransistor t

1:4 decreases dthemitter wi rateclock digital in doubling eachFor

HBT

e

DW

2substrate

2/11lnD

DTK

PDLK

PWL

LKPT sub

InPEInPe

e

EInP

eLr junctionnear flowheat lcylindrica

2/for flowheat spherical

HBTe DrL 2/for flowheat planar

HBTDr

scaling withcallylogarithmi

increases

scaling withvariationnegligible

constant is IF scaling with

llyquadratica increases

subT

Temperature Rise Within Transistor & Substrate

2substrate

2/11lnD

DTK

PDLK

PWL

LKPT sub

InPEInPe

e

EInP

0

20

40

60

80

100

120

140

100 200 300 400 500 600 700

tem

pera

ture

rise

in s

ubst

rate

, Kel

vin

master-slave D-Flip-Flop clock frequency, GHz

clocksub fT GHz/ 160 m 15

rate.clock digital GHz 300at even rise re temperatusubstrate acceptable allows

thicknesssubstrate reducingy Agressivel subT

junctionnear flowheat lcylindrica

eLr for flow spherical

2/for flowplanar

HBTDr

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variationantinsignific

constant is iflly quadratica increases

subT

ICs digital GHz 150

eddemonstrat from scaled etc.

densities,power rates,clock

lenghts, Wiring

Temperature Rise Within Package

chipCu

chippackage WK

PT

211

RiseeTemperatur PackageTotal

0

50

100

150

200

100 200 300 400 500 600

pack

age

tem

pera

ture

rise

, Kel

vin

fclock,

GHz

12 mA per transistor (25 logic load resistor)

3 mA per transistor (100 logic load resistor)

n)dissipatior transisto( 1.5 power IC rs/IC transisto1000

bias V 2 )GHz/ (150 m 20 :spacing Transistor

:sAssumption

ce

clock

Vf

rate.clock digital GHz 300at evenIC / rs transisto1000 with

rise re temperatupackage acceptableloading) (100stor per transi mA 3At

1:2 decrease dimensions chip 1:2 decrease spacings BT H

rateclock digital in doubling eachFor

chip

HBT

WD

Scaling of Breakdown Voltage with InP/InGaAs InP DHBTs

-2.0

-1.5

-1.0

-0.5

0.0

0.5

1.0

1.5

0 10 20 30 40 50 60 70 80

60 nm thick collector

Ener

gy (e

V)

distance (nm)

collector

base

-2.0

-1.5

-1.0

-0.5

0.0

0.5

1.0

1.5

0 20 40 60 80 100 120 140 160

120 nm thick collector

Ener

gy (e

V)

distance (nm)

collector

base

If collector is thinned without thinninggrade and setback layers...

..then Zener tunneling through grade& setback layers can reduce BVCEO

Or, should we simply thin the grade, using fewer superlattice periods ?

Type-2 DHBT: InGaAsSb baseType-1 DHBT: InGaAs base

Should we switch from type-I DHBT to type-2, eliminating the grade but sacrificing base transport ?

...or other approaches...

Erik Lind

Breakdown Voltage: What do we really need ?

0

2

4

6

8

10

0 1 2 3 4 5 6 7 8

J e (mA/

m2 )

Vce (V)

6.8 V BVCEO

maxminmaxmax 81 IVVP

0

2

4

6

8

10

0 1 2 3 4 5 6 7 8

J e (mA/

m2 )

Vce (V)

6.8 V BVCEO

10 mW/um2

20 mW/um2

maxminmaxmax 81 IVVP

Breakdown Voltage: What do we really need ?

0

2

4

6

8

10

0 1 2 3 4 5 6 7 8

J e (mA/

m2 )

Vce (V)

maxminmaxmax 81 IVVP

!

Breakdown Voltage: What do we really need ?

0

2

4

6

8

10

0 1 2 3 4 5 6 7 8

J e (mA/

m2 )

Vce (V)

maxminmaxmax 81 IVVP

Breakdown Voltage: What do we really need ?

max&high ff max& low ff

bandwidth decreases at high Vce due to velocity-field characteristics

Scaling challenges: What looks easy, what looks hard ?

key device parameter required change

collector depletion layer thickness decrease 2:1

base thickness decrease 1.414:1

emitter junction width decrease 4:1

collector junction width decrease 4:1

emitter resistance per unit emitter area decrease 4:1

current density increase 4:1

base contact resistivity (if contacts lie above collector junction)

decrease 4:1

base contact resistivity (if contacts do not lie above collector junction)

unchanged

Hard:Thermal resistance (ICs)Emitter contact + access resistanceYield in deep submicron processesContact electromigration (?), dark-line defects (?)

Probably not as hard :Maintaining adequate breakdown for 3 V operation...

Frequency Limitsand Scaling Laws of (most) Electron Devices

bottomR

topR

lenght stripe/1

area/thickness/area

thickness

bottom

contacttop

R

RC

Applies whenever AC signals are removed though Ohmic contactsSemiconductor lasers avoid R/C/ limits by radiating through end facets

capacitanceresistance transit time

device bandwidth

applies to:transistors: BJTs & HBTs, MOSFETS & HEMTs, Schottky diodes, photodiodes, photo mixers, RTDs,

Mesa HBTs

Mesa DHBTs at the 500-600 nm Scaling Generation

1.3 m base-collector mesa1.7 m base-collector mesa

Zach Griffith

600 nm emitter width

40, VBR,CEO = 3.9 V. Emitter contact Rcont < 10 m2

Base : Rsheet = 610 /sq, Rcont = 4.6 m2 Collector : Rsheet = 12.1 /sq, Rcont = 8.4 m2

Vcb

= -0.3 V

0

2

4

6

8

10

0 2.5 5 7.5 10 12.50

5

10

15

20

25

C cb/A

e (fF/

m2 )

J e (mA/m2)

Ccb (fF)

-0.2 V

0.0 V

0.2 V

Vcb

= 0.6 V

Ajbc

= 1.3 x 6.5 m2

Ccb

/Ic=0.2 ps/V

0.4 ps/V

0.6 ps/V

0.8 ps/V

1.0 ps/V1.5ps/V

Ajbe

= 0.6 x 4.3 m2

0

5

10

15

20

25

30

35

109 1010 1011 1012

Gai

ns (d

B)

Frequency (Hz)

U

Ajbe

= 0.6 x 4.3 um2

Ic = 20.6 mA, V

ce = 1.53 V

Je = 8.0 mA/um2, V

cb= 0.6 V

ft = 450 GHz, f

max = 490 GHz

h21

10-12

10-10

10-8

10-6

10-4

0.01

0 0.25 0.5 0.75 1

I b, Ic (A

)

Vbe

(V)

VCB

= 0.0 V (dashed)

VCB

= 0.3 V (solid)

Ic

Ib

nc = 1.12

nb = 1.41

Gummel characteristics

InP DHBT: 600 nm lithography, 120 nm thick collector, 30 nm thick base

Zach Griffith

Average 50, BVCEO = 3.2 V, BVCBO = 3.4 V (Ic = 50 A)Emitter contact (from RF extraction), Rcont 8.6 m2

Base (from TLM) : Rsheet = 805 /sq, Rcont = 16 m2

Collector (from TLM) : Rsheet = 12.0 /sq, Rcont = 4.7 m2

InP DHBT: 600 nm lithography, 75 nm thick collector, 20 nm base

Peak f

Peak fmax

DC characteristics

RF characteristics

Aje = 0.65 4.3 m2 , Ib,step = 175 A

Zach Griffith

Variation of Transistor Bandwidth with Scaling

0

100

200

300

400

500

600

700

800

0 100 200 300 400 500 600 700 800

f max

(GH

z)

ft (GHz)

500 GHz400 GHz300 GHz200 GHz maxff

Updated July 5 2006

epitaxial scaling

epita

xial,

lithog

raph

ic,

& conta

ct re

sistan

ce

scali

ng

)( ),/( ),/( ),/(

hence , :digital

gain, associated ,F :amplifiers noise low

mW/ gain, associated PAE,

:amplifierspower

)11(

2/) (alone or

min

1max

max

max

max

cb

cbb

cex

ccb

clock

ττVIRVIRIVC

f

m

ff

ff

ffff

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?

?

7.5 mW output power

175 GHz Amplifiers with 300 GHz fmax Mesa DHBTs7 dB gain measured @ 175 GHz

2 fingers x 0.8 um x 12 um, ~250 GHz f, 300 GHz fmax , Vbr ~ 7V, ~ 3 mA/um2 current density

V. Paidi, Z. Griffith, M. Dahlström

-10

-5

0

5

10

15

140 150 160 170 180 190 200

S21

, S11

, S22

dB

Frequency, GHz

S21

S11

S22

7-dB small-signal gain at 176 GHz8.1 dBm output power at 6.3 dB gain

unitsdata

current steering

data emitter

followers

clock current steering

clock emitter

followerssize m2 0.5 x 3.5 0.5 x 4.5 0.5 x 4.5 0.5 x 5.5

currentdensity

mA/m2 6.9 4.4 4.4 4.4

Ccb/Ic psec / V 0.59 0.99 0.74 0.86

Vcb V 0.6 0 0.6 1.7

f GHz 301 260 301 280

fmax GHz 358 268 358 280

UCSB / RSC / GCS 150 GHz Static Frequency Dividers

-40

-30

-20

-10

0

10

20

0 20 40 60 80 100 120 140 160

Min

imum

inpu

t pow

er (d

Bm

)

frequency (GHz)

IC design: Z. Griffith, UCSBHBT design: RSC / UCSB / GCSIC Process / Fabrication: GCSTest: UCSB / RSC / Mayo

-80

-70

-60

-50

-40

-30

74.9975 74.9987 75.0000 75.0012 75.0025

Out

put P

ower

(dB

m)

frequency (GHz)

-90

-80

-70

-60

-50

-40

-30

-20

-10

0.00 19.00 38.00 57.00 76.00

Out

put P

ower

(dB

m)

frequency (GHz)

probe station chuck @ 25C

PDC,total = 659.8 mWdivider core without output buffer 594.7 mW

4:1 Mux in Vitesse VIP3 InP HBT Process

160 Gb/s

150 Gb/s

T. Swahn et al

250 nm scaling generation DHBTs

• 100 % I-line lithography• Emitter contact resistance reduced 40%: from 8.5 to 5 m2 • Base contact resistance is < 5 m2 --hard to measure • Recall, 1/8 m scaling generation needs 5 m2 emitter c

Zach Griffith

0.30 µm emitter junction, Wc/We ~ 1.6Zach Griffith

First mm-wave results with 250 nm InP DHBTs150 nm material250 nm emitter width

f = 420 GHzfmax = 650 GHz~6 V breakdown30 mW/um2 power handling

results to be presented postdeadline this conference, E. Lind, Z. Griffith et al

Erik Lind

Epitaxial scaling at 250 nm design rules

0

100

200

300

400

500

600

700

800

0 100 200 300 400 500 600 700 800

f max

(GH

z)

ft (GHz)

500 GHz400 GHz300 GHz200 GHz maxff

Updated July 5 2006

?

? 60 nm thick collector

process failurenew fab run in progress

100 nm thick collector

f / fmax, proj ~ 575/550 GHzat 250 nm emitter width

Zach Griffith

330 GHz Cascode Power Amplifiers In Design

Psat = 50 mW (17 dBm) 10-dB associated power gainuse 650 GHz fmax transistors

-5

0

5

10

15

20

0

0.05

0.1

0.15

0.2

0.25

-15 -10 -5 0 5 10

Gai

n (d

B),

Out

put P

ower

(dB

m)

PA

E (%

)

Input Power, dBm

PAE

Gain

Output Power

-10

-5

0

5

10

15

260 280 300 320 340 360

S21

, S11

, S22

( dB

)

Frequency, GHz

S21

S11

S22

Navin Parthasarathy

Manufacturable Process Flows

At a given scaling generation, intelligent choice of device geometry reduces extrinsic parasitics

Parasitic Reduction for Improved InP HBT Bandwidth

SiO2 SiO2

P base

N+ subcollector

N-thick extrinsic base : low resistancethin intrinsic base: low transit time

wide emitter contact: low resistancenarrow emitter junction: scaling (low Rbb/Ae)

wide base contacts: low resistancenarrow collector junction: low capacitance

Much more fully developed in Si…

Wr

LR bulk

bulk2ln2

LrR c

contact 2

These are planar approximations toradial contacts:

extrinsic base

extrinsicemitter

N+ subcollector

extrinsic base

bulk

contactbulk

WLR

ln34.12

mintotal,

→ greatly reduced access resistance

Polycrystalline Extrinsic Emitter D. Scott, Y. Wei

0

0.002

0.004

0.006

0.008

0.01

0.012

0.014

0 0.5 1 1.5

Ibstep

=100 uA

I C(A

)

VCE

(V)

Self-aligned, AE_junction

=0.3 um x 4 um

0

5

10

15

20

25

30

1 10 100 1000

IC=9.72 mA

VCE

=1.2 V

U, M

SG

/MA

G, h

21 (d

B),

K

Frequency (GHz)

U

h21MAG/MSG

K

fT=280 GHzf

MAX=148GHz

Emitter junction area: 0.3 x 4 m2

ApproachWide emitter contact for low emitter access resistanceThick extrinsic base for low base resistanceSelf-aligned refractory base contacts

Enabling TechnologyLow-resistance polycrystalline InAsIn-band Fermi-level pinning eliminates barriers

ChallengesVery complex processHydrogen passivationResistance of Refractory contacts

Self-aligned Sidewall Spacer (S3) Manufacturable HBT Process

Self-aligned contacts are critical to submicron device scaling. Eliminates lithography alignment tolerance.

RSC’s S3 HBT process utilizes electroplated contacts with dielectric sidewalls. Eliminates low yield liftoff processes from base-emitter junction formation.

Electroplated base contact is selectively deposited on the base semiconductor.

Process enables deep submicron scaling while maintaining high levels of performance and yield

Emitter Contact

Base Contact

Dielectric Sidewall

Simple S3 Device Process Flow

Electroplate emitter contact Etch emitter semiconductor

Dielectric sidewall deposition Base contact patterning

Selectively deposit base metal

S3 Process Flow

SEM Cross-Section of B-E Junction

10 11 120

10

20

30

40

Frequency (GHz)

|H21

|(red

), U

(blu

e) (d

B)

f = 405GHz fmax = 392 GHz

RF Gains

JE = 6.5 mA/um2

VCE = 1.5 V

Miguel Urteaga, Richard Pierson, Petra RowellKeisuke Shinohara, Berinder Brar

VIP-2 HBT structure: Dielectric Sidewall

Dielectric Spacer allows tightly controlled separation between Emitter and Base to minimize Rbx and Cbcx

B

C

Cross section

LayoutE B

E

C

Note that the basevia is “folded” on topof the transistor toreduce Cbc

Minh Le et al

G. He, J. Howard, M. Le, P. Partyka, B. Li, G. Kim, R. Hess, R. Bryie, R. Lee, S. Rustomji, J. Pepper, M. Kail, M. Helix, R. Elder, D. Jansen, N. Harff, J. Prairie, E. Daniel, and B. Gilbert, “Self-Aligned InP DHBT with ft and fmax over 300 GHz in a new manufacturable technology,” IEEE Electron Device Lett., vol. 25, no. 8, pp. 520–522, Aug. 2004.

Low-Power High-Speed Logic → Small Pad Capacitance

ECL with impedance-matched 50 Ohm bus:25 Ohm load→ switch 12 mA 12 mA x 7 x 4 V = 336 mW/latch

CML with impedance-matched 50 Ohm bus:25 Ohm load→ switch 12 mA 12 mA x 3 x 3 V = 108 mW/latch

Low-Power CML100 Ohm loaded → switch 3 mA 3 mA x 3 x 3 V = 27 mW/latch

base pad capacitance key parasitic in low power bipolar logicCML operates at lower Vce → reduced Kirk-effect-limited current

12 mA12 mA 12 mA

50 Ohm bus 50 Ohm 50 Ohm

12 mA

50 Ohm bus 50 Ohm 50 Ohm

50 Ohm bus100 Ohm

3 mA

3 mA 3 mA

padcbwiring CC ,low ,low power low @ speed High

100 Ohm

0

5

10

15

20

25

-0.4 -0.2 0.0 0.2 0.4 0.60.00

1.55

3.10

4.65

6.20

7.75

9.30

Ccb

(fF)

Vcb

(V)

Ccb / A

e (fF/um2)

mesa

implanted sub-collector

implanted sub-collector + pedestal

Ajbc

= 1.3 x 8.5 um2

Subcollector & Pedestal Implant

Fe

N+S.I.

N+

Epitaxial growth JunctionFabrication

N+ N+FeFe

N+S.I.

N+N+ N+Fe

Pedestal Implant

Fe

N+S.I.

N+N+ N+Fe

Fe Implant

S.I.

Fe

Subcollector Implant

N+S.I.

Fe

Subcollector implant eliminates Ccb in base pad area .

Pedestal further reduces Ccb.

Navin Parthasarathy

0

5

10

15

20

0 1 2 3 4 5 6 70

5

10

15

20

I c (mA)

VCE

(V)

Ib start

= 50 A

Ib step

= 100 A

~ 40

BVCEO

= 6.8V

0

5

10

15

20

25

30

35

109 1010 1011 1012

Gai

ns (d

B)

Frequency (Hz)

ft = 352 GHz, f

max = 403 GHz

Uh

21

10-12

10-10

10-8

10-6

10-4

0.01

0 0.2 0.4 0.6 0.8 1I b, I

c (A)

Vbe

(V)

VCB

= 0.3 V (solid)

VCB

= 0.0 V (dashed)

Ic

nc = 1.18

Ajbe

= 0.65 x 4.3 m2

Ib

50 pA

nb = 1.53

Without Ccb reduction

fmax = 51 GHz

Fe

N+S.I.

N+

Epitaxial growth JunctionFabrication

N+ N+FeFe

N+S.I.

N+N+ N+Fe

Pedestal Implant

Fe

N+S.I.

N+N+ N+Fe

Fe Implant

S.I.

Fe

Subcollector Implant

N+S.I.

Fe

With Pedestal

fmax = 61.2 GHz (measured)fmax ~ 100 GHz (simulated)Pdivider core, 31 mW(includes emitter follower buffers)

Device technology, other higher-speed circuits,

M. Urteaga, K. Shinohara, R. Pierson, P. Rowell, B. Brar, Z. Griffith, N. Parthasarathy, M. Rodwell" InP DHBT IC Technology with Implanted Collector-Pedestal and Electroplated Device Contacts" , submitted to IEEE CSIC Symposium

Low-Power IC Design: Z. Griffith, N. Parthasarathy, M. Rodwell, M. Urteaga, K. Shinohara, P. Rowell, R. Pierson, and B. Brar"An Ultra Low-Power ( ≤ 13.6 mW/latch) Static Frequency Divider in an InP/InGaAs DHBT Technology" , 2006 IEEE IMS Symposium

Ultra low power CML Static Frequency Divider: RSC S3 Process with Pedestal

Frequency Limits of Bipolar Integrated Circuits500 nm generation: Done ~475 GHz ft & fmax 150 GHz static dividers (digital ICs)

250 nm results coming very soon. expect ~225 GHz digital clock rate, 300-400 GHz amplifiers

125 nm devices are the next target . → 300 GHz digital clock rate, 600 GHz amplifiers

THz transistors will come The approach is scaling. The limits are contact & thermal resistance

serious challenge: volume applications to support development