Digital Design – Register-Transfer Level (RTL) Design

Digital Design – Register-Transfer Level (RTL) Design

Chapter 5 - Register-Transfer Level (RTL)

Design

2

Digital DesignRTL Design

Table 5.1 RTL Design Process

Step Description

Ste

p 1 Create a high-

level state machine

Describe the system’s desired behavior as a high-level state machine. The state machine consists of states and transitions. The state machine is “high-level” because the transition conditions and the state actions are more than just Boolean operations on bit inputs and outputs. The operations may be described in English (e.g., “turn on laser”) rather than as precise expressions or assignments of inputs and outputs (e.g., “L=1”).

Ste

p 2 Create a

datapathCreate a datapath to carry out the conditions and actions of the high-level state machine.

Ste

p 3 Connect the

datapath to a controller

Connect the datapath to a controller block. Connect all external inputs and outputs to either the controller block or the datapath block

Ste

p 4 Derive the

controller’s FSM

Convert the high-level state machine to a finite-state machine (FSM) of the controller, by replacing high-level conditions and actions with Boolean expressions and assignments involving actual controller inputs and outputs, which cause transfers and operations in the datapath.

3


Figure 5.1 Laser-based distance measurement.

object ofinterest

T (in seconds)

2D = T sec * 3x108 m/sec

Dlaser

sensor

Figure 5.2 Block diagram of the laser-based distance measurement system.

L

SD

to laser

from sensor

from button

to display

Laser-baseddistancemeasurer

Example 5.1 Laser-based distance measurer.

4



Step 1: Create a high-level state machine

S1 S2 S3

turn on laserenable timer

reflection not detected

reflectionS4

disable timerclear timer

S0

clear Dreg

S5

load Dreg withtimer value converted

turn off laser

to meters

button not pressed

buttonpressed detected

turn off laser

Outputs: L (bit), D (16 bits)Inputs: B, S (bits)

5


Step 2: Create a datapath

countclear

Q

Dctr: 16-bit

16

load Dreg: 16-bit

Q

I

D

up-counter register

Dreg_ld

Dctr_clr

Dctr_cnt

300 MHz clock

Datapath

clear

Dreg_clr


6


Step 3: Connect the datapath to a controller

B L

S

D

to laser

from sensorfrom button

to display

Controller

DatapathDreg_ld

Dctr_clr

Dctr_cnt

Dreg_clr

300 MHz Clock

(Imple-mentedFSM of

(Fig. 5.4)Fig. 5.6)

7


Step 4: Derive the controller’s FSM


B=0

S1 S2B=1 S3

L=1L=0

S=0

S=1 S4

L=0 L=0

S0

Dreg_clr=1

S5

L=0L=0

Dreg_ld=0Dctr_clr=0

Dctr_cnt=0

Dreg_clr=0

Dreg_ld=0Dctr_clr=1

Dctr_cnt=0

Dreg_clr=0

Dreg_ld=0Dctr_clr=0

Dctr_cnt=1

Dreg_clr=0

Dreg_ld=0Dctr_clr=0

Dctr_cnt=1

Dreg_clr=0

Dreg_ld=0Dctr_clr=0

Dctr_cnt=0

Dreg_clr=0

Dreg_ld=1Dctr_clr=0

Dctr_cnt=0(turn on laser) (disable timer)(clear timer)

(clear Dreg)(load Dreg)

(enable timer)(turn off laser)

(turn off laser)

Outputs: L, Dreg_clr, Dreg_ld, Dctr_clr, Dctr_cntInputs: B, S

8


Figure 5.7 FSM description of the controller for the laser-based distance measurer, using the convention that FSM outputs not explicitly

assigned a value in a state are implicitly assigned 0

B=0

S1 S2B=1 S3

L=1

S=0

S=1 S4

L=0

S0

Dreg_clr=1

S5

Dctr_clr=1Dctr_cnt=1 Dctr_cnt=1

Dctr_cnt=0 Dreg_ld=1

(turn on laser)(disable timer)(clear timer)(clear Dreg) (load Dreg)

(enable timer)(turn off laser)

Outputs : L, Dreg_clr, Dreg_ld, Dctr_clr, Dctr_cntInputs: B, S

9


Figure 5.8 A basic digital filter that outputs the average of the previous four inputs, assuming the input was steady at 180 for a long time

before the above sequence began, and stays at 182 for a long time after the sequence.

I Q

180

190

184

time time182 182

181

180

182 190 182 182 182 182180

180180 181 183 184 184 184 182180

Basicfilter

10


Figure 5.9 Writing the four registers in a round-robin manner to always maintain the previous four input values in the registers.

181 182 190 182 182 182 182180

cycle: 1 2 3 4 5 6 7 8

Ia Ib Ic Id

1 2 43

5 6 7 8

value on input I:

11


Figure 5.10 Datapath (right) and FSM description of the controller (left) for our basic filter.

Ia Ib Ic Id

I

8-bit adder 8-bit adder

8-bit adder

>>2

Qreg

Q

Datapath

S0

S1

S2 S3

S4

Ia_ld

Ib_ldIc_ldId_ld

Ireg_clr

Qreg_ld

Qreg_clrController

Ireg_clr=1Qreg_clr=1

Ia_ld=1

Qreg_ld=1

I b _ ld = 1Qreg_ld=1

Qreg_ld=1

Id_ld=1

Ic_ld=1Qreg_ld=1

8

8Basic Filter

12


Figure 5.11 High-level state machine of the sending half of a simple bus interface.

WaitMyAddress SendData

D = “Z” D=Q1(A=Faddr)and rd

((A=Faddr)and rd)’

rdrd’

Ql=Q

Inputs: rd (bit), Q (32 bits), A, Faddr (4 bits)Outputs: D (32 bits)Local register: Q1 (32 bits)

13


Figure 5.12 Bus interface timing diagram.

rd

D

clk

Z Q1 ZZ Q1

Inputs

StateOutputs

W W SD W W SD SD W

14


Figure 5.13 Datapath (right) and controller FSM description (left) for the simple bus interface.

QFaddrA

= (4-bit)

D

A_eq_Faddr

D_enDatapath

WaitMyAddress SendData

D_en=0 D_en=1A_eq_Faddrand rd

A_eq_Faddrand rd)’

Controller

rd 32

32

4 4

Bus interface

rdrd’Ql

Ql_ld

Ql_ld=1 Ql_ld=0

15


Figure 5.14 A key principle of video compression recognizes that successive frames have much similarity.

1 Mbyte 1 Mbyte

Frame1 Frame2

D ig it iz ed fra me 1 D igi t ize d fr am e2

1 Mbyte 0.01 Mbyte

Frame1 Frame2

D ig i t ized fra m e1 D iffe renc e of 2 from 1

16


Figure 5.15 Sum-of-absolute-differences (SAD) component: block diagram (left), and high-level state machine (right).

sum=0

Inputs: A, B (256-byte memory), go (bit)

Local registers: sum, sad_reg (32 bits), i (9 bits)

i<256sum=sum+abs(A[i]-B[i])i=i+1

Outputs: sad (32 bits)

sad_reg = sum

!(i<

256)

SAD

sad

A

B

go

i=0

go!goS0

S1

S2

S3

S4

17


Figure 5.16 SAD datapath and controller FSM.

sum=0 sum_clr=1

i<256 i_lt_256sum=sum+abs(A[i]-B[i])

i=i+1 i_inc=1

sad_reg = sum

!(i<

256)

!(i

_lt_

256)

i=0 i_clr=1

go!go

sad_reg

abs

sad_reg_ld

sad

ii_inc

i_clr

sum

sum_ld

sum_clr

AB_addr A_data B_data

-

+

AB_rd

<256i_lt_256

sum_ld=1; AB_rd=1

sad_reg_ld=1

go

S0

S1

S2

S3

S4

Controller Datapath

18


Figure 5.17 Results of a 5-tap FIR filter with c0=c1=c2=c3=c4=0.2 applied to a noisy signal.

-1.5

-1

-0.5

0

0.5

1

1.5

original

noisy

fir_avg_out

19


Figure 5.18 Adding a main signal, in1, to a carrier signal, in2, resulting in a composite signal in_total.

-2.5

-2

-1.5

-1

-0.5

0

0.5

1

1.5

2

2.5 in1

in2

in_total

20


Figure 5.19 Filtering out the carrier signal using a 7-tap FIR filter with constants 0.25, 0, 0, 0.5, 0, 0, 0.25. The slight delay in the output

signal typically poses no problem.

-2.5

-2

-1.5

-1

-0.5

0

0.5

1

1.5

2

2.5

in_total

fir_out

21


Figure 5.20 General block diagram of an FIR filter.

X Y3-tap FIR filter

clk

22


Figure 5.21 Beginning to build the datapath for the FIR filter -- inserting and connecting the x(t), x(t-1) and x(t-2) registers.

X Y

3-tap FIR filter

clk

x(t) x(t-1) x(t-2)

xt0 xt1 xt2

23


Figure 5.22 Extending the datapath for the FIR filter -- inserting and connecting the c0, c1, and c2 registers, along with the multipliers, for

each tap.

X

Y

3-tap FIR filter

clk

x(t) x(t-1) x(t-2)

xt0 xt1 xt2c0 c1 c2

24


Figure 5.23 Computing the output Y in the FIR filter as the sum of the tap products.

X

Y

3-tap FIR filter

clk

x(t) x(t-1) x(t-2)

xt0 xt1 xt2c0 c1 c2

25


Figure 5.24 Finalizing the FIR filter datapath with circuitry for loading the constant registers.

X

Y

3-tap FIR filter

clk

x(t) x(t-1) x(t-2)

xt0 xt1 xt2

c0 c1 c2

C

Ca0Ca1

2x4

3210

CL

e

yreg

26


Figure 5.25 C program description of a sum-of-absolute differences computation -- The C program may be easier to develop and easier to

understand than a state machine.

int SAD(byte A[256], byte B[256]) // not quite C syntax{

uint sum; short uint i;sum = 0;i = 0;while (i < 256) {

sum = sum + abs(A[i] - B[i]);i = i + 1;

}return(sum);

}

27


Figure 5.26 T for assignment statement.

target = expression;target = expression

if (cond) {// then stmts

}

cond

(then stmts)

!cond

(end)

if (cond) {// then stmts

}

cond(then stmts)

!cond

else {// else stmts

}

( else stmts)

(end)

while (cond) {// while stmts

}

cond(while stmts)

!cond

(end)

Figure 5.27 Template for if-then statement.

Figure 5.28 Template for if-then-else statement.

Figure 5.29 Template for while loop statement.

28


Figure 5.30 Behavioral-level design starting from C code.

Inputs: uint X, Y

if (X > Y) {

Outputs: uint Max

Max = X;}else {

Max = Y;}

X>Y

!(X>Y)

Max=X Max=Y

X>Y

!(X>Y)

(then stmts) ( else stmts)

(a) (b) (c)

(end) (end)

29


Figure 5.31 Behavioral-level design of the sum-of-absolute difference code.

Inputs: byte A[256],B[256]

uint sum; short uint i;

sum = 0;i = 0;while (i < 256) {

sum = sum + abs(A[i] - B[i]);i = i + 1;

}}

!go

!(!go)Outputs: int sadmain(){

while (1) {

while (!go);

}

!go go

sum=0

i = 0

i<256

!(i<256)

!go go

sum=0i = 0

(a)

(b)(c)

(d)

(e)

!go go

sum=0i = 0

while stmts

i<256

!(i<256)

(f)

!go go

sum=0i = 0

i = 0sum = sum + abs...

i<256

!(i<256)

(g)

!go go

sum=0i = 0

i = 0sum = sum + abs...

bit go;

sad = sum;

sad = sumsad = sum

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Digital Design – Register-Transfer Level (RTL) Design